Remove unused W6300 register accessors and internal functions
This commit is contained in:
@@ -563,258 +563,74 @@ void reg_write_buf(uint32_t addr_sel, uint8_t* buf, datasize_t len);
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uint16_t get_sn_tx_fsr(uint8_t sn);
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uint16_t get_sn_tx_fsr(uint8_t sn);
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uint16_t get_sn_rx_rsr(uint8_t sn);
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uint16_t get_sn_rx_rsr(uint8_t sn);
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inline uint8_t get_rtl() { return reg_read(REG_RTL); }
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uint16_t get_cidr() { return (((uint16_t)reg_read(REG_CIDR) | (((reg_read(REG_RTL)) & 0x0F) << 1)) << 8) + reg_read(offset_inc(REG_CIDR, 1)); }
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inline uint16_t get_cidr() { return (((uint16_t)reg_read(REG_CIDR) | (((reg_read(REG_RTL)) & 0x0F) << 1)) << 8) + reg_read(offset_inc(REG_CIDR, 1)); }
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uint8_t get_sysr() { return reg_read(REG_SYSR); }
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inline uint16_t get_ver() { return (((uint16_t)reg_read(REG_VER)) << 8) + reg_read(offset_inc(REG_VER, 1)); }
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uint8_t get_sycr0() { return reg_read(REG_SYCR0); }
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inline uint8_t get_sysr() { return reg_read(REG_SYSR); }
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void set_sycr0(uint8_t v) { reg_write(REG_SYCR0, v); }
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inline uint8_t get_sycr0() { return reg_read(REG_SYCR0); }
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void set_imr(uint8_t v) { reg_write(REG_IMR, v); }
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inline void set_sycr0(uint8_t v) { reg_write(REG_SYCR0, v); }
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void set_irclr(uint8_t v) { reg_write(REG_IRCLR, v); }
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inline uint8_t get_sycr1() { return reg_read(REG_SYCR1); }
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void set_simr(uint8_t v) { reg_write(REG_SIMR, v); }
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inline void set_sycr1(uint8_t v) { reg_write(REG_SYCR1, v); }
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void set_slimr(uint8_t v) { reg_write(REG_SLIMR, v); }
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inline uint16_t get_tcntr() { return (((uint16_t)reg_read(REG_TCNTR)) << 8) + reg_read(offset_inc(REG_TCNTR, 1)); }
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void set_slirclr(uint8_t v) { reg_write(REG_SLIRCLR, v); }
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inline void set_tcntrclr(uint8_t v) { reg_write(REG_TCNTRCLR, v); }
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void set_shar(uint8_t* v) { reg_write_buf(REG_SHAR, v, 6); }
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inline uint8_t get_ir() { return reg_read(REG_IR); }
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void get_shar(uint8_t* v) { reg_read_buf(REG_SHAR, v, 6); }
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inline uint8_t get_sir() { return reg_read(REG_SIR); }
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void set_gar(uint8_t* v) { reg_write_buf(REG_GAR, v, 4); }
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inline uint8_t get_slir() { return reg_read(REG_SLIR); }
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void get_gar(uint8_t* v) { reg_read_buf(REG_GAR, v, 4); }
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inline void set_imr(uint8_t v) { reg_write(REG_IMR, v); }
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void set_subr(uint8_t* v) { reg_write_buf(REG_SUBR, v, 4); }
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inline uint8_t get_imr() { return reg_read(REG_IMR); }
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void get_subr(uint8_t* v) { reg_read_buf(REG_SUBR, v, 4); }
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inline void set_irclr(uint8_t v) { reg_write(REG_IRCLR, v); }
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void set_sipr(uint8_t* v) { reg_write_buf(REG_SIPR, v, 4); }
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inline void set_ir(uint8_t v) { set_irclr(v); }
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void get_sipr(uint8_t* v) { reg_read_buf(REG_SIPR, v, 4); }
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inline void set_simr(uint8_t v) { reg_write(REG_SIMR, v); }
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void set_llar(uint8_t* v) { reg_write_buf(REG_LLAR, v, 16); }
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inline uint8_t get_simr() { return reg_read(REG_SIMR); }
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void get_llar(uint8_t* v) { reg_read_buf(REG_LLAR, v, 16); }
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inline void set_slimr(uint8_t v) { reg_write(REG_SLIMR, v); }
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void set_guar(uint8_t* v) { reg_write_buf(REG_GUAR, v, 16); }
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inline uint8_t get_slimr() { return reg_read(REG_SLIMR); }
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void get_guar(uint8_t* v) { reg_read_buf(REG_GUAR, v, 16); }
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inline void set_slirclr(uint8_t v) { reg_write(REG_SLIRCLR, v); }
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void set_sub6r(uint8_t* v) { reg_write_buf(REG_SUB6R, v, 16); }
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inline void set_slir(uint8_t v) { set_slirclr(v); }
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void get_sub6r(uint8_t* v) { reg_read_buf(REG_SUB6R, v, 16); }
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inline void set_slpsr(uint8_t v) { reg_write(REG_SLPSR, v); }
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void set_ga6r(uint8_t* v) { reg_write_buf(REG_GA6R, v, 16); }
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inline uint8_t get_slpsr() { return reg_read(REG_SLPSR); }
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void get_ga6r(uint8_t* v) { reg_read_buf(REG_GA6R, v, 16); }
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inline void set_slcr(uint8_t v) { reg_write(REG_SLCR, v); }
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void set_chplckr(uint8_t v) { reg_write(REG_CHPLCKR, v); }
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inline uint8_t get_slcr() { return reg_read(REG_SLCR); }
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void chip_lock() { set_chplckr(0xFF); }
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inline uint8_t get_physr() { return reg_read(REG_PHYSR); }
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void chip_unlock() { set_chplckr(0xCE); }
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inline void set_phyrar(uint8_t v) { reg_write(REG_PHYRAR, v); }
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void set_netlckr(uint8_t v) { reg_write(REG_NETLCKR, v); }
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inline uint8_t get_phyrar() { return reg_read(REG_PHYRAR); }
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void net_lock() { set_netlckr(0xC5); }
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inline void set_phydir(uint16_t v) {
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void net_unlock() { set_netlckr(0x3A); }
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reg_write(offset_inc(REG_PHYDIR, 1), (uint8_t)(v >> 8));
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reg_write(REG_PHYDIR, (uint8_t)v);
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}
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inline uint16_t get_phydor() { return (((uint16_t)reg_read(offset_inc(REG_PHYDOR, 1))) << 8) + reg_read(REG_PHYDOR); }
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inline void set_phyacr(uint8_t v) { reg_write(REG_PHYACR, v); }
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inline uint8_t get_phyacr() { return reg_read(REG_PHYACR); }
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inline void set_phydivr(uint8_t v) { reg_write(REG_PHYDIVR, v); }
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inline uint8_t get_phydivr() { return reg_read(REG_PHYDIVR); }
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inline void set_phycr0(uint8_t v) { reg_write(REG_PHYCR0, v); }
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inline void set_phycr1(uint8_t v) { reg_write(REG_PHYCR1, v); }
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inline uint8_t get_phycr1() { return reg_read(REG_PHYCR1); }
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inline void set_net4mr(uint8_t v) { reg_write(REG_NET4MR, v); }
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inline void set_net6mr(uint8_t v) { reg_write(REG_NET6MR, v); }
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inline void set_netmr(uint8_t v) { reg_write(REG_NETMR, v); }
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inline void set_netmr2(uint8_t v) { reg_write(REG_NETMR2, v); }
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inline uint8_t get_net4mr() { return reg_read(REG_NET4MR); }
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inline uint8_t get_net6mr() { return reg_read(REG_NET6MR); }
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inline uint8_t get_netmr() { return reg_read(REG_NETMR); }
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inline uint8_t get_netmr2() { return reg_read(REG_NETMR2); }
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inline void set_ptmr(uint8_t v) { reg_write(REG_PTMR, v); }
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inline uint8_t get_ptmr() { return reg_read(REG_PTMR); }
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inline void set_pmnr(uint8_t v) { reg_write(REG_PMNR, v); }
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inline uint8_t get_pmnr() { return reg_read(REG_PMNR); }
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inline void set_phar(uint8_t* v) { reg_write_buf(REG_PHAR, v, 6); }
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inline void get_phar(uint8_t* v) { reg_read_buf(REG_PHAR, v, 6); }
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inline void set_psidr(uint16_t v) {
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reg_write(REG_PSIDR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_PSIDR, 1), (uint8_t)v);
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}
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inline uint16_t get_psidr() { return (((uint16_t)reg_read(REG_PSIDR)) << 8) + reg_read(offset_inc(REG_PSIDR, 1)); }
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inline void set_pmrur(uint16_t v) {
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reg_write(REG_PMRUR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_PMRUR, 1), (uint8_t)v);
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}
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inline uint16_t get_pmrur() { return (((uint16_t)reg_read(REG_PMRUR)) << 8) + reg_read(offset_inc(REG_PMRUR, 1)); }
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inline void set_shar(uint8_t* v) { reg_write_buf(REG_SHAR, v, 6); }
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inline void get_shar(uint8_t* v) { reg_read_buf(REG_SHAR, v, 6); }
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inline void set_gar(uint8_t* v) { reg_write_buf(REG_GAR, v, 4); }
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inline void get_gar(uint8_t* v) { reg_read_buf(REG_GAR, v, 4); }
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inline void set_ga4r(uint8_t* v) { set_gar(v); }
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inline void get_ga4r(uint8_t* v) { get_gar(v); }
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inline void set_subr(uint8_t* v) { reg_write_buf(REG_SUBR, v, 4); }
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inline void get_subr(uint8_t* v) { reg_read_buf(REG_SUBR, v, 4); }
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inline void set_sub4r(uint8_t* v) { set_subr(v); }
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inline void get_sub4r(uint8_t* v) { get_subr(v); }
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inline void set_sipr(uint8_t* v) { reg_write_buf(REG_SIPR, v, 4); }
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inline void get_sipr(uint8_t* v) { reg_read_buf(REG_SIPR, v, 4); }
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inline void set_llar(uint8_t* v) { reg_write_buf(REG_LLAR, v, 16); }
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inline void get_llar(uint8_t* v) { reg_read_buf(REG_LLAR, v, 16); }
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inline void set_guar(uint8_t* v) { reg_write_buf(REG_GUAR, v, 16); }
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inline void get_guar(uint8_t* v) { reg_read_buf(REG_GUAR, v, 16); }
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inline void set_sub6r(uint8_t* v) { reg_write_buf(REG_SUB6R, v, 16); }
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inline void get_sub6r(uint8_t* v) { reg_read_buf(REG_SUB6R, v, 16); }
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inline void set_ga6r(uint8_t* v) { reg_write_buf(REG_GA6R, v, 16); }
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inline void get_ga6r(uint8_t* v) { reg_read_buf(REG_GA6R, v, 16); }
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inline void set_sldipr(uint8_t* v) { reg_write_buf(REG_SLDIPR, v, 4); }
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inline void set_sldip4r(uint8_t* v) { set_sldipr(v); }
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inline void get_sldipr(uint8_t* v) { reg_read_buf(REG_SLDIPR, v, 4); }
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inline void get_sldip4r(uint8_t* v) { get_sldipr(v); }
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inline void set_sldip6r(uint8_t* v) { reg_write_buf(REG_SLDIP6R, v, 16); }
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inline void get_sldip6r(uint8_t* v) { reg_read_buf(REG_SLDIP6R, v, 16); }
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inline void get_sldhar(uint8_t* v) { reg_read_buf(REG_SLDHAR, v, 6); }
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inline void set_pingidr(uint16_t v) {
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reg_write(REG_PINGIDR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_PINGIDR, 1), (uint8_t)v);
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}
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inline uint16_t get_pingidr() { return ((uint16_t)(reg_read(REG_PINGIDR) << 8)) + reg_read(offset_inc(REG_PINGIDR, 1)); }
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inline void set_pingseqr(uint16_t v) {
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reg_write(REG_PINGSEQR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_PINGSEQR, 1), (uint8_t)v);
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}
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inline uint16_t get_pingseqr() { return ((uint16_t)(reg_read(REG_PINGSEQR) << 8)) + reg_read(offset_inc(REG_PINGSEQR, 1)); }
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inline void get_uipr(uint8_t* v) { reg_read_buf(REG_UIPR, v, 4); }
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inline void get_uip4r(uint8_t* v) { get_uipr(v); }
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inline uint16_t get_uportr() { return (((uint16_t)reg_read(REG_UPORTR)) << 8) + reg_read(offset_inc(REG_UPORTR, 1)); }
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inline uint16_t get_uport4r() { return get_uportr(); }
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inline void get_uip6r(uint8_t* v) { reg_read_buf(REG_UIP6R, v, 16); }
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inline uint16_t get_uport6r() { return (((uint16_t)reg_read(REG_UPORT6R)) << 8) + reg_read(offset_inc(REG_UPORT6R, 1)); }
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inline void set_intptmr(uint16_t v) {
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reg_write(REG_INTPTMR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_INTPTMR, 1), (uint8_t)v);
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}
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inline uint16_t get_intptmr() { return (((uint16_t)reg_read(REG_INTPTMR)) << 8) + reg_read(offset_inc(REG_INTPTMR, 1)); }
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inline uint8_t get_plr() { return reg_read(REG_PLR); }
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inline uint8_t get_pfr() { return reg_read(REG_PFR); }
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inline uint32_t get_vltr() {
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return (((uint32_t)reg_read(REG_VLTR)) << 24) +
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(((uint32_t)reg_read(offset_inc(REG_VLTR, 1))) << 16) +
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(((uint32_t)reg_read(offset_inc(REG_VLTR, 2))) << 8) +
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((uint32_t)reg_read(offset_inc(REG_VLTR, 3)));
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}
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inline uint32_t get_pltr() {
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return (((uint32_t)reg_read(REG_PLTR)) << 24) +
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(((uint32_t)reg_read(offset_inc(REG_PLTR, 1))) << 16) +
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(((uint32_t)reg_read(offset_inc(REG_PLTR, 2))) << 8) +
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((uint32_t)reg_read(offset_inc(REG_PLTR, 3)));
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}
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inline void get_par(uint8_t* v) { reg_read_buf(REG_PAR, v, 16); }
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inline void set_icmp6blkr(uint8_t v) { reg_write(REG_ICMP6BLKR, v); }
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inline uint8_t get_icmp6blkr() { return reg_read(REG_ICMP6BLKR); }
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inline void set_chplckr(uint8_t v) { reg_write(REG_CHPLCKR, v); }
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inline uint8_t get_chplckr() { return (get_sysr() & SYSR_CHPL) >> 7; }
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inline void chip_lock() { set_chplckr(0xFF); }
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inline void chip_unlock() { set_chplckr(0xCE); }
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inline void set_netlckr(uint8_t v) { reg_write(REG_NETLCKR, v); }
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inline uint8_t get_netlckr() { return (get_sysr() & SYSR_NETL) >> 6; }
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inline void net_lock() { set_netlckr(0xC5); }
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inline void net_unlock() { set_netlckr(0x3A); }
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inline void set_phylckr(uint8_t v) { reg_write(REG_PHYLCKR, v); }
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inline uint8_t get_phylckr() { return (get_sysr() & SYSR_PHYL) >> 5; }
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inline void phy_lock() { set_phylckr(0xFF); }
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inline void phy_unlock() { set_phylckr(0x53); }
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inline void set_rtr(uint16_t v) {
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reg_write(REG_RTR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_RTR, 1), (uint8_t)v);
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}
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inline uint16_t get_rtr() { return (((uint16_t)reg_read(REG_RTR)) << 8) + reg_read(offset_inc(REG_RTR, 1)); }
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inline void set_rcr(uint8_t v) { reg_write(REG_RCR, v); }
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inline uint8_t get_rcr() { return reg_read(REG_RCR); }
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inline void set_slrtr(uint16_t v) {
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reg_write(REG_SLRTR, (uint8_t)(v >> 8));
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reg_write(offset_inc(REG_SLRTR, 1), (uint8_t)v);
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}
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inline uint16_t get_slrtr() { return (((uint16_t)reg_read(REG_SLRTR)) << 8) + reg_read(offset_inc(REG_SLRTR, 1)); }
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inline void set_slrcr(uint8_t v) { reg_write(REG_SLRCR, v); }
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inline uint8_t get_slrcr() { return reg_read(REG_SLRCR); }
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inline void set_slhopr(uint8_t v) { reg_write(REG_SLHOPR, v); }
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inline uint8_t get_slhopr() { return reg_read(REG_SLHOPR); }
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inline void set_sn_mr(uint8_t sn, uint8_t v) { reg_write(REG_SN_MR(sn), v); }
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void set_sn_mr(uint8_t sn, uint8_t v) { reg_write(REG_SN_MR(sn), v); }
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inline uint8_t get_sn_mr(uint8_t sn) { return reg_read(REG_SN_MR(sn)); }
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uint8_t get_sn_mr(uint8_t sn) { return reg_read(REG_SN_MR(sn)); }
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inline void set_sn_psr(uint8_t sn, uint8_t v) { reg_write(REG_SN_PSR(sn), v); }
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void set_sn_cr(uint8_t sn, uint8_t v) { reg_write(REG_SN_CR(sn), v); }
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inline uint8_t get_sn_psr(uint8_t sn) { return reg_read(REG_SN_PSR(sn)); }
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uint8_t get_sn_cr(uint8_t sn) { return reg_read(REG_SN_CR(sn)); }
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inline void set_sn_cr(uint8_t sn, uint8_t v) { reg_write(REG_SN_CR(sn), v); }
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uint8_t get_sn_ir(uint8_t sn) { return reg_read(REG_SN_IR(sn)); }
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inline uint8_t get_sn_cr(uint8_t sn) { return reg_read(REG_SN_CR(sn)); }
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void set_sn_irclr(uint8_t sn, uint8_t v) { reg_write(REG_SN_IRCLR(sn), v); }
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inline uint8_t get_sn_ir(uint8_t sn) { return reg_read(REG_SN_IR(sn)); }
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void set_sn_ir(uint8_t sn, uint8_t v) { set_sn_irclr(sn, v); }
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inline void set_sn_imr(uint8_t sn, uint8_t v) { reg_write(REG_SN_IMR(sn), v); }
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uint8_t get_sn_sr(uint8_t sn) { return reg_read(REG_SN_SR(sn)); }
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inline uint8_t get_sn_imr(uint8_t sn) { return reg_read(REG_SN_IMR(sn)); }
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void set_sn_portr(uint8_t sn, uint16_t v) {
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inline void set_sn_irclr(uint8_t sn, uint8_t v) { reg_write(REG_SN_IRCLR(sn), v); }
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inline void set_sn_ir(uint8_t sn, uint8_t v) { set_sn_irclr(sn, v); }
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inline uint8_t get_sn_sr(uint8_t sn) { return reg_read(REG_SN_SR(sn)); }
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||||||
inline uint8_t get_sn_esr(uint8_t sn) { return reg_read(REG_SN_ESR(sn)); }
|
|
||||||
inline void set_sn_pnr(uint8_t sn, uint8_t v) { reg_write(REG_SN_PNR(sn), v); }
|
|
||||||
inline void set_sn_nhr(uint8_t sn, uint8_t v) { set_sn_pnr(sn, v); }
|
|
||||||
inline uint8_t get_sn_pnr(uint8_t sn) { return reg_read(REG_SN_PNR(sn)); }
|
|
||||||
inline uint8_t get_sn_nhr(uint8_t sn) { return get_sn_pnr(sn); }
|
|
||||||
inline void set_sn_tosr(uint8_t sn, uint8_t v) { reg_write(REG_SN_TOSR(sn), v); }
|
|
||||||
inline uint8_t get_sn_tosr(uint8_t sn) { return reg_read(REG_SN_TOSR(sn)); }
|
|
||||||
inline uint8_t get_sn_tos(uint8_t sn) { return get_sn_tosr(sn); }
|
|
||||||
inline void set_sn_tos(uint8_t sn, uint8_t v) { set_sn_tosr(sn, v); }
|
|
||||||
inline void set_sn_ttlr(uint8_t sn, uint8_t v) { reg_write(REG_SN_TTLR(sn), v); }
|
|
||||||
inline uint8_t get_sn_ttlr(uint8_t sn) { return reg_read(REG_SN_TTLR(sn)); }
|
|
||||||
inline void set_sn_ttl(uint8_t sn, uint8_t v) { set_sn_ttlr(sn, v); }
|
|
||||||
inline uint8_t get_sn_ttl(uint8_t sn) { return get_sn_ttlr(sn); }
|
|
||||||
inline void set_sn_hopr(uint8_t sn, uint8_t v) { set_sn_ttlr(sn, v); }
|
|
||||||
inline uint8_t get_sn_hopr(uint8_t sn) { return get_sn_ttlr(sn); }
|
|
||||||
inline void set_sn_frgr(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_FRGR(sn), (uint8_t)(v >> 8));
|
|
||||||
reg_write(offset_inc(REG_SN_FRGR(sn), 1), (uint8_t)v);
|
|
||||||
}
|
|
||||||
inline uint16_t get_sn_frgr(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_FRGR(sn))) << 8) + reg_read(offset_inc(REG_SN_FRGR(sn), 1)); }
|
|
||||||
inline void set_sn_mssr(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_MSSR(sn), (uint8_t)(v >> 8));
|
|
||||||
reg_write(offset_inc(REG_SN_MSSR(sn), 1), (uint8_t)v);
|
|
||||||
}
|
|
||||||
inline uint16_t get_sn_mssr(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_MSSR(sn))) << 8) + reg_read(offset_inc(REG_SN_MSSR(sn), 1)); }
|
|
||||||
inline void set_sn_portr(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_PORTR(sn), (uint8_t)(v >> 8));
|
reg_write(REG_SN_PORTR(sn), (uint8_t)(v >> 8));
|
||||||
reg_write(offset_inc(REG_SN_PORTR(sn), 1), (uint8_t)v);
|
reg_write(offset_inc(REG_SN_PORTR(sn), 1), (uint8_t)v);
|
||||||
}
|
}
|
||||||
inline uint16_t get_sn_portr(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_PORTR(sn))) << 8) + reg_read(offset_inc(REG_SN_PORTR(sn), 1)); }
|
void set_sn_dhar(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DHAR(sn), v, 6); }
|
||||||
inline void set_sn_dhar(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DHAR(sn), v, 6); }
|
void set_sn_dipr(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DIPR(sn), v, 4); }
|
||||||
inline void get_sn_dhar(uint8_t sn, uint8_t* v) { reg_read_buf(REG_SN_DHAR(sn), v, 6); }
|
void set_sn_dip6r(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DIP6R(sn), v, 16); }
|
||||||
inline void set_sn_dipr(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DIPR(sn), v, 4); }
|
void set_sn_dportr(uint8_t sn, uint16_t v) {
|
||||||
inline void get_sn_dipr(uint8_t sn, uint8_t* v) { reg_read_buf(REG_SN_DIPR(sn), v, 4); }
|
|
||||||
inline void set_sn_dip4r(uint8_t sn, uint8_t* v) { set_sn_dipr(sn, v); }
|
|
||||||
inline void get_sn_dip4r(uint8_t sn, uint8_t* v) { get_sn_dipr(sn, v); }
|
|
||||||
inline void set_sn_dip6r(uint8_t sn, uint8_t* v) { reg_write_buf(REG_SN_DIP6R(sn), v, 16); }
|
|
||||||
inline void get_sn_dip6r(uint8_t sn, uint8_t* v) { reg_read_buf(REG_SN_DIP6R(sn), v, 16); }
|
|
||||||
inline void set_sn_dportr(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_DPORTR(sn), (uint8_t)(v >> 8));
|
reg_write(REG_SN_DPORTR(sn), (uint8_t)(v >> 8));
|
||||||
reg_write(offset_inc(REG_SN_DPORTR(sn), 1), (uint8_t)v);
|
reg_write(offset_inc(REG_SN_DPORTR(sn), 1), (uint8_t)v);
|
||||||
}
|
}
|
||||||
inline uint16_t get_sn_dportr(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_DPORTR(sn))) << 8) + reg_read(offset_inc(REG_SN_DPORTR(sn), 1)); }
|
void set_sn_mr2(uint8_t sn, uint8_t v) { reg_write(REG_SN_MR2(sn), v); }
|
||||||
inline uint16_t get_sn_dport(uint8_t sn) { return get_sn_dportr(sn); }
|
void set_sn_tx_bsr(uint8_t sn, uint8_t v) { reg_write(REG_SN_TX_BSR(sn), v); }
|
||||||
inline void set_sn_dport(uint8_t sn, uint16_t v) { set_sn_dportr(sn, v); }
|
void set_sn_txbuf_size(uint8_t sn, uint8_t v) { set_sn_tx_bsr(sn, v); }
|
||||||
inline void set_sn_mr2(uint8_t sn, uint8_t v) { reg_write(REG_SN_MR2(sn), v); }
|
uint8_t get_sn_tx_bsr(uint8_t sn) { return reg_read(REG_SN_TX_BSR(sn)); }
|
||||||
inline uint8_t get_sn_mr2(uint8_t sn) { return reg_read(REG_SN_MR2(sn)); }
|
uint16_t get_sn_tx_max(uint8_t sn) { return get_sn_tx_bsr(sn) << 10; }
|
||||||
inline void set_sn_rtr(uint8_t sn, uint16_t v) {
|
uint16_t get_sn_tx_wr(uint8_t sn) { return ((uint16_t)reg_read(REG_SN_TX_WR(sn)) << 8) + reg_read(offset_inc(REG_SN_TX_WR(sn), 1)); }
|
||||||
reg_write(REG_SN_RTR(sn), (uint8_t)(v >> 8));
|
void set_sn_tx_wr(uint8_t sn, uint16_t v) {
|
||||||
reg_write(offset_inc(REG_SN_RTR(sn), 1), (uint8_t)v);
|
|
||||||
}
|
|
||||||
inline uint16_t get_sn_rtr(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_RTR(sn))) << 8) + reg_read(offset_inc(REG_SN_RTR(sn), 1)); }
|
|
||||||
inline void set_sn_rcr(uint8_t sn, uint8_t v) { reg_write(REG_SN_RCR(sn), v); }
|
|
||||||
inline uint8_t get_sn_rcr(uint8_t sn) { return reg_read(REG_SN_RCR(sn)); }
|
|
||||||
inline void set_sn_kpalvtr(uint8_t sn, uint8_t v) { reg_write(REG_SN_KPALVTR(sn), v); }
|
|
||||||
inline uint8_t get_sn_kpalvtr(uint8_t sn) { return reg_read(REG_SN_KPALVTR(sn)); }
|
|
||||||
inline void set_sn_tx_bsr(uint8_t sn, uint8_t v) { reg_write(REG_SN_TX_BSR(sn), v); }
|
|
||||||
inline void set_sn_txbuf_size(uint8_t sn, uint8_t v) { set_sn_tx_bsr(sn, v); }
|
|
||||||
inline uint8_t get_sn_tx_bsr(uint8_t sn) { return reg_read(REG_SN_TX_BSR(sn)); }
|
|
||||||
inline uint8_t get_sn_txbuf_size(uint8_t sn) { return get_sn_tx_bsr(sn); }
|
|
||||||
inline uint16_t get_sn_tx_max(uint8_t sn) { return get_sn_tx_bsr(sn) << 10; }
|
|
||||||
|
|
||||||
inline uint16_t get_sn_tx_rd(uint8_t sn) { return (((uint16_t)reg_read(REG_SN_TX_RD(sn))) << 8) + reg_read(offset_inc(REG_SN_TX_RD(sn), 1)); }
|
|
||||||
inline void set_sn_tx_wr(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_TX_WR(sn), (uint8_t)(v >> 8));
|
reg_write(REG_SN_TX_WR(sn), (uint8_t)(v >> 8));
|
||||||
reg_write(offset_inc(REG_SN_TX_WR(sn), 1), (uint8_t)v);
|
reg_write(offset_inc(REG_SN_TX_WR(sn), 1), (uint8_t)v);
|
||||||
}
|
}
|
||||||
inline uint16_t get_sn_tx_wr(uint8_t sn) { return ((uint16_t)reg_read(REG_SN_TX_WR(sn)) << 8) + reg_read(offset_inc(REG_SN_TX_WR(sn), 1)); }
|
void set_sn_rx_bsr(uint8_t sn, uint8_t v) { reg_write(REG_SN_RX_BSR(sn), v); }
|
||||||
inline void set_sn_rx_bsr(uint8_t sn, uint8_t v) { reg_write(REG_SN_RX_BSR(sn), v); }
|
void set_sn_rxbuf_size(uint8_t sn, uint8_t v) { set_sn_rx_bsr(sn, v); }
|
||||||
inline void set_sn_rxbuf_size(uint8_t sn, uint8_t v) { set_sn_rx_bsr(sn, v); }
|
void set_sn_rx_rd(uint8_t sn, uint16_t v) {
|
||||||
inline uint8_t get_sn_rx_bsr(uint8_t sn) { return reg_read(REG_SN_RX_BSR(sn)); }
|
|
||||||
inline uint8_t get_sn_rxbuf_size(uint8_t sn) { return get_sn_rx_bsr(sn); }
|
|
||||||
inline uint16_t get_sn_rx_max(uint8_t sn) { return get_sn_rx_bsr(sn) << 10; }
|
|
||||||
|
|
||||||
inline void set_sn_rx_rd(uint8_t sn, uint16_t v) {
|
|
||||||
reg_write(REG_SN_RX_RD(sn), (uint8_t)(v >> 8));
|
reg_write(REG_SN_RX_RD(sn), (uint8_t)(v >> 8));
|
||||||
reg_write(offset_inc(REG_SN_RX_RD(sn), 1), (uint8_t)v);
|
reg_write(offset_inc(REG_SN_RX_RD(sn), 1), (uint8_t)v);
|
||||||
}
|
}
|
||||||
inline uint16_t get_sn_rx_rd(uint8_t sn) { return ((uint16_t)reg_read(REG_SN_RX_RD(sn)) << 8) + reg_read(offset_inc(REG_SN_RX_RD(sn), 1)); }
|
uint16_t get_sn_rx_rd(uint8_t sn) { return ((uint16_t)reg_read(REG_SN_RX_RD(sn)) << 8) + reg_read(offset_inc(REG_SN_RX_RD(sn), 1)); }
|
||||||
inline uint16_t get_sn_rx_wr(uint8_t sn) { return ((uint16_t)reg_read(REG_SN_RX_WR(sn)) << 8) + reg_read(offset_inc(REG_SN_RX_WR(sn), 1)); }
|
|
||||||
static critical_section_t g_cris_sec;
|
static critical_section_t g_cris_sec;
|
||||||
|
|
||||||
void cris_enter() {
|
void cris_enter() {
|
||||||
@@ -907,10 +723,6 @@ void recv_ignore(uint8_t sn, uint16_t len) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
} // namespace
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
void soft_reset() {
|
void soft_reset() {
|
||||||
uint8_t gw[4], sn[4], sip[4], mac[6];
|
uint8_t gw[4], sn[4], sip[4], mac[6];
|
||||||
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
||||||
@@ -951,6 +763,36 @@ int8_t init_buffers(std::span<const uint8_t> txsize, std::span<const uint8_t> rx
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
constexpr uint16_t SOCK_ANY_PORT_NUM = 0xC000;
|
||||||
|
|
||||||
|
uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
|
||||||
|
uint16_t sock_io_mode_bits = 0;
|
||||||
|
uint16_t sock_is_sending = 0;
|
||||||
|
uint16_t sock_remained_size[sock_count] = {0,};
|
||||||
|
uint8_t sock_pack_info[sock_count] = {0,};
|
||||||
|
|
||||||
|
#define FAIL(e) return std::unexpected(sock_error::e)
|
||||||
|
#define CHECK_SOCKNUM() do { if(sn >= sock_count) FAIL(sock_num); } while(0)
|
||||||
|
#define CHECK_SOCKMODE(mode) do { if((get_sn_mr(sn) & 0x0F) != mode) FAIL(sock_mode); } while(0)
|
||||||
|
#define CHECK_SOCKDATA() do { if(len == 0) FAIL(data_len); } while(0)
|
||||||
|
#define CHECK_IPZERO(addr, addrlen) do { uint16_t ipzero=0; for(uint8_t i=0; i<addrlen; i++) ipzero += (uint16_t)addr[i]; if(ipzero == 0) FAIL(ip_invalid); } while(0)
|
||||||
|
|
||||||
|
std::expected<void, sock_error> close(socket_id sid) {
|
||||||
|
uint8_t sn = static_cast<uint8_t>(sid);
|
||||||
|
CHECK_SOCKNUM();
|
||||||
|
set_sn_cr(sn, SN_CR_CLOSE);
|
||||||
|
while (get_sn_cr(sn));
|
||||||
|
set_sn_ir(sn, 0xFF);
|
||||||
|
sock_io_mode_bits &= ~(1 << sn);
|
||||||
|
sock_is_sending &= ~(1 << sn);
|
||||||
|
sock_remained_size[sn] = 0;
|
||||||
|
sock_pack_info[sn] = PACK_NONE;
|
||||||
|
while (get_sn_sr(sn) != SOCK_CLOSED);
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace
|
||||||
|
|
||||||
void clear_interrupt(intr_kind intr) {
|
void clear_interrupt(intr_kind intr) {
|
||||||
set_irclr((uint8_t)intr);
|
set_irclr((uint8_t)intr);
|
||||||
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
||||||
@@ -966,39 +808,6 @@ void set_interrupt_mask(intr_kind intr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
constexpr uint16_t SOCK_ANY_PORT_NUM = 0xC000;
|
|
||||||
|
|
||||||
static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
|
|
||||||
static uint16_t sock_io_mode_bits = 0;
|
|
||||||
static uint16_t sock_is_sending = 0;
|
|
||||||
static uint16_t sock_remained_size[sock_count] = {0,};
|
|
||||||
uint8_t sock_pack_info[sock_count] = {0,};
|
|
||||||
|
|
||||||
#define FAIL(e) return std::unexpected(sock_error::e)
|
|
||||||
#define CHECK_SOCKNUM() do { if(sn >= sock_count) FAIL(sock_num); } while(0)
|
|
||||||
#define CHECK_SOCKMODE(mode) do { if((get_sn_mr(sn) & 0x0F) != mode) FAIL(sock_mode); } while(0)
|
|
||||||
#define CHECK_TCPMODE() do { if((get_sn_mr(sn) & 0x03) != 0x01) FAIL(sock_mode); } while(0)
|
|
||||||
#define CHECK_UDPMODE() do { if((get_sn_mr(sn) & 0x03) != 0x02) FAIL(sock_mode); } while(0)
|
|
||||||
#define CHECK_IPMODE() do { if((get_sn_mr(sn) & 0x07) != 0x03) FAIL(sock_mode); } while(0)
|
|
||||||
#define CHECK_DGRAMMODE() do { if(get_sn_mr(sn) == SN_MR_CLOSED) FAIL(sock_mode); if((get_sn_mr(sn) & 0x03) == 0x01) FAIL(sock_mode); } while(0)
|
|
||||||
#define CHECK_SOCKINIT() do { if((get_sn_sr(sn) != SOCK_INIT)) FAIL(sock_init); } while(0)
|
|
||||||
#define CHECK_SOCKDATA() do { if(len == 0) FAIL(data_len); } while(0)
|
|
||||||
#define CHECK_IPZERO(addr, addrlen) do { uint16_t ipzero=0; for(uint8_t i=0; i<addrlen; i++) ipzero += (uint16_t)addr[i]; if(ipzero == 0) FAIL(ip_invalid); } while(0)
|
|
||||||
|
|
||||||
static std::expected<void, sock_error> close(socket_id sid) {
|
|
||||||
uint8_t sn = static_cast<uint8_t>(sid);
|
|
||||||
CHECK_SOCKNUM();
|
|
||||||
set_sn_cr(sn, SN_CR_CLOSE);
|
|
||||||
while (get_sn_cr(sn));
|
|
||||||
set_sn_ir(sn, 0xFF);
|
|
||||||
sock_io_mode_bits &= ~(1 << sn);
|
|
||||||
sock_is_sending &= ~(1 << sn);
|
|
||||||
sock_remained_size[sn] = 0;
|
|
||||||
sock_pack_info[sn] = PACK_NONE;
|
|
||||||
while (get_sn_sr(sn) != SOCK_CLOSED);
|
|
||||||
return {};
|
|
||||||
}
|
|
||||||
|
|
||||||
std::expected<socket_id, sock_error> open_socket(socket_id sid, protocol proto, port_num port, sock_flag flag) {
|
std::expected<socket_id, sock_error> open_socket(socket_id sid, protocol proto, port_num port, sock_flag flag) {
|
||||||
uint8_t sn = static_cast<uint8_t>(sid);
|
uint8_t sn = static_cast<uint8_t>(sid);
|
||||||
uint16_t p = static_cast<uint16_t>(port);
|
uint16_t p = static_cast<uint16_t>(port);
|
||||||
|
|||||||
Reference in New Issue
Block a user