Add W6300 ethernet initialization
This commit is contained in:
Ian Gulliver
273
lib/w6300/ioLibrary/W6300/w6300.c
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273
lib/w6300/ioLibrary/W6300/w6300.c
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//*****************************************************************************
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//
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//! \file W6300.c
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//! \brief W6300 HAL Implements file.
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//! \version 1.0.0
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//! \date 2019/01/01
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//! \par Revision history
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//! <2019/01/01> 1st Release
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//! \author MidnightCow
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//! \copyright
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//!
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//! Copyright (c) 2019, WIZnet Co., LTD.
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//!
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//! Permission is hereby granted, free of charge, to any person obtaining a copy
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//! of this software and associated documentation files (the "Software"), to deal
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//! in the Software without restriction, including without limitation the rights
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//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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//! copies of the Software, and to permit persons to whom the Software is
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//! furnished to do so, subject to the following conditions:
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//!
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//! The above copyright notice and this permission notice shall be included in
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//! all copies or substantial portions of the Software.
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//!
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//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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//! SOFTWARE.
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//!
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//*****************************************************************************
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#include "w6300.h"
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#if 0
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#define _WIZCHIP_SPI_VDM_OP_ 0x00
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#define _WIZCHIP_SPI_FDM_LEN1_ 0x01
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#define _WIZCHIP_SPI_FDM_LEN2_ 0x02
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#define _WIZCHIP_SPI_FDM_LEN4_ 0x03
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#endif
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//
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// If you want to use SPI FDM mode, Feel free contact to WIZnet.
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// http://forum.wiznet.io
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//
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#if _WIZCHIP_ == 6300
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////////////////////////////////////////////////////////////////////////////////////////
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#define _W6300_SPI_OP_ _WIZCHIP_SPI_VDM_OP_
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#define _W6300_SPI_READ_ (0x00 << 5) ///< SPI interface Read operation in Control Phase
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#define _W6300_SPI_WRITE_ (0x01 << 5) ///< SPI interface Write operation in Control Phase
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//////////////////////////////////////////////////
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void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[4];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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tAD[3] = wb;
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 4, 1);
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#else //w6300 QSPI MODE
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, &wb, 1);
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#endif
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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}
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uint8_t WIZCHIP_READ(uint32_t AddrSel) {
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//uint8_t ret;
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uint8_t ret[2] = {0,};
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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ret[0] = WIZCHIP.IF.BUS._read_data(IDM_DR);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_READ_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, ret, 1);
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#endif
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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return ret[0];
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}
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void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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WIZCHIP.IF.BUS._write_data_buf(IDM_DR, pBuf, len, 0);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, pBuf, len);//by_lihan
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//qspi_write_buf(opcode, ADDR, pBuf, len);
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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#endif
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}
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void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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uint8_t ret;
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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WIZCHIP.IF.BUS._read_data_buf(IDM_DR, pBuf, len, 0);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_READ_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, pBuf, len);//by_lihan
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//qspi_read_buf(opcode, ADDR, pBuf, len);
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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#endif
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}
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uint16_t getSn_TX_FSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_TX_FSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_FSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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uint16_t getSn_RX_RSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_RX_RSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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uint16_t ptr = 0;
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uint32_t addrsel = 0;
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ptr = getSn_TX_WR(sn);
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addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
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WIZCHIP_WRITE_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_TX_WR(sn, ptr);
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}
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#if 0
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#define ETHERNET_BUF_MAX_SIZE_TEMP (1024 * 32 )
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void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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uint16_t ptr = 0;
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uint32_t addrsel = 0;
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if (len == 0) {
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return;
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}
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ptr = getSn_RX_RD(sn);
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if (ptr + len > 0xFFFF) {
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addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
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uint16_t size = 0xFFFF - ptr;
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WIZCHIP_READ_BUF(addrsel, wizdata, size);
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wizdata += size;
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size = len - size;
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addrsel = WIZCHIP_RXBUF_BLOCK(sn);
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WIZCHIP_READ_BUF(addrsel, wizdata, size);
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} else {
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addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
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WIZCHIP_READ_BUF(addrsel, wizdata, len);
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}
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ptr += len;
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ptr %= 0xFFFF ;
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setSn_RX_RD(sn, ptr);
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}
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#else
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void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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uint16_t ptr = 0;
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uint32_t addrsel = 0;
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if (len == 0) {
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return;
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}
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ptr = getSn_RX_RD(sn);
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addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
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WIZCHIP_READ_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_RX_RD(sn, ptr);
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}
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#endif
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void wiz_recv_ignore(uint8_t sn, uint16_t len) {
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setSn_RX_RD(sn, getSn_RX_RD(sn) + len);
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}
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#if 1
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// 20231019 taylor
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void wiz_delay_ms(uint32_t milliseconds) {
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uint32_t i;
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for (i = 0 ; i < milliseconds ; i++) {
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//Write any values to clear the TCNTCLKR register
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setTCNTRCLR(0xff);
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// Wait until counter register value reaches 10.(10 = 1ms : TCNTR is 100us tick counter register)
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while (getTCNTR() < 0x0a) {}
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}
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}
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#endif
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/// @cond DOXY_APPLY_CODE
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#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
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/// @endcond
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void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
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setPHYRAR(phyregaddr);
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setPHYDIR(var);
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setPHYACR(PHYACR_WRITE);
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while (getPHYACR()); //wait for command complete
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}
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uint16_t wiz_mdio_read(uint8_t phyregaddr) {
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setPHYRAR(phyregaddr);
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setPHYACR(PHYACR_READ);
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while (getPHYACR()); //wait for command complete
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return getPHYDOR();
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}
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/// @cond DOXY_APPLY_CODE
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#endif
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/// @endcond
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////////////////////////////////////////////////////////////////////////////////////////
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#endif
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