Strip W6300 drivers to W6300-only, remove doxygen, flatten into w6300/
This commit is contained in:
Ian Gulliver
+7
-9
@@ -11,18 +11,16 @@ pico_sdk_init()
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add_executable(picomap
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picomap.cpp
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lib/w6300/wizchip_spi.c
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lib/w6300/wizchip_qspi_pio.c
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lib/w6300/ioLibrary/wizchip_conf.c
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lib/w6300/ioLibrary/W6300/w6300.c
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lib/w6300/ioLibrary/socket.c
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w6300/wizchip_spi.c
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w6300/wizchip_qspi_pio.c
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w6300/wizchip_conf.c
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w6300/w6300.c
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w6300/socket.c
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)
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target_include_directories(picomap PRIVATE
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include
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lib/w6300
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lib/w6300/ioLibrary
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lib/w6300/ioLibrary/W6300
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w6300
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)
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target_compile_definitions(picomap PRIVATE
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@@ -31,7 +29,7 @@ target_compile_definitions(picomap PRIVATE
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_WIZCHIP_QSPI_MODE_=QSPI_QUAD_MODE
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)
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pico_generate_pio_header(picomap ${CMAKE_CURRENT_LIST_DIR}/lib/w6300/wizchip_qspi_pio.pio)
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pico_generate_pio_header(picomap ${CMAKE_CURRENT_LIST_DIR}/w6300/wizchip_qspi_pio.pio)
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pico_enable_stdio_usb(picomap 1)
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pico_enable_stdio_uart(picomap 0)
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@@ -1,11 +0,0 @@
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/* Board list */
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#define WIZnet_Ethernet_HAT 0
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#define W5100S_EVB_PICO 1
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#define W5500_EVB_PICO 2
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#define W55RP20_EVB_PICO 3
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#define W5100S_EVB_PICO2 4
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#define W5500_EVB_PICO2 5
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#define W6100_EVB_PICO 6
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#define W6100_EVB_PICO2 7
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#define W6300_EVB_PICO 8
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#define W6300_EVB_PICO2 9
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,736 +0,0 @@
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//*****************************************************************************
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//
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//! \file socket.h
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//! \brief SOCKET APIs Header file.
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//! \details SOCKET APIs like as berkeley socket api.
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//! \version 1.0.2
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//! \date 2013/10/21
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//! \par Revision history
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//! <2015/02/05> Notice
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//! The version history is not updated after this point.
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//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
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//! >> https://github.com/Wiznet/ioLibrary_Driver
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//! <2014/05/01> V1.0.2. Refer to M20140501
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//! 1. Modify the comment : SO_REMAINED -> PACK_REMAINED
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//! 2. Add the comment as zero byte udp data reception in getsockopt().
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//! <2013/10/21> 1st Release
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//! \author MidnightCow
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//! \copyright
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//!
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//! Copyright (c) 2013, WIZnet Co., LTD.
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//! All rights reserved.
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//!
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//! Redistribution and use in source and binary forms, with or without
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//! modification, are permitted provided that the following conditions
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//! are met:
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//!
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//! * Redistributions of source code must retain the above copyright
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//! notice, this list of conditions and the following disclaimer.
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//! * Redistributions in binary form must reproduce the above copyright
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//! notice, this list of conditions and the following disclaimer in the
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//! documentation and/or other materials provided with the distribution.
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//! * Neither the name of the <ORGANIZATION> nor the names of its
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//! contributors may be used to endorse or promote products derived
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//! from this software without specific prior written permission.
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//!
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//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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//! THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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/**
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@defgroup WIZnet_socket_APIs 1. WIZnet socket APIs
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@brief WIZnet socket APIs are based on Berkeley socket APIs, thus it has much similar name and interface.
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But there is a little bit of difference.
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@details
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<b> Comparison between WIZnet and Berkeley SOCKET APIs </b>
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<table>
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<tr> <td><b>API</b></td> <td><b>WIZnet</b></td> <td><b>Berkeley</b></td> </tr>
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<tr> <td>socket()</td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>bind()</b></td> <td>X</td> <td>O</td> </tr>
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<tr> <td><b>listen()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>connect()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>accept()</b></td> <td>X</td> <td>O</td> </tr>
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<tr> <td><b>recv()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>send()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>recvfrom()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>sendto()</b></td> <td>O</td> <td>O</td> </tr>
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<tr> <td><b>closesocket()</b></td> <td>O<br>close() & disconnect()</td> <td>O</td> </tr>
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</table>
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There are @b bind() and @b accept() functions in @b Berkeley SOCKET API but,
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not in @b WIZnet SOCKET API. Because socket() of WIZnet is not only creating a SOCKET but also binding a local port number,
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and listen() of WIZnet is not only listening to connection request from client but also accepting the connection request. \n
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When you program "TCP SERVER" with Berkeley SOCKET API, you can use only one listen port.
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When the listen SOCKET accepts a connection request from a client, it keeps listening.
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After accepting the connection request, a new SOCKET is created and the new SOCKET is used in communication with the client. \n
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Following figure shows network flow diagram by Berkeley SOCKET API.
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@image html Berkeley_SOCKET.jpg "<Berkeley SOCKET API>"
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But, When you program "TCP SERVER" with WIZnet SOCKET API, you can use as many as 8 listen SOCKET with same port number. \n
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Because there's no accept() in WIZnet SOCKET APIs, when the listen SOCKET accepts a connection request from a client,
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it is changed in order to communicate with the client.
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And the changed SOCKET is not listening any more and is dedicated for communicating with the client. \n
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If there're many listen SOCKET with same listen port number and a client requests a connection,
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the SOCKET which has the smallest SOCKET number accepts the request and is changed as communication SOCKET. \n
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Following figure shows network flow diagram by WIZnet SOCKET API.
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@image html WIZnet_SOCKET.jpg "<WIZnet SOCKET API>"
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*/
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#ifndef _SOCKET_H_
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#define _SOCKET_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "wizchip_conf.h"
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#define SOCKET uint8_t ///< SOCKET type define for legacy driver
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#define SOCK_OK 1 ///< Result is OK about socket process.
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#define SOCK_BUSY 0 ///< Socket is busy on processing the operation. Valid only Non-block IO Mode.
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#define SOCK_FATAL -1000 ///< Result is fatal error about socket process.
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#define SOCK_ERROR 0
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#define SOCKERR_SOCKNUM (SOCK_ERROR - 1) ///< Invalid socket number
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#define SOCKERR_SOCKOPT (SOCK_ERROR - 2) ///< Invalid socket option
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#define SOCKERR_SOCKINIT (SOCK_ERROR - 3) ///< Socket is not initialized or SIPR is Zero IP address when Sn_MR_TCP
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#define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4) ///< Socket unexpectedly closed.
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#define SOCKERR_SOCKMODE (SOCK_ERROR - 5) ///< Invalid socket mode for socket operation.
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#define SOCKERR_SOCKFLAG (SOCK_ERROR - 6) ///< Invalid socket flag
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#define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7) ///< Invalid socket status for socket operation.
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#define SOCKERR_ARG (SOCK_ERROR - 10) ///< Invalid argument.
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#define SOCKERR_PORTZERO (SOCK_ERROR - 11) ///< Port number is zero
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#define SOCKERR_IPINVALID (SOCK_ERROR - 12) ///< Invalid IP address
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#define SOCKERR_TIMEOUT (SOCK_ERROR - 13) ///< Timeout occurred
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#define SOCKERR_DATALEN (SOCK_ERROR - 14) ///< Data length is zero or greater than buffer max size.
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#define SOCKERR_BUFFER (SOCK_ERROR - 15) ///< Socket buffer is not enough for data communication.
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#define SOCKFATAL_PACKLEN (SOCK_FATAL - 1) ///< Invalid packet length. Fatal Error.
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#if (_WIZCHIP_ == W5100 || _WIZCHIP_ == W5100S || _WIZCHIP_ == W5200 || _WIZCHIP_ == W5300 || _WIZCHIP_ == W5500)
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/*
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SOCKET FLAG
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*/
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#define SF_ETHER_OWN (Sn_MR_MFEN) ///< In @ref Sn_MR_MACRAW, Receive only the packet as broadcast, multicast and own packet
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#define SF_IGMP_VER2 (Sn_MR_MC) ///< In @ref Sn_MR_UDP with \ref SF_MULTI_ENABLE, Select IGMP version 2.
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#define SF_TCP_NODELAY (Sn_MR_ND) ///< In @ref Sn_MR_TCP, Use to nodelayed ack.
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#define SF_MULTI_ENABLE (Sn_MR_MULTI) ///< In @ref Sn_MR_UDP, Enable multicast mode.
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#define Sn_MR2_DHAM (1<<1)
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#define SF_DHA_MANUAL (Sn_MR2_DHAM)
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#define Sn_MR2_FARP (1<<0)
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#define SF_FORCE_ARP (Sn_MR2_FARP)
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#if _WIZCHIP_ == 5500
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#define SF_BROAD_BLOCK (Sn_MR_BCASTB) ///< In @ref Sn_MR_UDP or @ref Sn_MR_MACRAW, Block broadcast packet. Valid only in W5500
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#define SF_MULTI_BLOCK (Sn_MR_MMB) ///< In @ref Sn_MR_MACRAW, Block multicast packet. Valid only in W5500
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#define SF_IPv6_BLOCK (Sn_MR_MIP6B) ///< In @ref Sn_MR_MACRAW, Block IPv6 packet. Valid only in W5500
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#define SF_UNI_BLOCK (Sn_MR_UCASTB) ///< In @ref Sn_MR_UDP with \ref SF_MULTI_ENABLE. Valid only in W5500
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#endif
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//A201505 : For W5300
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#if _WIZCHIP_ == 5300
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#define SF_TCP_ALIGN 0x02 ///< Valid only \ref Sn_MR_TCP and W5300, refer to \ref Sn_MR_ALIGN
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#endif
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#define SF_IO_NONBLOCK 0x01 ///< Socket nonblock io mode. It used parameter in \ref socket().
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/*
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UDP & MACRAW Packet Infomation
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*/
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#define PACK_FIRST 0x80 ///< In Non-TCP packet, It indicates to start receiving a packet. (When W5300, This flag can be applied)
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#define PACK_REMAINED 0x01 ///< In Non-TCP packet, It indicates to remain a packet to be received. (When W5300, This flag can be applied)
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#define PACK_COMPLETED 0x00 ///< In Non-TCP packet, It indicates to complete to receive a packet. (When W5300, This flag can be applied)
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//A20150601 : For Integrating with W5300
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#define PACK_FIFOBYTE 0x02 ///< Valid only W5300, It indicate to have read already the Sn_RX_FIFOR.
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//
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//teddy 240122
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#define PACK_IPv6 (1<<7) ///< It indicates the destination IP address of the received packet is IPv6 or IPv4.
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#define PACK_IPV6_ALLNODE (PACK_IPv6 | (1<<6)) ///< It indicates the destination IP address of the received packet is allnode multicast(broadcast) address or not.
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#define PACK_IPV6_MULTI (PACK_IPv6 | (1<<5)) ///< It indicates the destination IP address of the received packet is multicast address or not.
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#define PACK_IPV6_LLA (PACK_IPv6 | (1<<4)) ///< It indicates the destination IP address of the received packet is lla or gua.
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#define PACK_NONE (0x00) ///< It indicates no information of a packet
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#elif ((_WIZCHIP_ == 6100) || (_WIZCHIP_ == 6300))
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/*
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- @ref Sn_MR_MULTI : Support UDP Multicasting
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- @ref Sn_MR_MF : Support MAC Filter Enable
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- @ref Sn_MR_BRDB : Broadcast Block
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- @ref Sn_MR_FPSH : Force PSH flag
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- @ref Sn_MR_ND : No Delay ACK flag
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- @ref Sn_MR_MC : IGMP ver2, ver1
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- @ref Sn_MR_SMB : Solicited Multicast Block
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- @ref Sn_MR_MMB : IPv4 Multicast block
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- @ref Sn_MR_UNIB : Unicast Block
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- @ref Sn_MR_MMB6 : IPv6 UDP Multicast Block </b>
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- @ref Sn_MR2_DHAM : @ref Sn_MR2_DHAM_AUTO, @ref Sn_MR2_DHAM_MANUAL
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- @ref Sn_MR_FARP
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*/
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/*
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SOCKET FLAG
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*/
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/**
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@brief In UDP mode such as @ref Sn_MR_UDP4 and @ref Sn_MR_UDP6, @ref Sn_MR_UDP6, Enable multicast mode. When @ref Sn_MR_UDP6, Enable only IPv6 Multicating.
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*/
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#define SF_MULTI_ENABLE (Sn_MR_MULTI)
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#define SF_ETHER_OWN (Sn_MR_MF) ///< In MACRAW mode such as @ref Sn_MR_MACRAW, Receive only the packet as broadcast, multicast and own packet
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/**
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@brief In UDP mode such as @ref Sn_MR_UDP4, @ref Sn_MR_UDP6 and @ref Sn_MR_UDPD, or In MACRAW mode sucha as @ref Sn_MR_MACRAW, Block a broadcast packet.
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*/
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#define SF_BROAD_BLOCK (Sn_MR_BRDB)
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#define SF_TCP_FPSH (Sn_MR_FPSH) ///< In TCP mode such as @ref Sn_MR_TCP4, @ref Sn_MR_TCP6 and @ref Sn_MR_TCPD, Use to forced push flag.
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#define SF_TCP_NODELAY (Sn_MR_ND) ///< In TCP mode such as @ref Sn_MR_TCP4, @ref Sn_MR_TCP6 and @ref Sn_MR_TCPD, Use to nodelayed ack.
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#define SF_IGMP_VER2 (Sn_MR_MC) ///< In UDP mode such as @ref Sn_MR_UDP4 with @ref SF_MULTI_ENABLE, Select IGMP version 2.
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#define SF_SOLICIT_BLOCK (Sn_MR_SMB) ///< In UDP mode such as @ref Sn_MR_UDP6 and @ref Sn_MR_UDPD, Block a solicited mutlicast packet.
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#define SF_ETHER_MULTI4B (Sn_MR_MMB4) ///< In MACRAW mode such as @ref Sn_MR_MACRAW with @ref SF_MULTI_ENABLE, Block a IPv4 multicast packet.
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#define SF_UNI_BLOCK (Sn_MR_UNIB) ///< In UDP mdoe such as @ref Sn_MR_UDP4, @ref Sn_MR_UDP6 and @ref Sn_MR_UDPD with @ref SF_MULTI_ENABLE, Block a unicast packet.
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#define SF_ETHER_MULIT6B (Sn_MR_MMB6) ///< In MACRAW mode such as @ref Sn_MR_MACRAW with @ref SF_MULTI_ENABLE, Block a IPv6 multicast packet.
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/**
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@brief Force to APR.
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@details In datagram mode such as @ref Sn_MR_IPRAW4, @ref Sn_MR_IPRAW6, @ref Sn_MR_UDP4, @ref Sn_MR_UDP6, and @ref Sn_MR_UDPD,
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Force to request ARP before a packet is sent to a destination.\n
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In TCP mode such as @ref Sn_MR_TCP4, @ref Sn_MR_TCP6, and @ref Sn_MR_TCPD and <b>TCP SERVER</b> operation mode,
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Force to request ARP before SYN/ACK packet is sent to a <b>TCP CLIENT</b>. \n
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When @ref SF_DHA_MANUAL is set, the ARP is process but the destination hardware address is fixed by user.
|
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*/
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#define SF_FORCE_ARP (Sn_MR2_FARP)
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/**
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@brief The destination hardware address of packet to be transmitted is set by user through @ref _Sn_DHAR_. It is invalid in MACRAW mode such as @ref Sn_MR_MACRAW.
|
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*/
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#define SF_DHA_MANUAL (Sn_MR2_DHAM)
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#define SF_IO_NONBLOCK (0x01 << 3) ///< Socket nonblock io mode. It used parameter in @ref socket().
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|
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/*
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UDP, IPRAW, MACRAW Packet Infomation
|
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*/
|
||||
#define PACK_IPv6 (1<<7) ///< It indicates the destination IP address of the received packet is IPv6 or IPv4.
|
||||
#define PACK_IPV6_ALLNODE (PACK_IPv6 | (1<<6)) ///< It indicates the destination IP address of the received packet is allnode multicast(broadcast) address or not.
|
||||
#define PACK_IPV6_MULTI (PACK_IPv6 | (1<<5)) ///< It indicates the destination IP address of the received packet is multicast address or not.
|
||||
#define PACK_IPV6_LLA (PACK_IPv6 | (1<<4)) ///< It indicates the destination IP address of the received packet is lla or gua.
|
||||
#define PACK_COMPLETED (1<<3) ///< It indicates the read data is last in the received packet.
|
||||
#define PACK_REMAINED (1<<2) ///< It indicates to remain data in the received packet
|
||||
#define PACK_FIRST (1<<1) ///< It indicates the read data is first in the received packet.
|
||||
#define PACK_NONE (0x00) ///< It indicates no information of a packet
|
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|
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#define SRCV6_PREFER_AUTO (PSR_AUTO) ///< Soruce IPv6 address is preferred to auto-selection. Refer to @ref _Sn_PSR_
|
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#define SRCV6_PREFER_LLA (PSR_LLA) ///< Soruce IPv6 address is preferred to link local address. Refer to @ref _Sn_PSR_
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#define SRCV6_PREFER_GUA (PSR_GUA) ///< Soruce IPv6 address is preferred to global unique address. Refer to @ref _Sn_PSR_
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||||
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||||
#define TCPSOCK_MODE (Sn_ESR_TCPM) ///< It indicates the IP version when SOCKETn is opened as TCP6 or TCPD mode.(0 - IPv4 , 1 - IPv6)
|
||||
#define TCPSOCK_OP (Sn_ESR_TCPOP) ///< It indicates the operation mode when SOCKETn is connected.(0 - <b>TCP CLIENT</b> , 1 - <b>TCP SERVER</b>)
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||||
#define TCPSOCK_SIP (Sn_ESR_IP6T) ///< It indicates the source ip address type when SOCKET is connected. (0 - Link Local, 1 - Global Unique)
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||||
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||||
/////////////////////////////
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||||
// SOCKET CONTROL & OPTION //
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||||
/////////////////////////////
|
||||
#define SOCK_IO_BLOCK 0 ///< Socket Block IO Mode in @ref setsockopt().
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||||
#define SOCK_IO_NONBLOCK 1 ///< Socket Non-block IO Mode in @ref setsockopt().
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||||
#endif
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||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
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||||
@brief Open a socket.
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||||
@details Initializes the socket with 'sn' passed as parameter and open.
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||||
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
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||||
@param protocol Protocol type to operate such as TCP, UDP and MACRAW.
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||||
@param port Port number to be bined.
|
||||
@param flag Socket flags as \ref SF_ETHER_OWN, \ref SF_IGMP_VER2, \ref SF_TCP_NODELAY, \ref SF_MULTI_ENABLE, \ref SF_IO_NONBLOCK and so on.\n
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||||
Valid flags only in W5500 : @ref SF_BROAD_BLOCK, @ref SF_MULTI_BLOCK, @ref SF_IPv6_BLOCK, and @ref SF_UNI_BLOCK.
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||||
@sa Sn_MR
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||||
|
||||
@return @b Success : The socket number @b 'sn' passed as parameter\n
|
||||
@b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number\n
|
||||
@ref SOCKERR_SOCKMODE - Not support socket mode as TCP, UDP, and so on. \n
|
||||
@ref SOCKERR_SOCKFLAG - Invaild socket flag.
|
||||
*/
|
||||
int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Close a socket.
|
||||
@details It closes the socket with @b'sn' passed as parameter.
|
||||
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
|
||||
|
||||
@return @b Success : @ref SOCK_OK \n
|
||||
@b Fail : @ref SOCKERR_SOCKNUM - Invalid socket number
|
||||
*/
|
||||
int8_t close(uint8_t sn);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Listen to a connection request from a client.
|
||||
@details It is listening to a connection request from a client.
|
||||
If connection request is accepted successfully, the connection is established. Socket sn is used in passive(server) mode.
|
||||
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
|
||||
@return @b Success : @ref SOCK_OK \n
|
||||
@b Fail :\n @ref SOCKERR_SOCKINIT - Socket is not initialized \n
|
||||
@ref SOCKERR_SOCKCLOSED - Socket closed unexpectedly.
|
||||
*/
|
||||
int8_t listen(uint8_t sn);
|
||||
|
||||
//teddy 240122
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Try to connect to a <b>TCP SERVER</b>.
|
||||
@details It sends a connection-reqeust message to the server with destination IP address and port number passed as parameter.\n
|
||||
SOCKET <i>sn</i> is used as active(<b>TCP CLIENT</b>) mode.
|
||||
@param sn SOCKET number. It should be <b>0 ~ @ref _WIZCHIP_SOCK_NUM_</b>.
|
||||
@param addr Pointer variable of destination IPv6 or IPv4 address.
|
||||
@param port Destination port number.
|
||||
@param addrlen the length of <i>addr</i>. \n <- removed
|
||||
If addr is IPv6 address it should be 16,else if addr is IPv4 address it should be 4. Otherwize, return @ref SOCKERR_IPINVALID.
|
||||
@return Success : @ref SOCK_OK \n
|
||||
Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number\n
|
||||
@ref SOCKERR_SOCKMODE - Invalid socket mode\n
|
||||
@ref SOCKERR_SOCKINIT - Socket is not initialized\n
|
||||
@ref SOCKERR_IPINVALID - Wrong server IP address\n
|
||||
@ref SOCKERR_PORTZERO - Server port zero\n
|
||||
@ref SOCKERR_TIMEOUT - Timeout occurred during request connection\n
|
||||
@ref SOCK_BUSY - In non-block io mode, it returns immediately\n
|
||||
@note It is valid only in TCP client mode. \n
|
||||
In block io mode, it does not return until connection is completed. \n
|
||||
In Non-block io mode(@ref SF_IO_NONBLOCK), it returns @ref SOCK_BUSY immediately.
|
||||
*/
|
||||
static int8_t connect_IO_6(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
//int8_t connect(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Try to disconnect a connection socket.
|
||||
@details It sends request message to disconnect the TCP socket 'sn' passed as parameter to the server or client.
|
||||
@note It is valid only in TCP server or client mode. \n
|
||||
In block io mode, it does not return until disconnection is completed. \n
|
||||
In Non-block io mode, it return @ref SOCK_BUSY immediately. \n
|
||||
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
|
||||
@return @b Success : @ref SOCK_OK \n
|
||||
@b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number \n
|
||||
@ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
|
||||
@ref SOCKERR_TIMEOUT - Timeout occurred \n
|
||||
@ref SOCK_BUSY - Socket is busy.
|
||||
*/
|
||||
int8_t disconnect(uint8_t sn);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Send data to the connected peer in TCP socket.
|
||||
@details It is used to send outgoing data to the connected socket.
|
||||
@note It is valid only in TCP server or client mode. It can't send data greater than socket buffer size. \n
|
||||
In block io mode, It doesn't return until data send is completed - socket buffer size is greater than data. \n
|
||||
In non-block io mode, It return @ref SOCK_BUSY immediately when socket buffer is not enough. \n
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
|
||||
@param buf Pointer buffer containing data to be sent.
|
||||
@param len The byte length of data in buf.
|
||||
@return @b Success : The sent data size \n
|
||||
@b Fail : \n @ref SOCKERR_SOCKSTATUS - Invalid socket status for socket operation \n
|
||||
@ref SOCKERR_TIMEOUT - Timeout occurred \n
|
||||
@ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
|
||||
@ref SOCKERR_SOCKNUM - Invalid socket number \n
|
||||
@ref SOCKERR_DATALEN - zero data length \n
|
||||
@ref SOCK_BUSY - Socket is busy.
|
||||
*/
|
||||
int32_t send(uint8_t sn, uint8_t * buf, uint16_t len);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Receive data from the connected peer.
|
||||
@details It is used to read incoming data from the connected socket.\n
|
||||
It waits for data as much as the application wants to receive.
|
||||
@note It is valid only in TCP server or client mode. It can't receive data greater than socket buffer size. \n
|
||||
In block io mode, it doesn't return until data reception is completed - data is filled as <I>len</I> in socket buffer. \n
|
||||
In non-block io mode, it return @ref SOCK_BUSY immediately when <I>len</I> is greater than data size in socket buffer. \n
|
||||
|
||||
@param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
|
||||
@param buf Pointer buffer to read incoming data.
|
||||
@param len The max data length of data in buf.
|
||||
@return @b Success : The real received data size \n
|
||||
@b Fail :\n
|
||||
@ref SOCKERR_SOCKSTATUS - Invalid socket status for socket operation \n
|
||||
@ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
|
||||
@ref SOCKERR_SOCKNUM - Invalid socket number \n
|
||||
@ref SOCKERR_DATALEN - zero data length \n
|
||||
@ref SOCK_BUSY - Socket is busy.
|
||||
*/
|
||||
int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Send datagram to the peer specifed by destination IP address and port number passed as parameter.
|
||||
@details It sends datagram data by using UDP,IPRAW, or MACRAW mode SOCKET.
|
||||
@param sn SOCKET number. It should be <b>0 ~ @ref _WIZCHIP_SOCK_NUM_</b>.
|
||||
@param buf Pointer of data buffer to be sent.
|
||||
@param len The byte length of data in buf.
|
||||
@param addr Pointer variable of destination IPv6 or IPv4 address.
|
||||
@param port Destination port number.
|
||||
@param addrlen the length of <i>addr</i>. \n
|
||||
If addr is IPv6 address it should be 16,else if addr is IPv4 address it should be 4. Otherwize, return @ref SOCKERR_IPINVALID.
|
||||
@return Success : The real sent data size. It may be equal to <i>len</i> or small.\n
|
||||
Fail :\n @ref SOCKERR_SOCKNUM - Invalid SOCKET number \n
|
||||
@ref SOCKERR_SOCKMODE - Invalid operation in the SOCKET \n
|
||||
@ref SOCKERR_SOCKSTATUS - Invalid SOCKET status for SOCKET operation \n
|
||||
@ref SOCKERR_IPINVALID - Invalid IP address\n
|
||||
@ref SOCKERR_PORTZERO - Destination port number is zero\n
|
||||
@ref SOCKERR_DATALEN - Invalid data length \n
|
||||
@ref SOCKERR_SOCKCLOSED - SOCKET unexpectedly closed \n
|
||||
@ref SOCKERR_TIMEOUT - Timeout occurred \n
|
||||
@ref SOCK_BUSY - SOCKET is busy.
|
||||
@note It is valid only in @ref Sn_MR_UDP4, @ref Sn_MR_UDP6, @ref Sn_MR_UDPD, @ref Sn_MR_IPRAW4, @ref Sn_MR_IPRAW6, and @ref Sn_MR_MACRAW. \n
|
||||
In UDP mode, It can send data as many as SOCKET RX buffer size if data is greater than SOCKET TX buffer size. \n
|
||||
In IPRAW and MACRAW mode, It should send data as many as MTU(maxium transmission unit) if data is greater than MTU. That is, <i>len</i> can't exceed to MTU.
|
||||
In block io mode, It doesn't return until data send is completed.
|
||||
In non-block io mode(@ref SF_IO_NONBLOCK), It return @ref SOCK_BUSY immediately when SOCKET transimttable buffer size is not enough.
|
||||
*/
|
||||
//int32_t sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
static int32_t sendto_IO_6(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Receive datagram from a peer
|
||||
@details It can read a data received from a peer by using UDP, IPRAW, or MACRAW mode SOCKET.
|
||||
@param sn SOCKET number. It should be <b>0 ~ @ref _WIZCHIP_SOCK_NUM_</b>.
|
||||
@param buf Pointer buffer to be saved the received data.
|
||||
@param len The max read data length. \n
|
||||
When the received packet size <= <i>len</i>, it can read data as many as the packet size. \n
|
||||
When others, it can read data as many as len and remain to the rest data of the packet.
|
||||
@param addr Pointer variable of destination IP address.\n
|
||||
It is valid only when @ref recvfrom() is first called for receiving the datagram packet.
|
||||
You can check it valid or not through @ref PACK_FIRST. You can get it through @ref getsockopt(sn, @ref SO_PACKINFO, &packinfo).\n
|
||||
In UDP4, IPRAW mode SOCKET, it should be allocated over 4bytes. \n
|
||||
In UDP6, UDPD mode SOCKET, it should be allocated over 16bytes.
|
||||
@param port Pointer variable of destination port number. \n
|
||||
It is valid only when @ref recvfrom() is first called for receiving the datagram packet, same as <i>port</i> case.
|
||||
@param addrlen The byte length of destination IP address. \n
|
||||
It is valid only when @ref recvfrom() is first called for receiving the datagram packet, same as <i>port</i> case.\n
|
||||
When the destination has a IPv4 address, it is set to 4. \n
|
||||
when the destination has a IPv6 address, it is set to 16.
|
||||
@return Success : The real received data size. It may be equal to <i>len</i> or small.\n
|
||||
Fail : @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
|
||||
@ref SOCKERR_SOCKNUM - Invalid socket number \n
|
||||
@ref SOCKERR_ARG - Invalid parameter such as <i>addr</i>, <i>port</i>
|
||||
@ref SOCK_BUSY - SOCKET is busy.
|
||||
@note It is valid only in @ref Sn_MR_UDP4, @ref Sn_MR_UDP6, @ref Sn_MR_UDPD, @ref Sn_MR_IPRAW4, @ref Sn_MR_IPRAW6, and @ref Sn_MR_MACRAW. \n
|
||||
When SOCKET is opened with @ref Sn_MR_MACRAW or When it reads the the remained data of the previous datagram packet,
|
||||
the parameters such as <i>addr</i>, <i>port</i>, <i>addrlen</i> is ignored. \n
|
||||
Also, It can read data as many as the received datagram packet size if <i>len</i> is greater than the datagram packet size. \n
|
||||
In block io mode, it doesn't return until data reception is completed. that is, it waits until any datagram packet is received in SOCKET RX buffer. \n
|
||||
In non-block io mode(@ref SF_IO_NONBLOCK), it return @ref SOCK_BUSY immediately when SOCKET RX buffer is empty. \n
|
||||
*/
|
||||
//int32_t recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen);
|
||||
static int32_t recvfrom_IO_6(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen);
|
||||
|
||||
|
||||
/////////////////////////////
|
||||
// SOCKET CONTROL & OPTION //
|
||||
/////////////////////////////
|
||||
#define SOCK_IO_BLOCK 0 ///< Socket Block IO Mode in @ref setsockopt().
|
||||
#define SOCK_IO_NONBLOCK 1 ///< Socket Non-block IO Mode in @ref setsockopt().
|
||||
|
||||
/**
|
||||
@defgroup DATA_TYPE DATA TYPE
|
||||
*/
|
||||
|
||||
/**
|
||||
@ingroup DATA_TYPE
|
||||
@brief The kind of Socket Interrupt.
|
||||
@sa Sn_IR, Sn_IMR, setSn_IR(), getSn_IR(), setSn_IMR(), getSn_IMR()
|
||||
*/
|
||||
typedef enum {
|
||||
SIK_CONNECTED = (1 << 0), ///< connected
|
||||
SIK_DISCONNECTED = (1 << 1), ///< disconnected
|
||||
SIK_RECEIVED = (1 << 2), ///< data received
|
||||
SIK_TIMEOUT = (1 << 3), ///< timeout occurred
|
||||
SIK_SENT = (1 << 4), ///< send ok
|
||||
//M20150410 : Remove the comma of last member
|
||||
//SIK_ALL = 0x1F, ///< all interrupt
|
||||
SIK_ALL = 0x1F ///< all interrupt
|
||||
} sockint_kind;
|
||||
|
||||
/**
|
||||
@ingroup DATA_TYPE
|
||||
@brief The type of @ref ctlsocket().
|
||||
*/
|
||||
typedef enum {
|
||||
CS_SET_IOMODE, ///< set socket IO mode with @ref SOCK_IO_BLOCK or @ref SOCK_IO_NONBLOCK
|
||||
CS_GET_IOMODE, ///< get socket IO mode
|
||||
CS_GET_MAXTXBUF, ///< get the size of socket buffer allocated in TX memory
|
||||
CS_GET_MAXRXBUF, ///< get the size of socket buffer allocated in RX memory
|
||||
CS_CLR_INTERRUPT, ///< clear the interrupt of socket with @ref sockint_kind
|
||||
CS_GET_INTERRUPT, ///< get the socket interrupt. refer to @ref sockint_kind
|
||||
|
||||
//teddy 240122
|
||||
//#if _WIZCHIP_ == W6100 || _WIZCHIP_ == W6300
|
||||
CS_SET_PREFER, ///< set the preferred source IPv6 address of transmission packet.\n Refer to @ref SRCV6_PREFER_AUTO, @ref SRCV6_PREFER_LLA and @ref SRCV6_PREFER_GUA.
|
||||
CS_GET_PREFER, ///< get the preferred source IPv6 address of transmission packet.\n Refer to @ref SRCV6_PREFER_AUTO, @ref SRCV6_PREFER_LLA and @ref SRCV6_PREFER_GUA.
|
||||
//#endif
|
||||
#if _WIZCHIP_ >= 5100
|
||||
CS_SET_INTMASK, ///< set the interrupt mask of socket with @ref sockint_kind, Not supported in W5100
|
||||
CS_GET_INTMASK ///< get the masked interrupt of socket. refer to @ref sockint_kind, Not supported in W5100
|
||||
#endif
|
||||
} ctlsock_type;
|
||||
|
||||
|
||||
/**
|
||||
@ingroup DATA_TYPE
|
||||
@brief The type of socket option in @ref setsockopt() or @ref getsockopt()
|
||||
*/
|
||||
typedef enum {
|
||||
SO_FLAG, ///< Valid only in getsockopt(), For set flag of socket refer to <I>flag</I> in @ref socket().
|
||||
SO_TTL, ///< Set TTL. @ref Sn_TTL ( @ref setSn_TTL(), @ref getSn_TTL() )
|
||||
SO_TOS, ///< Set TOS. @ref Sn_TOS ( @ref setSn_TOS(), @ref getSn_TOS() )
|
||||
SO_MSS, ///< Set MSS. @ref Sn_MSSR ( @ref setSn_MSSR(), @ref getSn_MSSR() )
|
||||
SO_DESTIP, ///< Set the destination IP address. @ref Sn_DIPR ( @ref setSn_DIPR(), @ref getSn_DIPR() )
|
||||
SO_DESTPORT, ///< Set the destination Port number. @ref Sn_DPORT ( @ref setSn_DPORT(), @ref getSn_DPORT() )
|
||||
#if _WIZCHIP_ != 5100
|
||||
SO_KEEPALIVESEND, ///< Valid only in setsockopt. Manually send keep-alive packet in TCP mode, Not supported in W5100
|
||||
#if !( (_WIZCHIP_ == 5100) || (_WIZCHIP_ == 5200) )
|
||||
SO_KEEPALIVEAUTO, ///< Set/Get keep-alive auto transmission timer in TCP mode, Not supported in W5100, W5200
|
||||
#endif
|
||||
#endif
|
||||
SO_SENDBUF, ///< Valid only in getsockopt. Get the free data size of Socekt TX buffer. @ref Sn_TX_FSR, @ref getSn_TX_FSR()
|
||||
SO_RECVBUF, ///< Valid only in getsockopt. Get the received data size in socket RX buffer. @ref Sn_RX_RSR, @ref getSn_RX_RSR()
|
||||
SO_STATUS, ///< Valid only in getsockopt. Get the socket status. @ref Sn_SR, @ref getSn_SR()
|
||||
|
||||
//teddy 240122
|
||||
//#if _WIZCHIP_ == W6100 || _WIZCHIP_ == W6300
|
||||
SO_EXTSTATUS, ///< Valid only in @ref getsockopt(). Get the extended TCP SOCKETn status. @ref getSn_ESR()
|
||||
SO_MODE,
|
||||
//#endif
|
||||
SO_REMAINSIZE, ///< Valid only in getsockopt. Get the remained packet size in other then TCP mode.
|
||||
SO_PACKINFO ///< Valid only in getsockopt. Get the packet information as @ref PACK_FIRST, @ref PACK_REMAINED, and @ref PACK_COMPLETED in other then TCP mode.
|
||||
} sockopt_type;
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Control socket.
|
||||
@details Control IO mode, Interrupt & Mask of socket and get the socket buffer information.
|
||||
Refer to @ref ctlsock_type.
|
||||
@param sn socket number
|
||||
@param cstype type of control socket. refer to @ref ctlsock_type.
|
||||
@param arg Data type and value is determined according to @ref ctlsock_type. \n
|
||||
<table>
|
||||
<tr> <td> @b cstype </td> <td> @b data type</td><td>@b value</td></tr>
|
||||
<tr> <td> @ref CS_SET_IOMODE \n @ref CS_GET_IOMODE </td> <td> uint8_t </td><td>@ref SOCK_IO_BLOCK @ref SOCK_IO_NONBLOCK</td></tr>
|
||||
<tr> <td> @ref CS_GET_MAXTXBUF \n @ref CS_GET_MAXRXBUF </td> <td> uint16_t </td><td> 0 ~ 16K </td></tr>
|
||||
<tr> <td> @ref CS_CLR_INTERRUPT \n @ref CS_GET_INTERRUPT \n @ref CS_SET_INTMASK \n @ref CS_GET_INTMASK </td> <td> @ref sockint_kind </td><td> @ref SIK_CONNECTED, etc. </td></tr>
|
||||
</table>
|
||||
@return @b Success @ref SOCK_OK \n
|
||||
@b fail @ref SOCKERR_ARG - Invalid argument\n
|
||||
*/
|
||||
int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief set socket options
|
||||
@details Set socket option like as TTL, MSS, TOS, and so on. Refer to @ref sockopt_type.
|
||||
|
||||
@param sn socket number
|
||||
@param sotype socket option type. refer to @ref sockopt_type
|
||||
@param arg Data type and value is determined according to <I>sotype</I>. \n
|
||||
<table>
|
||||
<tr> <td> @b sotype </td> <td> @b data type</td><td>@b value</td></tr>
|
||||
<tr> <td> @ref SO_TTL </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
|
||||
<tr> <td> @ref SO_TOS </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
|
||||
<tr> <td> @ref SO_MSS </td> <td> uint16_t </td><td> 0 ~ 65535 </td> </tr>
|
||||
<tr> <td> @ref SO_DESTIP </td> <td> uint8_t[4] </td><td> </td></tr>
|
||||
<tr> <td> @ref SO_DESTPORT </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
|
||||
<tr> <td> @ref SO_KEEPALIVESEND </td> <td> null </td><td> null </td></tr>
|
||||
<tr> <td> @ref SO_KEEPALIVEAUTO </td> <td> uint8_t </td><td> 0 ~ 255 </td></tr>
|
||||
</table>
|
||||
@return
|
||||
- @b Success : @ref SOCK_OK \n
|
||||
- @b Fail
|
||||
- @ref SOCKERR_SOCKNUM - Invalid Socket number \n
|
||||
- @ref SOCKERR_SOCKMODE - Invalid socket mode \n
|
||||
- @ref SOCKERR_SOCKOPT - Invalid socket option or its value \n
|
||||
- @ref SOCKERR_TIMEOUT - Timeout occurred when sending keep-alive packet \n
|
||||
*/
|
||||
int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg);
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief get socket options
|
||||
@details Get socket option like as FLAG, TTL, MSS, and so on. Refer to @ref sockopt_type
|
||||
@param sn socket number
|
||||
@param sotype socket option type. refer to @ref sockopt_type
|
||||
@param arg Data type and value is determined according to <I>sotype</I>. \n
|
||||
<table>
|
||||
<tr> <td> @b sotype </td> <td>@b data type</td><td>@b value</td></tr>
|
||||
<tr> <td> @ref SO_FLAG </td> <td> uint8_t </td><td> @ref SF_ETHER_OWN, etc... </td> </tr>
|
||||
<tr> <td> @ref SO_TOS </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
|
||||
<tr> <td> @ref SO_MSS </td> <td> uint16_t </td><td> 0 ~ 65535 </td> </tr>
|
||||
<tr> <td> @ref SO_DESTIP </td> <td> uint8_t[4] </td><td> </td></tr>
|
||||
<tr> <td> @ref SO_DESTPORT </td> <td> uint16_t </td><td> </td></tr>
|
||||
<tr> <td> @ref SO_KEEPALIVEAUTO </td> <td> uint8_t </td><td> 0 ~ 255 </td></tr>
|
||||
<tr> <td> @ref SO_SENDBUF </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
|
||||
<tr> <td> @ref SO_RECVBUF </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
|
||||
<tr> <td> @ref SO_STATUS </td> <td> uint8_t </td><td> @ref SOCK_ESTABLISHED, etc.. </td></tr>
|
||||
<tr> <td> @ref SO_REMAINSIZE </td> <td> uint16_t </td><td> 0~ 65535 </td></tr>
|
||||
<tr> <td> @ref SO_PACKINFO </td> <td> uint8_t </td><td> @ref PACK_FIRST, etc... </td></tr>
|
||||
</table>
|
||||
@return
|
||||
- @b Success : @ref SOCK_OK \n
|
||||
- @b Fail
|
||||
- @ref SOCKERR_SOCKNUM - Invalid Socket number \n
|
||||
- @ref SOCKERR_SOCKOPT - Invalid socket option or its value \n
|
||||
- @ref SOCKERR_SOCKMODE - Invalid socket mode \n
|
||||
@note
|
||||
The option as PACK_REMAINED and SO_PACKINFO is valid only in NON-TCP mode and after call @ref recvfrom(). \n
|
||||
When SO_PACKINFO value is PACK_FIRST and the return value of recvfrom() is zero,
|
||||
This means the zero byte UDP data(UDP Header only) received.
|
||||
*/
|
||||
int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg);
|
||||
|
||||
//teddy 240122
|
||||
#if _WIZCHIP_ == W6100 || _WIZCHIP_ == W6300
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief Peeks a sub-message in SOCKETn RX buffer
|
||||
@details It peeks the incoming message of SOCKETn RX buffer. \n
|
||||
It can find the specified sub-message in the incoming message and
|
||||
return the length of incoming message before the sub-message. \n
|
||||
It is useful when you need to read each messages from multiple message in SOCKET RX buffer.
|
||||
@param sn SOCKET number
|
||||
@param submsg sub-message pointer to find
|
||||
@param subsize the length of <i>submsg</i>
|
||||
@return
|
||||
- Success : the length of incoming message length before the <i>submsg</i> \n
|
||||
- Fail : -1
|
||||
@note
|
||||
It is just return the length of incoming message before the found sub-message. It does not receive the message.\n
|
||||
So, after calling peeksockmsg, @ref _Sn_RX_RD_ is not changed.
|
||||
*/
|
||||
int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize);
|
||||
|
||||
#endif
|
||||
|
||||
// void setAddrlen_W6x00( uint8_t num) ;
|
||||
// uint8_t checkAddrlen_W6x00() ;
|
||||
|
||||
// void inline_setAddrlen_W6x00( uint8_t num);
|
||||
// uint8_t inline_CheckAddrlen_W6x00( void );
|
||||
|
||||
|
||||
#if 1 // by_Lihan
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief by_Lihan_W5x00
|
||||
*/
|
||||
int8_t connect_W5x00(uint8_t sn, uint8_t * addr, uint16_t port);
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief by_Lihan_Wx00
|
||||
*/
|
||||
int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define GET_MACRO_connect(_1, _2, _3, _4, NAME, ...) NAME
|
||||
#define CHOOSE_TESTCODE_MACRO(...) GET_MACRO_connect(__VA_ARGS__, connect_4, connect_3)
|
||||
|
||||
/**
|
||||
// by_LIhan for overroading
|
||||
// NOTE_LIHAN: Some sections of this code are not yet fully defined.
|
||||
@note
|
||||
In case of get 3 arguments - int8_t connect_W5x00(uint8_t sn, uint8_t * addr, uint16_t port );\n
|
||||
In case of get 4 arguments - int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen );
|
||||
*/
|
||||
|
||||
#define connect(...) CHOOSE_TESTCODE_MACRO(__VA_ARGS__)(__VA_ARGS__)
|
||||
|
||||
// In case of get 3 arguments
|
||||
#define connect_3(sn , addr , port ) connect_W5x00(sn , addr , port)
|
||||
|
||||
// In case of get 4 arguments
|
||||
#define connect_4(sn , addr , port, addrlen ) connect_W6x00(sn , addr , port,addrlen)
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief by_Lihan
|
||||
*/
|
||||
int32_t sendto_W5x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port);
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief by_Lihan
|
||||
*/
|
||||
int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
|
||||
|
||||
#define GET_MACRO_sendto(_1, _2, _3, _4, _5 , _6, NAME, ...) NAME
|
||||
#define CHOOSE_sendto_MACRO(...) GET_MACRO_sendto(__VA_ARGS__, sendto_6, sendto_5)
|
||||
|
||||
// by_LIhan for overroading
|
||||
// NOTE_LIHAN: Some sections of this code are not yet fully defined.
|
||||
// In case of get 3 arguments - int8_t sendto_W5x00(uint8_t sn, uint8_t * addr, uint16_t port );
|
||||
// In case of get 4 arguments - int8_t sendto_W6x00(uint8_t sn, uint8_t * addr, uint16_t port,uint8_t addrlen );
|
||||
#define sendto(...) CHOOSE_sendto_MACRO(__VA_ARGS__)(__VA_ARGS__)
|
||||
|
||||
// In case of get 3 arguments
|
||||
#define sendto_5( sn, buf, len, addr, port ) sendto_W5x00( sn, buf, len, addr, port)
|
||||
|
||||
// In case of get 4 arguments
|
||||
#define sendto_6( sn, buf, len, addr, port, addrlen ) sendto_W6x00( sn, buf, len, addr, port, addrlen)
|
||||
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief byLihan_W5x00
|
||||
*/
|
||||
int32_t recvfrom_W5x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port);
|
||||
/**
|
||||
@ingroup WIZnet_socket_APIs
|
||||
@brief byLihan_Wx00
|
||||
*/
|
||||
int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen);
|
||||
|
||||
|
||||
#define GET_MACRO_recvfrom(_1, _2, _3, _4, _5, _6 ,NAME, ...) NAME
|
||||
#define CHOOSE_recvfrom_MACRO(...) GET_MACRO_recvfrom(__VA_ARGS__, recvfrom_6, recvfrom_5)
|
||||
|
||||
// by_LIhanfor overroading
|
||||
// In case of get 3 arguments - int8_t recvfrom_W5x00(uint8_t sn, uint8_t * addr, uint16_t port );
|
||||
// In case of get 4 arguments - int8_t recvfrom_W6x00(uint8_t sn, uint8_t * addr, uint16_t port,uint8_t addrlen );
|
||||
#define recvfrom(...) CHOOSE_recvfrom_MACRO(__VA_ARGS__)(__VA_ARGS__)
|
||||
|
||||
// In case of get 3 arguments
|
||||
#define recvfrom_5(sn, buf, len, addr, port ) recvfrom_W5x00(sn, buf, len, addr, port)
|
||||
|
||||
// In case of get 4 arguments
|
||||
#define recvfrom_6(sn, buf, len, addr, port, addrlen ) recvfrom_W6x00(sn, buf, len, addr, port, addrlen )
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SOCKET_H_
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,23 +0,0 @@
|
||||
/**
|
||||
Copyright (c) 2021 WIZnet Co.,Ltd
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _PORT_COMMON_H_
|
||||
#define _PORT_COMMON_H_
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Includes
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
/* Common */
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/binary_info.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "hardware/spi.h"
|
||||
#include "hardware/dma.h"
|
||||
#include "hardware/clocks.h"
|
||||
|
||||
#endif /* _PORT_COMMON_H_ */
|
||||
@@ -1,388 +0,0 @@
|
||||
/**
|
||||
Copyright (c) 2022 WIZnet Co.,Ltd
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Includes
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include <stdio.h>
|
||||
|
||||
#include "port_common.h"
|
||||
|
||||
#include "wizchip_conf.h"
|
||||
#include "wizchip_spi.h"
|
||||
#include "board_list.h"
|
||||
|
||||
|
||||
#include "wizchip_qspi_pio.h"
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/binary_info.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "hardware/dma.h"
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Macros
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Variables
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
static critical_section_t g_wizchip_cri_sec;
|
||||
|
||||
#ifdef USE_SPI_DMA
|
||||
static uint dma_tx;
|
||||
static uint dma_rx;
|
||||
static dma_channel_config dma_channel_config_tx;
|
||||
static dma_channel_config dma_channel_config_rx;
|
||||
#endif
|
||||
|
||||
#ifdef USE_PIO
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
wiznet_spi_config_t g_spi_config = {
|
||||
.clock_div_major = WIZNET_SPI_CLKDIV_MAJOR_DEFAULT,
|
||||
.clock_div_minor = WIZNET_SPI_CLKDIV_MINOR_DEFAULT,
|
||||
.clock_pin = PIO_SPI_SCK_PIN,
|
||||
.data_io0_pin = PIO_SPI_DATA_IO0_PIN,
|
||||
.data_io1_pin = PIO_SPI_DATA_IO1_PIN,
|
||||
.data_io2_pin = PIO_SPI_DATA_IO2_PIN,
|
||||
.data_io3_pin = PIO_SPI_DATA_IO3_PIN,
|
||||
.cs_pin = PIN_CS,
|
||||
.reset_pin = PIN_RST,
|
||||
.irq_pin = PIN_INT,
|
||||
};
|
||||
#else
|
||||
wiznet_spi_config_t g_spi_config = {
|
||||
.data_in_pin = PIN_MISO,
|
||||
.data_out_pin = PIN_MOSI,
|
||||
.cs_pin = PIN_CS,
|
||||
.clock_pin = PIN_SCK,
|
||||
.irq_pin = PIN_INT,
|
||||
.reset_pin = PIN_RST,
|
||||
.clock_div_major = WIZNET_SPI_CLKDIV_MAJOR_DEFAULT,
|
||||
.clock_div_minor = WIZNET_SPI_CLKDIV_MINOR_DEFAULT,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
wiznet_spi_handle_t spi_handle;
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Functions
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void wizchip_select(void) {
|
||||
gpio_put(PIN_CS, 0);
|
||||
}
|
||||
|
||||
static inline void wizchip_deselect(void) {
|
||||
gpio_put(PIN_CS, 1);
|
||||
|
||||
}
|
||||
|
||||
void wizchip_reset() {
|
||||
gpio_init(PIN_RST);
|
||||
|
||||
#if defined(USE_PIO) && (_WIZCHIP_ == W5500)
|
||||
gpio_pull_up(PIN_RST);
|
||||
gpio_set_dir(PIN_RST, GPIO_OUT);
|
||||
sleep_ms(5);
|
||||
#else
|
||||
gpio_set_dir(PIN_RST, GPIO_OUT);
|
||||
#endif
|
||||
gpio_put(PIN_RST, 0);
|
||||
sleep_ms(100);
|
||||
|
||||
gpio_put(PIN_RST, 1);
|
||||
sleep_ms(100);
|
||||
|
||||
bi_decl(bi_1pin_with_name(PIN_RST, "WIZCHIP RESET"));
|
||||
}
|
||||
|
||||
#ifndef USE_PIO
|
||||
static uint8_t wizchip_read(void) {
|
||||
uint8_t rx_data = 0;
|
||||
uint8_t tx_data = 0xFF;
|
||||
|
||||
spi_read_blocking(SPI_PORT, tx_data, &rx_data, 1);
|
||||
|
||||
return rx_data;
|
||||
}
|
||||
|
||||
static void wizchip_write(uint8_t tx_data) {
|
||||
spi_write_blocking(SPI_PORT, &tx_data, 1);
|
||||
}
|
||||
|
||||
|
||||
#if (_WIZCHIP_ == W6100)
|
||||
static void wizchip_read_buf(uint8_t* rx_data, datasize_t len) {
|
||||
uint8_t tx_data = 0xFF;
|
||||
|
||||
spi_read_blocking(SPI_PORT, tx_data, rx_data, len);
|
||||
}
|
||||
|
||||
static void wizchip_write_buf(uint8_t* tx_data, datasize_t len) {
|
||||
spi_write_blocking(SPI_PORT, tx_data, len);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef USE_SPI_DMA
|
||||
static void wizchip_read_burst(uint8_t *pBuf, uint16_t len) {
|
||||
uint8_t dummy_data = 0xFF;
|
||||
|
||||
channel_config_set_read_increment(&dma_channel_config_tx, false);
|
||||
channel_config_set_write_increment(&dma_channel_config_tx, false);
|
||||
dma_channel_configure(dma_tx, &dma_channel_config_tx,
|
||||
&spi_get_hw(SPI_PORT)->dr, // write address
|
||||
&dummy_data, // read address
|
||||
len, // element count (each element is of size transfer_data_size)
|
||||
false); // don't start yet
|
||||
|
||||
channel_config_set_read_increment(&dma_channel_config_rx, false);
|
||||
channel_config_set_write_increment(&dma_channel_config_rx, true);
|
||||
dma_channel_configure(dma_rx, &dma_channel_config_rx,
|
||||
pBuf, // write address
|
||||
&spi_get_hw(SPI_PORT)->dr, // read address
|
||||
len, // element count (each element is of size transfer_data_size)
|
||||
false); // don't start yet
|
||||
|
||||
dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));
|
||||
dma_channel_wait_for_finish_blocking(dma_rx);
|
||||
}
|
||||
|
||||
static void wizchip_write_burst(uint8_t *pBuf, uint16_t len) {
|
||||
uint8_t dummy_data;
|
||||
|
||||
channel_config_set_read_increment(&dma_channel_config_tx, true);
|
||||
channel_config_set_write_increment(&dma_channel_config_tx, false);
|
||||
dma_channel_configure(dma_tx, &dma_channel_config_tx,
|
||||
&spi_get_hw(SPI_PORT)->dr, // write address
|
||||
pBuf, // read address
|
||||
len, // element count (each element is of size transfer_data_size)
|
||||
false); // don't start yet
|
||||
|
||||
channel_config_set_read_increment(&dma_channel_config_rx, false);
|
||||
channel_config_set_write_increment(&dma_channel_config_rx, false);
|
||||
dma_channel_configure(dma_rx, &dma_channel_config_rx,
|
||||
&dummy_data, // write address
|
||||
&spi_get_hw(SPI_PORT)->dr, // read address
|
||||
len, // element count (each element is of size transfer_data_size)
|
||||
false); // don't start yet
|
||||
|
||||
dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));
|
||||
dma_channel_wait_for_finish_blocking(dma_rx);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static void wizchip_critical_section_lock(void) {
|
||||
critical_section_enter_blocking(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
static void wizchip_critical_section_unlock(void) {
|
||||
critical_section_exit(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
void wizchip_spi_initialize(void) {
|
||||
#ifdef USE_PIO
|
||||
spi_handle = wiznet_spi_pio_open(&g_spi_config);
|
||||
(*spi_handle)->set_active(spi_handle);
|
||||
#else
|
||||
// this example will use SPI0 at 5MHz
|
||||
spi_init(SPI_PORT, SPI_CLK * 1000 * 1000);
|
||||
|
||||
gpio_set_function(PIN_SCK, GPIO_FUNC_SPI);
|
||||
gpio_set_function(PIN_MOSI, GPIO_FUNC_SPI);
|
||||
gpio_set_function(PIN_MISO, GPIO_FUNC_SPI);
|
||||
|
||||
// make the SPI pins available to picotool
|
||||
bi_decl(bi_3pins_with_func(PIN_MISO, PIN_MOSI, PIN_SCK, GPIO_FUNC_SPI));
|
||||
|
||||
// chip select is active-low, so we'll initialise it to a driven-high state
|
||||
gpio_init(PIN_CS);
|
||||
gpio_set_dir(PIN_CS, GPIO_OUT);
|
||||
gpio_put(PIN_CS, 1);
|
||||
|
||||
// make the SPI pins available to picotool
|
||||
bi_decl(bi_1pin_with_name(PIN_CS, "W5x00 CHIP SELECT"));
|
||||
|
||||
#ifdef USE_SPI_DMA
|
||||
dma_tx = dma_claim_unused_channel(true);
|
||||
dma_rx = dma_claim_unused_channel(true);
|
||||
|
||||
dma_channel_config_tx = dma_channel_get_default_config(dma_tx);
|
||||
channel_config_set_transfer_data_size(&dma_channel_config_tx, DMA_SIZE_8);
|
||||
channel_config_set_dreq(&dma_channel_config_tx, DREQ_SPI0_TX);
|
||||
|
||||
// We set the inbound DMA to transfer from the SPI receive FIFO to a memory buffer paced by the SPI RX FIFO DREQ
|
||||
// We coinfigure the read address to remain unchanged for each element, but the write
|
||||
// address to increment (so data is written throughout the buffer)
|
||||
dma_channel_config_rx = dma_channel_get_default_config(dma_rx);
|
||||
channel_config_set_transfer_data_size(&dma_channel_config_rx, DMA_SIZE_8);
|
||||
channel_config_set_dreq(&dma_channel_config_rx, DREQ_SPI0_RX);
|
||||
channel_config_set_read_increment(&dma_channel_config_rx, false);
|
||||
channel_config_set_write_increment(&dma_channel_config_rx, true);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizchip_cris_initialize(void) {
|
||||
critical_section_init(&g_wizchip_cri_sec);
|
||||
reg_wizchip_cris_cbfunc(wizchip_critical_section_lock, wizchip_critical_section_unlock);
|
||||
}
|
||||
|
||||
void wizchip_initialize(void) {
|
||||
|
||||
#ifdef USE_PIO
|
||||
(*spi_handle)->frame_end();
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
reg_wizchip_qspi_cbfunc((*spi_handle)->read_byte, (*spi_handle)->write_byte);
|
||||
#else
|
||||
reg_wizchip_spi_cbfunc((*spi_handle)->read_byte, (*spi_handle)->write_byte);
|
||||
reg_wizchip_spiburst_cbfunc((*spi_handle)->read_buffer, (*spi_handle)->write_buffer);
|
||||
#endif
|
||||
reg_wizchip_cs_cbfunc((*spi_handle)->frame_start, (*spi_handle)->frame_end);
|
||||
|
||||
#else
|
||||
/* Deselect the FLASH : chip select high */
|
||||
wizchip_deselect();
|
||||
/* CS function register */
|
||||
reg_wizchip_cs_cbfunc(wizchip_select, wizchip_deselect);
|
||||
/* SPI function register */
|
||||
#if (_WIZCHIP_ == W6100)
|
||||
reg_wizchip_spi_cbfunc(wizchip_read, wizchip_write, wizchip_read_buf, wizchip_write_buf);
|
||||
#else
|
||||
reg_wizchip_spi_cbfunc(wizchip_read, wizchip_write);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef USE_SPI_DMA
|
||||
reg_wizchip_spiburst_cbfunc(wizchip_read_burst, wizchip_write_burst);
|
||||
#endif
|
||||
|
||||
/* W5x00, W6x00 initialize */
|
||||
uint8_t temp;
|
||||
#if (_WIZCHIP_ == W5100S)
|
||||
uint8_t memsize[2][4] = {{2, 2, 2, 2}, {2, 2, 2, 2}};
|
||||
#elif (_WIZCHIP_ == W5500)
|
||||
uint8_t memsize[2][8] = {{2, 2, 2, 2, 2, 2, 2, 2}, {2, 2, 2, 2, 2, 2, 2, 2}};
|
||||
#elif (_WIZCHIP_ == W6100)
|
||||
uint8_t memsize[2][8] = {{2, 2, 2, 2, 2, 2, 2, 2}, {2, 2, 2, 2, 2, 2, 2, 2}};
|
||||
#elif (_WIZCHIP_ == W6300)
|
||||
uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}};
|
||||
#endif
|
||||
|
||||
if (ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize) == -1) {
|
||||
#if _WIZCHIP_ <= W5500
|
||||
printf(" W5x00 initialized fail\n");
|
||||
#else
|
||||
printf(" W6x00 initialized fail\n");
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_check(void) {
|
||||
#if (_WIZCHIP_ == W5100S)
|
||||
/* Read version register */
|
||||
if (getVER() != 0x51) {
|
||||
printf(" ACCESS ERR : VERSION != 0x51, read value = 0x%02x\n", getVER());
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#elif (_WIZCHIP_ == W5500)
|
||||
/* Read version register */
|
||||
if (getVERSIONR() != 0x04) {
|
||||
printf(" ACCESS ERR : VERSION != 0x04, read value = 0x%02x\n", getVERSIONR());
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#elif (_WIZCHIP_ == W6100)
|
||||
/* Read version register */
|
||||
if (getCIDR() != 0x6100) {
|
||||
printf(" ACCESS ERR : VERSION != 0x6100, read value = 0x%02x\n", getCIDR());
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#elif (_WIZCHIP_ == W6300)
|
||||
/* Read version register */
|
||||
if (getCIDR() != 0x6300) {
|
||||
printf(" ACCESS ERR : VERSION != 0x6100, read value = 0x%02x\n", getCIDR());
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Network */
|
||||
void network_initialize(wiz_NetInfo net_info) {
|
||||
#if _WIZCHIP_ <= W5500
|
||||
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
||||
#else
|
||||
uint8_t syslock = SYS_NET_LOCK;
|
||||
ctlwizchip(CW_SYS_UNLOCK, &syslock);
|
||||
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
||||
#endif
|
||||
}
|
||||
|
||||
void print_network_information(wiz_NetInfo net_info) {
|
||||
uint8_t tmp_str[8] = {
|
||||
0,
|
||||
};
|
||||
|
||||
ctlnetwork(CN_GET_NETINFO, (void *)&net_info);
|
||||
ctlwizchip(CW_GET_ID, (void *)tmp_str);
|
||||
#if _WIZCHIP_ <= W5500
|
||||
if (net_info.dhcp == NETINFO_DHCP) {
|
||||
printf("====================================================================================================\n");
|
||||
printf(" %s network configuration : DHCP\n\n", (char *)tmp_str);
|
||||
} else {
|
||||
printf("====================================================================================================\n");
|
||||
printf(" %s network configuration : static\n\n", (char *)tmp_str);
|
||||
}
|
||||
|
||||
printf(" MAC : %02X:%02X:%02X:%02X:%02X:%02X\n", net_info.mac[0], net_info.mac[1], net_info.mac[2], net_info.mac[3], net_info.mac[4], net_info.mac[5]);
|
||||
printf(" IP : %d.%d.%d.%d\n", net_info.ip[0], net_info.ip[1], net_info.ip[2], net_info.ip[3]);
|
||||
printf(" Subnet Mask : %d.%d.%d.%d\n", net_info.sn[0], net_info.sn[1], net_info.sn[2], net_info.sn[3]);
|
||||
printf(" Gateway : %d.%d.%d.%d\n", net_info.gw[0], net_info.gw[1], net_info.gw[2], net_info.gw[3]);
|
||||
printf(" DNS : %d.%d.%d.%d\n", net_info.dns[0], net_info.dns[1], net_info.dns[2], net_info.dns[3]);
|
||||
printf("====================================================================================================\n\n");
|
||||
#else
|
||||
printf("==========================================================\n");
|
||||
printf(" %s network configuration\n\n", (char *)tmp_str);
|
||||
|
||||
printf(" MAC : %02X:%02X:%02X:%02X:%02X:%02X\n", net_info.mac[0], net_info.mac[1], net_info.mac[2], net_info.mac[3], net_info.mac[4], net_info.mac[5]);
|
||||
printf(" IP : %d.%d.%d.%d\n", net_info.ip[0], net_info.ip[1], net_info.ip[2], net_info.ip[3]);
|
||||
printf(" Subnet Mask : %d.%d.%d.%d\n", net_info.sn[0], net_info.sn[1], net_info.sn[2], net_info.sn[3]);
|
||||
printf(" Gateway : %d.%d.%d.%d\n", net_info.gw[0], net_info.gw[1], net_info.gw[2], net_info.gw[3]);
|
||||
printf(" DNS : %d.%d.%d.%d\n", net_info.dns[0], net_info.dns[1], net_info.dns[2], net_info.dns[3]);
|
||||
print_ipv6_addr(" GW6 ", net_info.gw6);
|
||||
print_ipv6_addr(" LLA ", net_info.lla);
|
||||
print_ipv6_addr(" GUA ", net_info.gua);
|
||||
print_ipv6_addr(" SUB6", net_info.sn6);
|
||||
print_ipv6_addr(" DNS6", net_info.dns6);
|
||||
printf("==========================================================\n\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
void print_ipv6_addr(uint8_t* name, uint8_t* ip6addr) {
|
||||
printf("%s : ", name);
|
||||
printf("%04X:%04X", ((uint16_t)ip6addr[0] << 8) | ((uint16_t)ip6addr[1]), ((uint16_t)ip6addr[2] << 8) | ((uint16_t)ip6addr[3]));
|
||||
printf(":%04X:%04X", ((uint16_t)ip6addr[4] << 8) | ((uint16_t)ip6addr[5]), ((uint16_t)ip6addr[6] << 8) | ((uint16_t)ip6addr[7]));
|
||||
printf(":%04X:%04X", ((uint16_t)ip6addr[8] << 8) | ((uint16_t)ip6addr[9]), ((uint16_t)ip6addr[10] << 8) | ((uint16_t)ip6addr[11]));
|
||||
printf(":%04X:%04X\r\n", ((uint16_t)ip6addr[12] << 8) | ((uint16_t)ip6addr[13]), ((uint16_t)ip6addr[14] << 8) | ((uint16_t)ip6addr[15]));
|
||||
}
|
||||
@@ -1,236 +0,0 @@
|
||||
/**
|
||||
Copyright (c) 2022 WIZnet Co.,Ltd
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _WIZCHIP_SPI_H_
|
||||
#define _WIZCHIP_SPI_H_
|
||||
|
||||
#include "board_list.h"
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Macros
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
/* SPI */
|
||||
#if (DEVICE_BOARD_NAME == W55RP20_EVB_PICO)
|
||||
|
||||
#define USE_PIO
|
||||
#define WIZNET_SPI_CLKDIV_MAJOR_DEFAULT 2
|
||||
#define WIZNET_SPI_CLKDIV_MINOR_DEFAULT 0
|
||||
|
||||
#define PIN_CS 20
|
||||
#define PIN_SCK 21
|
||||
#define PIN_MOSI 23
|
||||
#define PIN_MISO 22
|
||||
#define PIN_INT 24
|
||||
#define PIN_RST 25
|
||||
|
||||
#elif (DEVICE_BOARD_NAME == W6300_EVB_PICO || DEVICE_BOARD_NAME == W6300_EVB_PICO2)
|
||||
|
||||
#define USE_PIO
|
||||
#define WIZNET_SPI_CLKDIV_MAJOR_DEFAULT 2
|
||||
#define WIZNET_SPI_CLKDIV_MINOR_DEFAULT 0
|
||||
|
||||
#define PIN_INT 15
|
||||
#define PIN_CS 16
|
||||
#define PIO_SPI_SCK_PIN 17
|
||||
#define PIO_SPI_DATA_IO0_PIN 18
|
||||
#define PIO_SPI_DATA_IO1_PIN 19
|
||||
#define PIO_SPI_DATA_IO2_PIN 20
|
||||
#define PIO_SPI_DATA_IO3_PIN 21
|
||||
#define PIN_RST 22
|
||||
|
||||
#else
|
||||
/* SPI */
|
||||
#define SPI_PORT spi0
|
||||
#define SPI_CLK 10
|
||||
|
||||
#define PIN_SCK 18
|
||||
#define PIN_MOSI 19
|
||||
#define PIN_MISO 16
|
||||
#define PIN_CS 17
|
||||
#define PIN_RST 20
|
||||
#define PIN_INT 21
|
||||
|
||||
/* Use SPI DMA */
|
||||
//#define USE_SPI_DMA // if you want to use SPI DMA, uncomment.
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
----------------------------------------------------------------------------------------------------
|
||||
Functions
|
||||
----------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
/* wizchip */
|
||||
/*! \brief Set CS pin
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set chip select pin of spi0 to low(Active low).
|
||||
|
||||
\param none
|
||||
*/
|
||||
static inline void wizchip_select(void);
|
||||
|
||||
/*! \brief Set CS pin
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set chip select pin of spi0 to high(Inactive high).
|
||||
|
||||
\param none
|
||||
*/
|
||||
static inline void wizchip_deselect(void);
|
||||
|
||||
/*! \brief Read from an SPI device, blocking
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set spi_read_blocking function.
|
||||
Read byte from SPI to rx_data buffer.
|
||||
Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
|
||||
|
||||
\param none
|
||||
*/
|
||||
static uint8_t wizchip_read(void);
|
||||
|
||||
/*! \brief Write to an SPI device, blocking
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set spi_write_blocking function.
|
||||
Write byte from tx_data buffer to SPI device.
|
||||
Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
|
||||
|
||||
\param tx_data Buffer of data to write
|
||||
*/
|
||||
static void wizchip_write(uint8_t tx_data);
|
||||
|
||||
|
||||
#if (_WIZCHIP_ == W6100)
|
||||
static void wizchip_read_buf(uint8_t* rx_data, datasize_t len);
|
||||
static void wizchip_write_buf(uint8_t* tx_data, datasize_t len);
|
||||
#endif
|
||||
|
||||
#ifdef USE_SPI_DMA
|
||||
/*! \brief Configure all DMA parameters and optionally start transfer
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Configure all DMA parameters and read from DMA
|
||||
|
||||
\param pBuf Buffer of data to read
|
||||
\param len element count (each element is of size transfer_data_size)
|
||||
*/
|
||||
static void wizchip_read_burst(uint8_t *pBuf, uint16_t len);
|
||||
|
||||
/*! \brief Configure all DMA parameters and optionally start transfer
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Configure all DMA parameters and write to DMA
|
||||
|
||||
\param pBuf Buffer of data to write
|
||||
\param len element count (each element is of size transfer_data_size)
|
||||
*/
|
||||
static void wizchip_write_burst(uint8_t *pBuf, uint16_t len);
|
||||
#endif
|
||||
|
||||
/*! \brief Enter a critical section
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set ciritical section enter blocking function.
|
||||
If the spin lock associated with this critical section is in use, then this
|
||||
method will block until it is released.
|
||||
|
||||
\param none
|
||||
*/
|
||||
static void wizchip_critical_section_lock(void);
|
||||
|
||||
/*! \brief Release a critical section
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set ciritical section exit function.
|
||||
Release a critical section.
|
||||
|
||||
\param none
|
||||
*/
|
||||
static void wizchip_critical_section_unlock(void);
|
||||
|
||||
/*! \brief Initialize SPI instances and Set DMA channel
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set GPIO to spi0.
|
||||
Puts the SPI into a known state, and enable it.
|
||||
Set DMA channel completion channel.
|
||||
|
||||
\param none
|
||||
*/
|
||||
void wizchip_spi_initialize(void);
|
||||
|
||||
/*! \brief Initialize a critical section structure
|
||||
\ingroup wizchip_spi
|
||||
|
||||
The critical section is initialized ready for use.
|
||||
Registers callback function for critical section for WIZchip.
|
||||
|
||||
\param none
|
||||
*/
|
||||
void wizchip_cris_initialize(void);
|
||||
|
||||
/*! \brief wizchip reset
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set a reset pin and reset.
|
||||
|
||||
\param none
|
||||
*/
|
||||
void wizchip_reset(void);
|
||||
|
||||
/*! \brief Initialize WIZchip
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set callback function to read/write byte using SPI & QSPI.
|
||||
Set callback function for WIZchip select/deselect.
|
||||
Set memory size of wizchip and monitor PHY link status.
|
||||
|
||||
\param none
|
||||
*/
|
||||
void wizchip_initialize(void);
|
||||
|
||||
/*! \brief Check chip version
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Get version information.
|
||||
|
||||
\param none
|
||||
*/
|
||||
void wizchip_check(void);
|
||||
|
||||
/* Network */
|
||||
/*! \brief Initialize network
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Set network information.
|
||||
|
||||
\param net_info network information.
|
||||
*/
|
||||
void network_initialize(wiz_NetInfo net_info);
|
||||
|
||||
/*! \brief Print network information
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Print network information about MAC address, IP address, Subnet mask, Gateway, DHCP and DNS address.
|
||||
|
||||
\param net_info network information.
|
||||
*/
|
||||
void print_network_information(wiz_NetInfo net_info);
|
||||
|
||||
/*! \brief Print IPv6 Address
|
||||
\ingroup wizchip_spi
|
||||
|
||||
Print IPv6 Address.
|
||||
|
||||
\param net_info network information.
|
||||
*/
|
||||
void print_ipv6_addr(uint8_t* name, uint8_t* ip6addr);
|
||||
|
||||
#endif /* _WIZCHIP_SPI_H_ */
|
||||
@@ -0,0 +1 @@
|
||||
#define W6300_EVB_PICO2 9
|
||||
@@ -0,0 +1,11 @@
|
||||
#ifndef _PORT_COMMON_H_
|
||||
#define _PORT_COMMON_H_
|
||||
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/binary_info.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "hardware/spi.h"
|
||||
#include "hardware/dma.h"
|
||||
#include "hardware/clocks.h"
|
||||
|
||||
#endif /* _PORT_COMMON_H_ */
|
||||
+578
@@ -0,0 +1,578 @@
|
||||
#include "socket.h"
|
||||
|
||||
#define SOCK_ANY_PORT_NUM 0xC000
|
||||
|
||||
static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
|
||||
static uint16_t sock_io_mode = 0;
|
||||
static uint16_t sock_is_sending = 0;
|
||||
static uint16_t sock_remained_size[_WIZCHIP_SOCK_NUM_] = {0,};
|
||||
uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
|
||||
|
||||
#define CHECK_SOCKNUM() do { if(sn >= _WIZCHIP_SOCK_NUM_) return SOCKERR_SOCKNUM; } while(0)
|
||||
#define CHECK_SOCKMODE(mode) do { if((getSn_MR(sn) & 0x0F) != mode) return SOCKERR_SOCKMODE; } while(0)
|
||||
#define CHECK_TCPMODE() do { if((getSn_MR(sn) & 0x03) != 0x01) return SOCKERR_SOCKMODE; } while(0)
|
||||
#define CHECK_UDPMODE() do { if((getSn_MR(sn) & 0x03) != 0x02) return SOCKERR_SOCKMODE; } while(0)
|
||||
#define CHECK_IPMODE() do { if((getSn_MR(sn) & 0x07) != 0x03) return SOCKERR_SOCKMODE; } while(0)
|
||||
#define CHECK_DGRAMMODE() do { if(getSn_MR(sn) == Sn_MR_CLOSED) return SOCKERR_SOCKMODE; if((getSn_MR(sn) & 0x03) == 0x01) return SOCKERR_SOCKMODE; } while(0)
|
||||
#define CHECK_SOCKINIT() do { if((getSn_SR(sn) != SOCK_INIT)) return SOCKERR_SOCKINIT; } while(0)
|
||||
#define CHECK_SOCKDATA() do { if(len == 0) return SOCKERR_DATALEN; } while(0)
|
||||
#define CHECK_IPZERO(addr, addrlen) do { uint16_t ipzero=0; for(uint8_t i=0; i<addrlen; i++) ipzero += (uint16_t)addr[i]; if(ipzero == 0) return SOCKERR_IPINVALID; } while(0)
|
||||
|
||||
#define Sn_MR_TCP4 (Sn_MR_TCP)
|
||||
#define Sn_MR_UDP4 (Sn_MR_UDP)
|
||||
#define Sn_MR_IPRAW4 (Sn_MR_IPRAW)
|
||||
#define Sn_MR_TCP6 (0x09)
|
||||
#define Sn_MR_UDP6 (0x0A)
|
||||
#define Sn_MR_IPRAW6 (0x0B)
|
||||
#define Sn_MR_TCPD (0x0D)
|
||||
#define Sn_MR_UDPD (0x0E)
|
||||
|
||||
int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag) {
|
||||
uint8_t taddr[16];
|
||||
CHECK_SOCKNUM();
|
||||
switch (protocol & 0x0F) {
|
||||
case Sn_MR_TCP4:
|
||||
getSIPR(taddr);
|
||||
CHECK_IPZERO(taddr, 4);
|
||||
break;
|
||||
case Sn_MR_TCP6:
|
||||
getLLAR(taddr);
|
||||
CHECK_IPZERO(taddr, 16);
|
||||
break;
|
||||
case Sn_MR_TCPD:
|
||||
getSIPR(taddr);
|
||||
CHECK_IPZERO(taddr, 4);
|
||||
getLLAR(taddr);
|
||||
CHECK_IPZERO(taddr, 16);
|
||||
break;
|
||||
case Sn_MR_UDP:
|
||||
case Sn_MR_UDP6:
|
||||
case Sn_MR_UDPD:
|
||||
case Sn_MR_MACRAW:
|
||||
case Sn_MR_IPRAW4:
|
||||
case Sn_MR_IPRAW6:
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_SOCKMODE;
|
||||
}
|
||||
if ((flag & 0x04) != 0) return SOCKERR_SOCKFLAG;
|
||||
|
||||
if (flag != 0) {
|
||||
switch (protocol) {
|
||||
case Sn_MR_MACRAW:
|
||||
if ((flag & (SF_DHA_MANUAL | SF_FORCE_ARP)) != 0) return SOCKERR_SOCKFLAG;
|
||||
break;
|
||||
case Sn_MR_TCP4:
|
||||
case Sn_MR_TCP6:
|
||||
case Sn_MR_TCPD:
|
||||
if ((flag & (SF_MULTI_ENABLE | SF_UNI_BLOCK)) != 0) return SOCKERR_SOCKFLAG;
|
||||
break;
|
||||
case Sn_MR_IPRAW4:
|
||||
case Sn_MR_IPRAW6:
|
||||
if (flag != 0) return SOCKERR_SOCKFLAG;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
close(sn);
|
||||
setSn_MR(sn, (protocol | (flag & 0xF0)));
|
||||
setSn_MR2(sn, flag & 0x03);
|
||||
if (!port) {
|
||||
port = sock_any_port++;
|
||||
if (sock_any_port == 0xFFF0) sock_any_port = SOCK_ANY_PORT_NUM;
|
||||
}
|
||||
setSn_PORTR(sn, port);
|
||||
setSn_CR(sn, Sn_CR_OPEN);
|
||||
while (getSn_CR(sn));
|
||||
sock_io_mode &= ~(1 << sn);
|
||||
sock_io_mode |= ((flag & (SF_IO_NONBLOCK >> 3)) << sn);
|
||||
sock_is_sending &= ~(1 << sn);
|
||||
sock_remained_size[sn] = 0;
|
||||
sock_pack_info[sn] = PACK_COMPLETED;
|
||||
while (getSn_SR(sn) == SOCK_CLOSED);
|
||||
return (int8_t)sn;
|
||||
}
|
||||
|
||||
int8_t close(uint8_t sn) {
|
||||
CHECK_SOCKNUM();
|
||||
setSn_CR(sn, Sn_CR_CLOSE);
|
||||
while (getSn_CR(sn));
|
||||
setSn_IR(sn, 0xFF);
|
||||
sock_io_mode &= ~(1 << sn);
|
||||
sock_is_sending &= ~(1 << sn);
|
||||
sock_remained_size[sn] = 0;
|
||||
sock_pack_info[sn] = PACK_NONE;
|
||||
while (getSn_SR(sn) != SOCK_CLOSED);
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int8_t listen(uint8_t sn) {
|
||||
CHECK_SOCKNUM();
|
||||
CHECK_TCPMODE();
|
||||
CHECK_SOCKINIT();
|
||||
setSn_CR(sn, Sn_CR_LISTEN);
|
||||
while (getSn_CR(sn));
|
||||
while (getSn_SR(sn) != SOCK_LISTEN) {
|
||||
close(sn);
|
||||
return SOCKERR_SOCKCLOSED;
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen) {
|
||||
CHECK_SOCKNUM();
|
||||
CHECK_TCPMODE();
|
||||
CHECK_SOCKINIT();
|
||||
CHECK_IPZERO(addr, addrlen);
|
||||
if (port == 0) return SOCKERR_PORTZERO;
|
||||
|
||||
setSn_DPORTR(sn, port);
|
||||
if (addrlen == 16) {
|
||||
if (getSn_MR(sn) & 0x08) {
|
||||
setSn_DIP6R(sn, addr);
|
||||
setSn_CR(sn, Sn_CR_CONNECT6);
|
||||
} else {
|
||||
return SOCKERR_SOCKMODE;
|
||||
}
|
||||
} else {
|
||||
if (getSn_MR(sn) == Sn_MR_TCP6) return SOCKERR_SOCKMODE;
|
||||
setSn_DIPR(sn, addr);
|
||||
setSn_CR(sn, Sn_CR_CONNECT);
|
||||
}
|
||||
while (getSn_CR(sn));
|
||||
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
||||
while (getSn_SR(sn) != SOCK_ESTABLISHED) {
|
||||
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
||||
setSn_IR(sn, Sn_IR_TIMEOUT);
|
||||
return SOCKERR_TIMEOUT;
|
||||
}
|
||||
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int8_t disconnect(uint8_t sn) {
|
||||
CHECK_SOCKNUM();
|
||||
CHECK_TCPMODE();
|
||||
if (getSn_SR(sn) != SOCK_CLOSED) {
|
||||
setSn_CR(sn, Sn_CR_DISCON);
|
||||
while (getSn_CR(sn));
|
||||
sock_is_sending &= ~(1 << sn);
|
||||
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
||||
while (getSn_SR(sn) != SOCK_CLOSED) {
|
||||
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
||||
close(sn);
|
||||
return SOCKERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int32_t send(uint8_t sn, uint8_t * buf, uint16_t len) {
|
||||
uint8_t tmp = 0;
|
||||
uint16_t freesize = 0;
|
||||
|
||||
freesize = getSn_TxMAX(sn);
|
||||
if (len > freesize) len = freesize;
|
||||
while (1) {
|
||||
freesize = (uint16_t)getSn_TX_FSR(sn);
|
||||
tmp = getSn_SR(sn);
|
||||
if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT)) {
|
||||
if (tmp == SOCK_CLOSED) close(sn);
|
||||
return SOCKERR_SOCKSTATUS;
|
||||
}
|
||||
if ((sock_io_mode & (1 << sn)) && (len > freesize)) return SOCK_BUSY;
|
||||
if (len <= freesize) break;
|
||||
}
|
||||
wiz_send_data(sn, buf, len);
|
||||
if (sock_is_sending & (1 << sn)) {
|
||||
while (!(getSn_IR(sn) & Sn_IR_SENDOK)) {
|
||||
tmp = getSn_SR(sn);
|
||||
if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT)) {
|
||||
if ((tmp == SOCK_CLOSED) || (getSn_IR(sn) & Sn_IR_TIMEOUT)) close(sn);
|
||||
return SOCKERR_SOCKSTATUS;
|
||||
}
|
||||
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
||||
}
|
||||
setSn_IR(sn, Sn_IR_SENDOK);
|
||||
}
|
||||
setSn_CR(sn, Sn_CR_SEND);
|
||||
while (getSn_CR(sn));
|
||||
sock_is_sending |= (1 << sn);
|
||||
return len;
|
||||
}
|
||||
|
||||
int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len) {
|
||||
uint8_t tmp = 0;
|
||||
uint16_t recvsize = 0;
|
||||
|
||||
CHECK_SOCKNUM();
|
||||
CHECK_SOCKMODE(Sn_MR_TCP);
|
||||
CHECK_SOCKDATA();
|
||||
|
||||
recvsize = getSn_RxMAX(sn);
|
||||
if (recvsize < len) len = recvsize;
|
||||
|
||||
while (1) {
|
||||
recvsize = (uint16_t)getSn_RX_RSR(sn);
|
||||
tmp = getSn_SR(sn);
|
||||
if (tmp != SOCK_ESTABLISHED) {
|
||||
if (tmp == SOCK_CLOSE_WAIT) {
|
||||
if (recvsize != 0) break;
|
||||
else if (getSn_TX_FSR(sn) == getSn_TxMAX(sn)) {
|
||||
close(sn);
|
||||
return SOCKERR_SOCKSTATUS;
|
||||
}
|
||||
} else {
|
||||
close(sn);
|
||||
return SOCKERR_SOCKSTATUS;
|
||||
}
|
||||
}
|
||||
if (recvsize != 0) break;
|
||||
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
||||
};
|
||||
|
||||
if (recvsize < len) len = recvsize;
|
||||
wiz_recv_data(sn, buf, len);
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
return (int32_t)len;
|
||||
}
|
||||
|
||||
int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen) {
|
||||
uint8_t tmp = 0;
|
||||
uint8_t tcmd = Sn_CR_SEND;
|
||||
uint16_t freesize = 0;
|
||||
|
||||
CHECK_SOCKNUM();
|
||||
switch (getSn_MR(sn) & 0x0F) {
|
||||
case Sn_MR_UDP:
|
||||
case Sn_MR_MACRAW:
|
||||
case Sn_MR_IPRAW:
|
||||
case Sn_MR_IPRAW6:
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_SOCKMODE;
|
||||
}
|
||||
tmp = getSn_MR(sn);
|
||||
if (tmp != Sn_MR_MACRAW) {
|
||||
if (addrlen == 16) {
|
||||
if (tmp & 0x08) {
|
||||
setSn_DIP6R(sn, addr);
|
||||
tcmd = Sn_CR_SEND6;
|
||||
} else {
|
||||
return SOCKERR_SOCKMODE;
|
||||
}
|
||||
} else if (addrlen == 4) {
|
||||
if (tmp == Sn_MR_UDP6 || tmp == Sn_MR_IPRAW6) return SOCKERR_SOCKMODE;
|
||||
setSn_DIPR(sn, addr);
|
||||
tcmd = Sn_CR_SEND;
|
||||
} else {
|
||||
return SOCKERR_IPINVALID;
|
||||
}
|
||||
}
|
||||
if ((tmp & 0x03) == 0x02) {
|
||||
if (port) {
|
||||
setSn_DPORTR(sn, port);
|
||||
} else {
|
||||
return SOCKERR_PORTZERO;
|
||||
}
|
||||
}
|
||||
|
||||
freesize = getSn_TxMAX(sn);
|
||||
if (len > freesize) len = freesize;
|
||||
while (1) {
|
||||
freesize = getSn_TX_FSR(sn);
|
||||
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
||||
if ((sock_io_mode & (1 << sn)) && (len > freesize)) return SOCK_BUSY;
|
||||
if (len <= freesize) break;
|
||||
};
|
||||
wiz_send_data(sn, buf, len);
|
||||
setSn_CR(sn, tcmd);
|
||||
while (getSn_CR(sn));
|
||||
while (1) {
|
||||
tmp = getSn_IR(sn);
|
||||
if (tmp & Sn_IR_SENDOK) {
|
||||
setSn_IR(sn, Sn_IR_SENDOK);
|
||||
break;
|
||||
} else if (tmp & Sn_IR_TIMEOUT) {
|
||||
setSn_IR(sn, Sn_IR_TIMEOUT);
|
||||
return SOCKERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return (int32_t)len;
|
||||
}
|
||||
|
||||
int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen) {
|
||||
uint8_t mr;
|
||||
uint8_t head[8];
|
||||
uint16_t pack_len = 0;
|
||||
|
||||
CHECK_SOCKNUM();
|
||||
CHECK_SOCKDATA();
|
||||
|
||||
switch ((mr = getSn_MR(sn)) & 0x0F) {
|
||||
case Sn_MR_UDP:
|
||||
case Sn_MR_IPRAW:
|
||||
case Sn_MR_IPRAW6:
|
||||
case Sn_MR_MACRAW:
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_SOCKMODE;
|
||||
}
|
||||
|
||||
if (sock_remained_size[sn] == 0) {
|
||||
while (1) {
|
||||
pack_len = getSn_RX_RSR(sn);
|
||||
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
||||
if (pack_len != 0) {
|
||||
sock_pack_info[sn] = PACK_NONE;
|
||||
break;
|
||||
}
|
||||
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
||||
};
|
||||
}
|
||||
|
||||
wiz_recv_data(sn, head, 2);
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
pack_len = head[0] & 0x07;
|
||||
pack_len = (pack_len << 8) + head[1];
|
||||
|
||||
switch (mr & 0x07) {
|
||||
case Sn_MR_UDP4:
|
||||
case Sn_MR_UDP6:
|
||||
case Sn_MR_UDPD:
|
||||
if (addr == 0) return SOCKERR_ARG;
|
||||
sock_pack_info[sn] = head[0] & 0xF8;
|
||||
if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16;
|
||||
else *addrlen = 4;
|
||||
wiz_recv_data(sn, addr, *addrlen);
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
break;
|
||||
case Sn_MR_MACRAW:
|
||||
if (sock_remained_size[sn] == 0) {
|
||||
sock_remained_size[sn] = head[0];
|
||||
sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[1] - 2;
|
||||
if (sock_remained_size[sn] > 1514) {
|
||||
close(sn);
|
||||
return SOCKFATAL_PACKLEN;
|
||||
}
|
||||
sock_pack_info[sn] = PACK_FIRST;
|
||||
}
|
||||
if (len < sock_remained_size[sn]) pack_len = len;
|
||||
else pack_len = sock_remained_size[sn];
|
||||
wiz_recv_data(sn, buf, pack_len);
|
||||
break;
|
||||
case Sn_MR_IPRAW6:
|
||||
case Sn_MR_IPRAW4:
|
||||
if (sock_remained_size[sn] == 0) {
|
||||
if (*addr == 0) return SOCKERR_ARG;
|
||||
sock_pack_info[sn] = head[0] & 0xF8;
|
||||
if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16;
|
||||
else *addrlen = 4;
|
||||
wiz_recv_data(sn, addr, *addrlen);
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
wiz_recv_ignore(sn, pack_len);
|
||||
sock_remained_size[sn] = pack_len;
|
||||
break;
|
||||
}
|
||||
|
||||
sock_remained_size[sn] = pack_len;
|
||||
sock_pack_info[sn] |= PACK_FIRST;
|
||||
if ((getSn_MR(sn) & 0x03) == 0x02) {
|
||||
if (port == 0) return SOCKERR_ARG;
|
||||
wiz_recv_data(sn, head, 2);
|
||||
*port = (((uint16_t)head[0]) << 8) + head[1];
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
}
|
||||
|
||||
if (len < sock_remained_size[sn]) pack_len = len;
|
||||
else pack_len = sock_remained_size[sn];
|
||||
wiz_recv_data(sn, buf, pack_len);
|
||||
setSn_CR(sn, Sn_CR_RECV);
|
||||
while (getSn_CR(sn));
|
||||
|
||||
sock_remained_size[sn] -= pack_len;
|
||||
if (sock_remained_size[sn] != 0) sock_pack_info[sn] |= PACK_REMAINED;
|
||||
else sock_pack_info[sn] |= PACK_COMPLETED;
|
||||
|
||||
return (int32_t)pack_len;
|
||||
}
|
||||
|
||||
int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg) {
|
||||
uint8_t tmp = 0;
|
||||
CHECK_SOCKNUM();
|
||||
tmp = *((uint8_t*)arg);
|
||||
switch (cstype) {
|
||||
case CS_SET_IOMODE:
|
||||
if (tmp == SOCK_IO_NONBLOCK) sock_io_mode |= (1 << sn);
|
||||
else if (tmp == SOCK_IO_BLOCK) sock_io_mode &= ~(1 << sn);
|
||||
else return SOCKERR_ARG;
|
||||
break;
|
||||
case CS_GET_IOMODE:
|
||||
*((uint8_t*)arg) = (uint8_t)((sock_io_mode >> sn) & 0x0001);
|
||||
break;
|
||||
case CS_GET_MAXTXBUF:
|
||||
*((uint16_t*)arg) = getSn_TxMAX(sn);
|
||||
break;
|
||||
case CS_GET_MAXRXBUF:
|
||||
*((uint16_t*)arg) = getSn_RxMAX(sn);
|
||||
break;
|
||||
case CS_CLR_INTERRUPT:
|
||||
if (tmp > SIK_ALL) return SOCKERR_ARG;
|
||||
setSn_IR(sn, tmp);
|
||||
break;
|
||||
case CS_GET_INTERRUPT:
|
||||
*((uint8_t*)arg) = getSn_IR(sn);
|
||||
break;
|
||||
case CS_SET_INTMASK:
|
||||
if (tmp > SIK_ALL) return SOCKERR_ARG;
|
||||
setSn_IMR(sn, tmp);
|
||||
break;
|
||||
case CS_GET_INTMASK:
|
||||
*((uint8_t*)arg) = getSn_IMR(sn);
|
||||
break;
|
||||
case CS_SET_PREFER:
|
||||
if ((tmp & 0x03) == 0x01) return SOCKERR_ARG;
|
||||
setSn_PSR(sn, tmp);
|
||||
break;
|
||||
case CS_GET_PREFER:
|
||||
*(uint8_t*)arg = getSn_PSR(sn);
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_ARG;
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg) {
|
||||
CHECK_SOCKNUM();
|
||||
switch (sotype) {
|
||||
case SO_TTL:
|
||||
setSn_TTL(sn, *(uint8_t*)arg);
|
||||
break;
|
||||
case SO_TOS:
|
||||
setSn_TOS(sn, *(uint8_t*)arg);
|
||||
break;
|
||||
case SO_MSS:
|
||||
setSn_MSSR(sn, *(uint16_t*)arg);
|
||||
break;
|
||||
case SO_DESTIP:
|
||||
if (((wiz_IPAddress *)arg)->len == 16) setSn_DIP6R(sn, ((wiz_IPAddress*)arg)->ip);
|
||||
else setSn_DIPR(sn, (uint8_t*)arg);
|
||||
break;
|
||||
case SO_DESTPORT:
|
||||
setSn_DPORTR(sn, *(uint16_t*)arg);
|
||||
break;
|
||||
case SO_KEEPALIVESEND:
|
||||
CHECK_TCPMODE();
|
||||
if (getSn_KPALVTR(sn) != 0) return SOCKERR_SOCKOPT;
|
||||
setSn_CR(sn, Sn_CR_SEND_KEEP);
|
||||
while (getSn_CR(sn) != 0) {
|
||||
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
||||
setSn_IR(sn, Sn_IR_TIMEOUT);
|
||||
return SOCKERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case SO_KEEPALIVEAUTO:
|
||||
CHECK_TCPMODE();
|
||||
setSn_KPALVTR(sn, *(uint8_t*)arg);
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_ARG;
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg) {
|
||||
CHECK_SOCKNUM();
|
||||
switch (sotype) {
|
||||
case SO_FLAG:
|
||||
*(uint8_t*)arg = (getSn_MR(sn) & 0xF0) | (getSn_MR2(sn)) | ((uint8_t)(((sock_io_mode >> sn) & 0x0001) << 3));
|
||||
break;
|
||||
case SO_TTL:
|
||||
*(uint8_t*)arg = getSn_TTL(sn);
|
||||
break;
|
||||
case SO_TOS:
|
||||
*(uint8_t*)arg = getSn_TOS(sn);
|
||||
break;
|
||||
case SO_MSS:
|
||||
*(uint16_t*)arg = getSn_MSSR(sn);
|
||||
break;
|
||||
case SO_DESTIP:
|
||||
CHECK_TCPMODE();
|
||||
if (getSn_ESR(sn) & TCPSOCK_MODE) {
|
||||
getSn_DIP6R(sn, ((wiz_IPAddress*)arg)->ip);
|
||||
((wiz_IPAddress*)arg)->len = 16;
|
||||
} else {
|
||||
getSn_DIPR(sn, ((wiz_IPAddress*)arg)->ip);
|
||||
((wiz_IPAddress*)arg)->len = 4;
|
||||
}
|
||||
break;
|
||||
case SO_DESTPORT:
|
||||
*(uint16_t*)arg = getSn_DPORTR(sn);
|
||||
break;
|
||||
case SO_KEEPALIVEAUTO:
|
||||
CHECK_TCPMODE();
|
||||
*(uint16_t*)arg = getSn_KPALVTR(sn);
|
||||
break;
|
||||
case SO_SENDBUF:
|
||||
*(uint16_t*)arg = getSn_TX_FSR(sn);
|
||||
break;
|
||||
case SO_RECVBUF:
|
||||
*(uint16_t*)arg = getSn_RX_RSR(sn);
|
||||
break;
|
||||
case SO_STATUS:
|
||||
*(uint8_t*)arg = getSn_SR(sn);
|
||||
break;
|
||||
case SO_EXTSTATUS:
|
||||
CHECK_TCPMODE();
|
||||
*(uint8_t*)arg = getSn_ESR(sn) & 0x07;
|
||||
break;
|
||||
case SO_REMAINSIZE:
|
||||
if (getSn_MR(sn) == SOCK_CLOSED) return SOCKERR_SOCKSTATUS;
|
||||
if (getSn_MR(sn) & 0x01) *(uint16_t*)arg = getSn_RX_RSR(sn);
|
||||
else *(uint16_t*)arg = sock_remained_size[sn];
|
||||
break;
|
||||
case SO_PACKINFO:
|
||||
if (getSn_MR(sn) == SOCK_CLOSED) return SOCKERR_SOCKSTATUS;
|
||||
if (getSn_MR(sn) & 0x01) return SOCKERR_SOCKMODE;
|
||||
else *(uint8_t*)arg = sock_pack_info[sn];
|
||||
break;
|
||||
case SO_MODE:
|
||||
*(uint8_t*)arg = 0x0F & getSn_MR(sn);
|
||||
break;
|
||||
default:
|
||||
return SOCKERR_SOCKOPT;
|
||||
}
|
||||
return SOCK_OK;
|
||||
}
|
||||
|
||||
int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize) {
|
||||
uint32_t rx_ptr = 0;
|
||||
uint16_t i = 0, sub_idx = 0;
|
||||
if ((getSn_RX_RSR(sn) > 0) && (subsize > 0)) {
|
||||
rx_ptr = ((uint32_t)getSn_RX_RD(sn) << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
||||
sub_idx = 0;
|
||||
for (i = 0; i < getSn_RX_RSR(sn); i++) {
|
||||
if (WIZCHIP_READ(rx_ptr) == submsg[sub_idx]) {
|
||||
sub_idx++;
|
||||
if (sub_idx == subsize) return (i + 1 - sub_idx);
|
||||
} else {
|
||||
sub_idx = 0;
|
||||
}
|
||||
rx_ptr = WIZCHIP_OFFSET_INC(rx_ptr, 1);
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
+130
@@ -0,0 +1,130 @@
|
||||
#ifndef _SOCKET_H_
|
||||
#define _SOCKET_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
#define SOCKET uint8_t
|
||||
|
||||
#define SOCK_OK 1
|
||||
#define SOCK_BUSY 0
|
||||
#define SOCK_FATAL -1000
|
||||
|
||||
#define SOCK_ERROR 0
|
||||
#define SOCKERR_SOCKNUM (SOCK_ERROR - 1)
|
||||
#define SOCKERR_SOCKOPT (SOCK_ERROR - 2)
|
||||
#define SOCKERR_SOCKINIT (SOCK_ERROR - 3)
|
||||
#define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4)
|
||||
#define SOCKERR_SOCKMODE (SOCK_ERROR - 5)
|
||||
#define SOCKERR_SOCKFLAG (SOCK_ERROR - 6)
|
||||
#define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7)
|
||||
#define SOCKERR_ARG (SOCK_ERROR - 10)
|
||||
#define SOCKERR_PORTZERO (SOCK_ERROR - 11)
|
||||
#define SOCKERR_IPINVALID (SOCK_ERROR - 12)
|
||||
#define SOCKERR_TIMEOUT (SOCK_ERROR - 13)
|
||||
#define SOCKERR_DATALEN (SOCK_ERROR - 14)
|
||||
#define SOCKERR_BUFFER (SOCK_ERROR - 15)
|
||||
|
||||
#define SOCKFATAL_PACKLEN (SOCK_FATAL - 1)
|
||||
|
||||
#define SF_MULTI_ENABLE (Sn_MR_MULTI)
|
||||
#define SF_ETHER_OWN (Sn_MR_MF)
|
||||
#define SF_BROAD_BLOCK (Sn_MR_BRDB)
|
||||
#define SF_TCP_FPSH (Sn_MR_FPSH)
|
||||
#define SF_TCP_NODELAY (Sn_MR_ND)
|
||||
#define SF_IGMP_VER2 (Sn_MR_MC)
|
||||
#define SF_SOLICIT_BLOCK (Sn_MR_SMB)
|
||||
#define SF_ETHER_MULTI4B (Sn_MR_MMB4)
|
||||
#define SF_UNI_BLOCK (Sn_MR_UNIB)
|
||||
#define SF_ETHER_MULIT6B (Sn_MR_MMB6)
|
||||
#define SF_FORCE_ARP (Sn_MR2_FARP)
|
||||
#define SF_DHA_MANUAL (Sn_MR2_DHAM)
|
||||
#define SF_IO_NONBLOCK (0x01 << 3)
|
||||
|
||||
#define PACK_IPv6 (1<<7)
|
||||
#define PACK_IPV6_ALLNODE (PACK_IPv6 | (1<<6))
|
||||
#define PACK_IPV6_MULTI (PACK_IPv6 | (1<<5))
|
||||
#define PACK_IPV6_LLA (PACK_IPv6 | (1<<4))
|
||||
#define PACK_COMPLETED (1<<3)
|
||||
#define PACK_REMAINED (1<<2)
|
||||
#define PACK_FIRST (1<<1)
|
||||
#define PACK_NONE (0x00)
|
||||
|
||||
#define SRCV6_PREFER_AUTO (PSR_AUTO)
|
||||
#define SRCV6_PREFER_LLA (PSR_LLA)
|
||||
#define SRCV6_PREFER_GUA (PSR_GUA)
|
||||
|
||||
#define TCPSOCK_MODE (Sn_ESR_TCPM)
|
||||
#define TCPSOCK_OP (Sn_ESR_TCPOP)
|
||||
#define TCPSOCK_SIP (Sn_ESR_IP6T)
|
||||
|
||||
#define SOCK_IO_BLOCK 0
|
||||
#define SOCK_IO_NONBLOCK 1
|
||||
|
||||
int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag);
|
||||
int8_t close(uint8_t sn);
|
||||
int8_t listen(uint8_t sn);
|
||||
int8_t disconnect(uint8_t sn);
|
||||
int32_t send(uint8_t sn, uint8_t * buf, uint16_t len);
|
||||
int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len);
|
||||
|
||||
typedef enum {
|
||||
SIK_CONNECTED = (1 << 0),
|
||||
SIK_DISCONNECTED = (1 << 1),
|
||||
SIK_RECEIVED = (1 << 2),
|
||||
SIK_TIMEOUT = (1 << 3),
|
||||
SIK_SENT = (1 << 4),
|
||||
SIK_ALL = 0x1F
|
||||
} sockint_kind;
|
||||
|
||||
typedef enum {
|
||||
CS_SET_IOMODE,
|
||||
CS_GET_IOMODE,
|
||||
CS_GET_MAXTXBUF,
|
||||
CS_GET_MAXRXBUF,
|
||||
CS_CLR_INTERRUPT,
|
||||
CS_GET_INTERRUPT,
|
||||
CS_SET_PREFER,
|
||||
CS_GET_PREFER,
|
||||
CS_SET_INTMASK,
|
||||
CS_GET_INTMASK
|
||||
} ctlsock_type;
|
||||
|
||||
typedef enum {
|
||||
SO_FLAG,
|
||||
SO_TTL,
|
||||
SO_TOS,
|
||||
SO_MSS,
|
||||
SO_DESTIP,
|
||||
SO_DESTPORT,
|
||||
SO_KEEPALIVESEND,
|
||||
SO_KEEPALIVEAUTO,
|
||||
SO_SENDBUF,
|
||||
SO_RECVBUF,
|
||||
SO_STATUS,
|
||||
SO_EXTSTATUS,
|
||||
SO_MODE,
|
||||
SO_REMAINSIZE,
|
||||
SO_PACKINFO
|
||||
} sockopt_type;
|
||||
|
||||
int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg);
|
||||
int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg);
|
||||
int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg);
|
||||
int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize);
|
||||
|
||||
int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen);
|
||||
int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen);
|
||||
|
||||
#define connect(sn, addr, port, addrlen) connect_W6x00(sn, addr, port, addrlen)
|
||||
#define sendto(sn, buf, len, addr, port, addrlen) sendto_W6x00(sn, buf, len, addr, port, addrlen)
|
||||
#define recvfrom(sn, buf, len, addr, port, addrlen) recvfrom_W6x00(sn, buf, len, addr, port, addrlen)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,67 +1,10 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \file W6300.c
|
||||
//! \brief W6300 HAL Implements file.
|
||||
//! \version 1.0.0
|
||||
//! \date 2019/01/01
|
||||
//! \par Revision history
|
||||
//! <2019/01/01> 1st Release
|
||||
//! \author MidnightCow
|
||||
//! \copyright
|
||||
//!
|
||||
//! Copyright (c) 2019, WIZnet Co., LTD.
|
||||
//!
|
||||
//! Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
//! of this software and associated documentation files (the "Software"), to deal
|
||||
//! in the Software without restriction, including without limitation the rights
|
||||
//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
//! copies of the Software, and to permit persons to whom the Software is
|
||||
//! furnished to do so, subject to the following conditions:
|
||||
//!
|
||||
//! The above copyright notice and this permission notice shall be included in
|
||||
//! all copies or substantial portions of the Software.
|
||||
//!
|
||||
//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
//! SOFTWARE.
|
||||
//!
|
||||
//*****************************************************************************
|
||||
|
||||
#include "w6300.h"
|
||||
|
||||
|
||||
#if 0
|
||||
#define _WIZCHIP_SPI_VDM_OP_ 0x00
|
||||
#define _WIZCHIP_SPI_FDM_LEN1_ 0x01
|
||||
#define _WIZCHIP_SPI_FDM_LEN2_ 0x02
|
||||
#define _WIZCHIP_SPI_FDM_LEN4_ 0x03
|
||||
#endif
|
||||
//
|
||||
// If you want to use SPI FDM mode, Feel free contact to WIZnet.
|
||||
// http://forum.wiznet.io
|
||||
//
|
||||
|
||||
#if _WIZCHIP_ == 6300
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#define _W6300_SPI_OP_ _WIZCHIP_SPI_VDM_OP_
|
||||
#define _W6300_SPI_READ_ (0x00 << 5) ///< SPI interface Read operation in Control Phase
|
||||
#define _W6300_SPI_WRITE_ (0x01 << 5) ///< SPI interface Write operation in Control Phase
|
||||
|
||||
//////////////////////////////////////////////////
|
||||
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
|
||||
|
||||
uint8_t opcode = 0;
|
||||
uint16_t ADDR = 0;
|
||||
|
||||
WIZCHIP_CRITICAL_ENTER();
|
||||
WIZCHIP.CS._select();
|
||||
|
||||
#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
|
||||
uint8_t tAD[4];
|
||||
tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
|
||||
@@ -69,25 +12,21 @@ void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
|
||||
tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
|
||||
tAD[3] = wb;
|
||||
WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 4, 1);
|
||||
#else //w6300 QSPI MODE
|
||||
#else
|
||||
opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
|
||||
ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
|
||||
WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, &wb, 1);
|
||||
#endif
|
||||
|
||||
WIZCHIP.CS._deselect();
|
||||
WIZCHIP_CRITICAL_EXIT();
|
||||
}
|
||||
|
||||
uint8_t WIZCHIP_READ(uint32_t AddrSel) {
|
||||
//uint8_t ret;
|
||||
uint8_t WIZCHIP_READ(uint32_t AddrSel) {
|
||||
uint8_t ret[2] = {0,};
|
||||
uint8_t opcode = 0;
|
||||
uint16_t ADDR = 0;
|
||||
|
||||
WIZCHIP_CRITICAL_ENTER();
|
||||
WIZCHIP.CS._select();
|
||||
|
||||
#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
|
||||
uint8_t tAD[3];
|
||||
tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
|
||||
@@ -105,15 +44,11 @@ uint8_t WIZCHIP_READ(uint32_t AddrSel) {
|
||||
return ret[0];
|
||||
}
|
||||
|
||||
|
||||
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
||||
|
||||
uint8_t opcode = 0;
|
||||
uint16_t ADDR = 0;
|
||||
|
||||
WIZCHIP_CRITICAL_ENTER();
|
||||
WIZCHIP.CS._select();
|
||||
|
||||
#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
|
||||
uint8_t tAD[3];
|
||||
tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
|
||||
@@ -124,22 +59,17 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
||||
#else
|
||||
opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
|
||||
ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
|
||||
WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, pBuf, len);//by_lihan
|
||||
//qspi_write_buf(opcode, ADDR, pBuf, len);
|
||||
WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, pBuf, len);
|
||||
WIZCHIP.CS._deselect();
|
||||
WIZCHIP_CRITICAL_EXIT();
|
||||
#endif
|
||||
}
|
||||
|
||||
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
||||
|
||||
uint8_t ret;
|
||||
uint8_t opcode = 0;
|
||||
uint16_t ADDR = 0;
|
||||
|
||||
WIZCHIP_CRITICAL_ENTER();
|
||||
WIZCHIP.CS._select();
|
||||
|
||||
#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
|
||||
uint8_t tAD[3];
|
||||
tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
|
||||
@@ -150,8 +80,7 @@ void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
||||
#else
|
||||
opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_READ_) | (_WIZCHIP_QSPI_MODE_));
|
||||
ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
|
||||
WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, pBuf, len);//by_lihan
|
||||
//qspi_read_buf(opcode, ADDR, pBuf, len);
|
||||
WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, pBuf, len);
|
||||
WIZCHIP.CS._deselect();
|
||||
WIZCHIP_CRITICAL_EXIT();
|
||||
#endif
|
||||
@@ -178,96 +107,45 @@ uint16_t getSn_RX_RSR(uint8_t sn) {
|
||||
}
|
||||
|
||||
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
|
||||
uint16_t ptr = 0;
|
||||
uint32_t addrsel = 0;
|
||||
ptr = getSn_TX_WR(sn);
|
||||
addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
|
||||
uint16_t ptr = getSn_TX_WR(sn);
|
||||
uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
|
||||
WIZCHIP_WRITE_BUF(addrsel, wizdata, len);
|
||||
ptr += len;
|
||||
setSn_TX_WR(sn, ptr);
|
||||
}
|
||||
|
||||
#if 0
|
||||
#define ETHERNET_BUF_MAX_SIZE_TEMP (1024 * 32 )
|
||||
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
|
||||
uint16_t ptr = 0;
|
||||
uint32_t addrsel = 0;
|
||||
if (len == 0) {
|
||||
return;
|
||||
}
|
||||
ptr = getSn_RX_RD(sn);
|
||||
|
||||
if (ptr + len > 0xFFFF) {
|
||||
addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
||||
uint16_t size = 0xFFFF - ptr;
|
||||
WIZCHIP_READ_BUF(addrsel, wizdata, size);
|
||||
wizdata += size;
|
||||
size = len - size;
|
||||
addrsel = WIZCHIP_RXBUF_BLOCK(sn);
|
||||
WIZCHIP_READ_BUF(addrsel, wizdata, size);
|
||||
} else {
|
||||
addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
||||
WIZCHIP_READ_BUF(addrsel, wizdata, len);
|
||||
}
|
||||
|
||||
ptr += len;
|
||||
ptr %= 0xFFFF ;
|
||||
|
||||
setSn_RX_RD(sn, ptr);
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
|
||||
uint16_t ptr = 0;
|
||||
uint32_t addrsel = 0;
|
||||
if (len == 0) {
|
||||
return;
|
||||
}
|
||||
ptr = getSn_RX_RD(sn);
|
||||
addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
||||
if (len == 0) return;
|
||||
uint16_t ptr = getSn_RX_RD(sn);
|
||||
uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
||||
WIZCHIP_READ_BUF(addrsel, wizdata, len);
|
||||
ptr += len;
|
||||
setSn_RX_RD(sn, ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
void wiz_recv_ignore(uint8_t sn, uint16_t len) {
|
||||
setSn_RX_RD(sn, getSn_RX_RD(sn) + len);
|
||||
}
|
||||
|
||||
#if 1
|
||||
// 20231019 taylor
|
||||
void wiz_delay_ms(uint32_t milliseconds) {
|
||||
uint32_t i;
|
||||
for (i = 0 ; i < milliseconds ; i++) {
|
||||
//Write any values to clear the TCNTCLKR register
|
||||
for (uint32_t i = 0; i < milliseconds; i++) {
|
||||
setTCNTRCLR(0xff);
|
||||
|
||||
// Wait until counter register value reaches 10.(10 = 1ms : TCNTR is 100us tick counter register)
|
||||
while (getTCNTR() < 0x0a) {}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/// @cond DOXY_APPLY_CODE
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
/// @endcond
|
||||
void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
|
||||
setPHYRAR(phyregaddr);
|
||||
setPHYDIR(var);
|
||||
setPHYACR(PHYACR_WRITE);
|
||||
while (getPHYACR()); //wait for command complete
|
||||
while (getPHYACR());
|
||||
}
|
||||
|
||||
uint16_t wiz_mdio_read(uint8_t phyregaddr) {
|
||||
setPHYRAR(phyregaddr);
|
||||
setPHYACR(PHYACR_READ);
|
||||
while (getPHYACR()); //wait for command complete
|
||||
while (getPHYACR());
|
||||
return getPHYDOR();
|
||||
}
|
||||
/// @cond DOXY_APPLY_CODE
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
+929
@@ -0,0 +1,929 @@
|
||||
#ifndef _W6300_H_
|
||||
#define _W6300_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define _W6300_SPI_READ_ (0x00 << 5) ///< SPI interface Read operation in Control Phase
|
||||
#define _W6300_SPI_WRITE_ (0x01 << 5) ///< SPI interface Write operation in Control Phase
|
||||
|
||||
#define WIZCHIP_CREG_BLOCK (0x00 ) ///< Common register block
|
||||
#define WIZCHIP_SREG_BLOCK(N) ((1+4*N)) ///< SOCKETn register block
|
||||
#define WIZCHIP_TXBUF_BLOCK(N) ((2+4*N)) ///< SOCKETn Tx buffer address block
|
||||
#define WIZCHIP_RXBUF_BLOCK(N) ((3+4*N)) ///< SOCKETn Rx buffer address block
|
||||
|
||||
#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) ///< Increase offset address
|
||||
|
||||
#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
|
||||
#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
|
||||
#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
|
||||
#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
|
||||
#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
|
||||
#define _W6300_IO_BASE_ _WIZCHIP_IO_BASE_
|
||||
#elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
|
||||
#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
|
||||
#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
|
||||
#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
|
||||
#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
|
||||
#define _W6300_IO_BASE_ 0x00000000
|
||||
#define _W6100_IO_BASE_ 0x00000000
|
||||
#endif
|
||||
|
||||
|
||||
#define _CIDR_ (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RTL_ (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _VER_ (_W6300_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SYSR_ (_W6300_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SYCR0_ (_W6300_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
|
||||
#define _SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1))
|
||||
#define _TCNTR_ (_W6300_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _TCNTRCLR_ (_W6300_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IR_ (_W6300_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIR_ (_W6300_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIR_ (_W6300_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IMR_ (_W6300_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IRCLR_ (_W6300_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIMR_ (_W6300_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIMR_ (_W6300_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIRCLR_ (_W6300_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLPSR_ (_W6300_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLCR_ (_W6300_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYSR_ (_W6300_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYRAR_ (_W6300_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIR_ (_W6300_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDOR_ (_W6300_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYACR_ (_W6300_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIVR_ (_W6300_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYCR0_ (_W6300_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1)
|
||||
#define _NET4MR_ (_W6300_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NET6MR_ (_W6300_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR_ (_W6300_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR2_ (_W6300_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PTMR_ (_W6300_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMNR_ (_W6300_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHAR_ (_W6300_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PSIDR_ (_W6300_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMRUR_ (_W6300_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SHAR_ (_W6300_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GAR_ (_W6300_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GA4R_ (_GAR_)
|
||||
#define _SUBR_ (_W6300_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUB4R_ (_SUBR_)
|
||||
|
||||
#define _SIPR_ (_W6300_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIP4R_ (_SIPR_)
|
||||
#define _LLAR_ (_W6300_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GUAR_ (_W6300_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUB6R_ (_W6300_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GA6R_ (_W6300_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIP6R_ (_W6300_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIPR_ (_W6300_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIP4R_ (_SLDIPR_)
|
||||
#define _SLDHAR_ (_W6300_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGIDR_ (_W6300_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGSEQR_ (_W6300_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIPR_ (_W6300_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIP4R_ (_UIPR_)
|
||||
#define _UPORTR_ (_W6300_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORT4R_ (_UPORTR_)
|
||||
#define _UIP6R_ (_W6300_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORT6R_ (_W6300_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _INTPTMR_ (_W6300_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLR_ (_W6300_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PFR_ (_W6300_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _VLTR_ (_W6300_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLTR_ (_W6300_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PAR_ (_W6300_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _ICMP6BLKR_ (_W6300_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _CHPLCKR_ (_W6300_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETLCKR_ (_W6300_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYLCKR_ (_W6300_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RTR_ (_W6300_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RCR_ (_W6300_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRTR_ (_W6300_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRCR_ (_W6300_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLHOPR_ (_W6300_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)
|
||||
|
||||
#define _Sn_MR_(N) (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PSR_(N) (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_CR_(N) (_W6300_IO_BASE_ + (0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IR_(N) (_W6300_IO_BASE_ + (0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IMR_(N) (_W6300_IO_BASE_ + (0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IRCLR_(N) (_W6300_IO_BASE_ + (0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
|
||||
|
||||
|
||||
#define _Sn_SR_(N) (_W6300_IO_BASE_ + (0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_ESR_(N) (_W6300_IO_BASE_ + (0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PNR_(N) (_W6300_IO_BASE_ + (0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_NHR_(N) (_Sn_PNR_(N))
|
||||
#define _Sn_TOSR_(N) (_W6300_IO_BASE_ + (0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TTLR_(N) (_W6300_IO_BASE_ + (0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_HOPR_(N) (_Sn_TTLR_(N))
|
||||
#define _Sn_FRGR_(N) (_W6300_IO_BASE_ + (0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MSSR_(N) (_W6300_IO_BASE_ + (0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PORTR_(N) (_W6300_IO_BASE_ + (0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DHAR_(N) (_W6300_IO_BASE_ + (0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIPR_(N) (_W6300_IO_BASE_ + (0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIP4R_(N) (_Sn_DIPR_(N))
|
||||
#define _Sn_DIP6R_(N) (_W6300_IO_BASE_ + (0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DPORTR_(N) (_W6300_IO_BASE_ + (0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MR2_(N) (_W6300_IO_BASE_ + (0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RTR_(N) (_W6300_IO_BASE_ + (0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RCR_(N) (_W6300_IO_BASE_ + (0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_KPALVTR_(N) (_W6300_IO_BASE_ + (0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_BSR_(N) (_W6300_IO_BASE_ + (0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_FSR_(N) (_W6300_IO_BASE_ + (0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_RD_(N) (_W6300_IO_BASE_ + (0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_WR_(N) (_W6300_IO_BASE_ + (0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_BSR_(N) (_W6300_IO_BASE_ + (0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RSR_(N) (_W6300_IO_BASE_ + (0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RD_(N) (_W6300_IO_BASE_ + (0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_WR_(N) (_W6300_IO_BASE_ + (0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
|
||||
#define SYSR_CHPL (1 << 7)
|
||||
#define SYSR_NETL (1 << 6)
|
||||
#define SYSR_PHYL (1 << 5)
|
||||
|
||||
#define SYSR_IND (1 << 5)
|
||||
#define SYSR_SPI (1 << 0)
|
||||
#define SYCR0_RST (0x00)
|
||||
#define SYCR1_IEN (1 << 7)
|
||||
#define SYCR1_CLKSEL (1 << 0)
|
||||
#define SYCR1_CLKSEL_25M 1
|
||||
#define SYCR1_CLKSEL_100M 0
|
||||
#define IR_WOL (1<<7)
|
||||
#define IR_UNR6 (1<<4)
|
||||
#define IR_IPCONF (1<<2)
|
||||
#define IR_UNR4 (1<<1)
|
||||
#define IR_PTERM (1<<0)
|
||||
#define SIR_INT(N) (1<<N)
|
||||
#define SLIR_TOUT (1<<7)
|
||||
#define SLIR_ARP4 (1<<6)
|
||||
#define SLIR_PING4 (1<<5)
|
||||
#define SLIR_ARP6 (1<<4)
|
||||
#define SLIR_PING6 (1<<3)
|
||||
#define SLIR_NS (1<<2)
|
||||
#define SLIR_RS (1<<1)
|
||||
#define SLIR_RA (1<<0)
|
||||
#define PSR_AUTO (0x00)
|
||||
#define PSR_LLA (0x02)
|
||||
#define PSR_GUA (0x03)
|
||||
#define SLCR_ARP4 (1<<6)
|
||||
#define SLCR_PING4 (1<<5)
|
||||
#define SLCR_ARP6 (1<<4)
|
||||
#define SLCR_PING6 (1<<3)
|
||||
#define SLCR_NS (1<<2)
|
||||
#define SLCR_RS (1<<1)
|
||||
#define SLCR_UNA (1<<0)
|
||||
#define PHYSR_CAB (1<<7)
|
||||
#define PHYSR_CAB_OFF (1<<7)
|
||||
#define PHYSR_CAB_ON (0<<7)
|
||||
#define PHYSR_MODE (7<<3)
|
||||
#define PHYSR_MODE_AUTO (0<<3)
|
||||
|
||||
#define PHYSR_MODE_100F (4<<3)
|
||||
#define PHYSR_MODE_100H (5<<3)
|
||||
#define PHYSR_MODE_10F (6<<3)
|
||||
#define PHYSR_MODE_10H (7<<3)
|
||||
#define PHYSR_DPX (1<<2)
|
||||
#define PHYSR_DPX_HALF (1<<2)
|
||||
#define PHYSR_DPX_FULL (0<<2)
|
||||
#define PHYSR_SPD (1<<1)
|
||||
#define PHYSR_SPD_10M (1<<1)
|
||||
#define PHYSR_SPD_100M (0<<1)
|
||||
#define PHYSR_LNK (1<<0)
|
||||
#define PHYSR_LNK_UP (1<<0)
|
||||
#define PHYSR_LNK_DOWN (0<<0)
|
||||
#define PHYACR_READ (0x02)
|
||||
#define PHYACR_WRITE (0x01)
|
||||
#define PHYDIVR_32 (0x00)
|
||||
#define PHYDIVR_64 (0x01)
|
||||
#define PHYDIVR_128 (0xFF)
|
||||
#define PHYCR0_AUTO (0x00)
|
||||
#define PHYCR0_100F (0x04)
|
||||
#define PHYCR0_100H (0x05)
|
||||
#define PHYCR0_10F (0x06)
|
||||
#define PHYCR0_10H (0x07)
|
||||
#define PHYCR1_PWDN (1<<5)
|
||||
#define PHYCR1_TE (1<<3)
|
||||
#define PHYCR1_RST (1<<0)
|
||||
#define NETxMR_UNRB (1<<3)
|
||||
#define NETxMR_PARP (1<<2)
|
||||
#define NETxMR_RSTB (1<<1)
|
||||
#define NETxMR_PB (1<<0)
|
||||
#define NETMR_ANB (1<<5)
|
||||
#define NETMR_M6B (1<<4)
|
||||
#define NETMR_WOL (1<<2)
|
||||
#define NETMR_IP6B (1<<1)
|
||||
#define NETMR_IP4B (1<<0)
|
||||
#define NETMR2_DHAS (1<<7)
|
||||
#define NETMR2_DHAS_ARP (1<<7)
|
||||
#define NETMR2_DHAS_ETH (0<<7)
|
||||
#define NETMR2_PPPoE (1<<0)
|
||||
#define ICMP6BLKR_PING6 (1<<4)
|
||||
#define ICMP6BLKR_MLD (1<<3)
|
||||
#define ICMP6BLKR_RA (1<<2)
|
||||
#define ICMP6BLKR_NA (1<<1)
|
||||
#define ICMP6BLKR_NS (1<<0)
|
||||
#define Sn_MR_MULTI (1<<7)
|
||||
#define Sn_MR_MF (1<<7)
|
||||
#define Sn_MR_BRDB (1<<6)
|
||||
#define Sn_MR_FPSH (1<<6)
|
||||
#define Sn_MR_ND (1<<5)
|
||||
#define Sn_MR_MC (1<<5)
|
||||
#define Sn_MR_SMB (1<<5)
|
||||
#define Sn_MR_MMB (1<<5)
|
||||
#define Sn_MR_MMB4 (Sn_MR_MMB)
|
||||
#define Sn_MR_UNIB (1<<4)
|
||||
#define Sn_MR_MMB6 (1<<4)
|
||||
#define Sn_MR_CLOSE (0x00)
|
||||
#define Sn_MR_TCP (0x01)
|
||||
#define Sn_MR_TCP4 (Sn_MR_TCP)
|
||||
#define Sn_MR_UDP (0x02)
|
||||
#define Sn_MR_UDP4 (Sn_MR_UDP)
|
||||
#define Sn_MR_IPRAW (0x03)
|
||||
#define Sn_MR_IPRAW4 (Sn_MR_IPRAW)
|
||||
#define Sn_MR_MACRAW (0x07)
|
||||
#define Sn_MR_TCP6 (0x09)
|
||||
#define Sn_MR_UDP6 (0x0A)
|
||||
#define Sn_MR_IPRAW6 (0x0B)
|
||||
#define Sn_MR_TCPD (0x0D)
|
||||
#define Sn_MR_UDPD (0x0E)
|
||||
#define Sn_CR_OPEN (0x01)
|
||||
#define Sn_CR_LISTEN (0x02)
|
||||
#define Sn_CR_CONNECT (0x04)
|
||||
#define Sn_CR_CONNECT6 (0x84)
|
||||
#define Sn_CR_DISCON (0x08)
|
||||
#define Sn_CR_CLOSE (0x10)
|
||||
#define Sn_CR_SEND (0x20)
|
||||
#define Sn_CR_SEND6 (0xA0)
|
||||
#define Sn_CR_SEND_KEEP (0x22)
|
||||
#define Sn_CR_RECV (0x40)
|
||||
#define Sn_IR_SENDOK (0x10)
|
||||
#define Sn_IR_TIMEOUT (0x08)
|
||||
#define Sn_IR_RECV (0x04)
|
||||
#define Sn_IR_DISCON (0x02)
|
||||
#define Sn_IR_CON (0x01)
|
||||
#define SOCK_CLOSED (0x00)
|
||||
#define SOCK_INIT (0x13)
|
||||
#define SOCK_LISTEN (0x14)
|
||||
#define SOCK_SYNSENT (0x15)
|
||||
#define SOCK_SYNRECV (0x16)
|
||||
#define SOCK_ESTABLISHED (0x17)
|
||||
#define SOCK_FIN_WAIT (0x18)
|
||||
|
||||
#define SOCK_TIME_WAIT (0x1B)
|
||||
#define SOCK_CLOSE_WAIT (0x1C)
|
||||
#define SOCK_LAST_ACK (0x1D)
|
||||
#define SOCK_UDP (0x22)
|
||||
#define SOCK_IPRAW4 (0x32)
|
||||
#define SOCK_IPRAW (SOCK_IPRAW4)
|
||||
#define SOCK_IPRAW6 (0x33)
|
||||
#define SOCK_MACRAW (0x42)
|
||||
#define Sn_ESR_TCPM (1<<2)
|
||||
#define Sn_ESR_TCPM_IPV4 (0<<2)
|
||||
#define Sn_ESR_TCPM_IPV6 (1<<2)
|
||||
#define Sn_ESR_TCPOP (1<<1)
|
||||
#define Sn_ESR_TCPOP_SVR (0<<1)
|
||||
#define Sn_ESR_TCPOP_CLT (1<<1)
|
||||
#define Sn_ESR_IP6T (1<<0)
|
||||
#define Sn_ESR_IP6T_LLA (0<<0)
|
||||
#define Sn_ESR_IP6T_GUA (1<<0)
|
||||
#define Sn_MR2_DHAM (1<<1)
|
||||
#define Sn_MR2_DHAM_AUTO (0<<1)
|
||||
#define Sn_MR2_DHAM_MANUAL (1<<1)
|
||||
#define Sn_MR2_FARP (1<<0)
|
||||
#define PHYRAR_BMCR (0x00)
|
||||
#define PHYRAR_BMSR (0x01)
|
||||
#define BMCR_RST (1<<15)
|
||||
#define BMCR_LB (1<<14)
|
||||
#define BMCR_SPD (1<<13)
|
||||
#define BMCR_ANE (1<<12)
|
||||
#define BMCR_PWDN (1<<11)
|
||||
#define BMCR_ISOL (1<<10)
|
||||
#define BMCR_REAN (1<<9)
|
||||
#define BMCR_DPX (1<<8)
|
||||
#define BMCR_COLT (1<<7)
|
||||
#define BMSR_100_T4 (1<<15)
|
||||
#define BMSR_100_FDX (1<<14)
|
||||
#define BMSR_100_HDX (1<<13)
|
||||
#define BMSR_10_FDX (1<<12)
|
||||
#define BMSR_10_HDX (1<<11)
|
||||
#define BMSR_MF_SUP (1<<6)
|
||||
#define BMSR_AN_COMP (1<<5)
|
||||
#define BMSR_REMOTE_FAULT (1<<4)
|
||||
#define BMSR_AN_ABILITY (1<<3)
|
||||
#define BMSR_LINK_STATUS (1<<2)
|
||||
#define BMSR_JABBER_DETECT (1<<1)
|
||||
#define BMSR_EXT_CAPA (1<<0)
|
||||
|
||||
|
||||
#define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
|
||||
#define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
|
||||
|
||||
uint8_t WIZCHIP_READ(uint32_t AddrSel);
|
||||
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
|
||||
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
|
||||
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
|
||||
|
||||
#define getRTL() \
|
||||
WIZCHIP_READ(_RTL_)
|
||||
|
||||
#define getCIDR() \
|
||||
((((uint16_t)WIZCHIP_READ(_CIDR_)| (((WIZCHIP_READ(_RTL_))&0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_,1)))
|
||||
|
||||
#define getVER() \
|
||||
((((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_,1)))
|
||||
|
||||
#define getSYSR() \
|
||||
WIZCHIP_READ(_SYSR_)
|
||||
|
||||
#define getSYCR0() \
|
||||
WIZCHIP_READ(_SYCR0_)
|
||||
|
||||
#define setSYCR0(sycr0) \
|
||||
WIZCHIP_WRITE(_SYCR0_, (sycr0))
|
||||
|
||||
#define getSYCR1() \
|
||||
WIZCHIP_READ(_SYCR1_)
|
||||
|
||||
#define setSYCR1(sycr1) \
|
||||
WIZCHIP_WRITE(_SYCR1_, (sycr1))
|
||||
|
||||
#define getTCNTR() \
|
||||
((((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_,1)))
|
||||
|
||||
#define setTCNTRCLR(tcntrclr) \
|
||||
WIZCHIP_WRITE(_TCNTRCLR_,(tcntrclr))
|
||||
|
||||
#define getIR() \
|
||||
WIZCHIP_READ(_IR_)
|
||||
|
||||
#define getSIR() \
|
||||
WIZCHIP_READ(_SIR_)
|
||||
|
||||
#define getSLIR() \
|
||||
WIZCHIP_READ(_SLIR_)
|
||||
|
||||
#define setIMR(imr) \
|
||||
WIZCHIP_WRITE(_IMR_,(imr))
|
||||
|
||||
#define getIMR() \
|
||||
WIZCHIP_READ(_IMR_)
|
||||
|
||||
#define setIRCLR(irclr) \
|
||||
WIZCHIP_WRITE(_IRCLR_,(irclr))
|
||||
#define setIR(ir) setIRCLR(ir)
|
||||
|
||||
#define setSIMR(simr) \
|
||||
WIZCHIP_WRITE(_SIMR_,(simr))
|
||||
|
||||
#define getSIMR() \
|
||||
WIZCHIP_READ(_SIMR_)
|
||||
|
||||
#define setSLIMR(slimr) \
|
||||
WIZCHIP_WRITE(_SLIMR_,(slimr))
|
||||
|
||||
#define getSLIMR() \
|
||||
WIZCHIP_READ(_SLIMR_)
|
||||
|
||||
#define setSLIRCLR(slirclr) \
|
||||
WIZCHIP_WRITE(_SLIRCLR_,(slirclr))
|
||||
#define setSLIR(slir) setSLIRCLR(slir)
|
||||
|
||||
#define setSLPSR(slpsr) \
|
||||
WIZCHIP_WRITE(_SLPSR_,(slpsr))
|
||||
|
||||
#define getSLPSR() \
|
||||
WIZCHIP_READ(_SLPSR_)
|
||||
|
||||
#define setSLCR(slcr) \
|
||||
WIZCHIP_WRITE(_SLCR_,(slcr))
|
||||
|
||||
#define getSLCR() \
|
||||
WIZCHIP_READ(_SLCR_)
|
||||
|
||||
#define getPHYSR() \
|
||||
WIZCHIP_READ(_PHYSR_)
|
||||
|
||||
#define setPHYRAR(phyrar) \
|
||||
WIZCHIP_WRITE(_PHYRAR_,(phyrar))
|
||||
|
||||
#define getPHYRAR() \
|
||||
WIZCHIP_READ(_PHYRAR_)
|
||||
|
||||
#define setPHYDIR(phydir) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_,1), (uint8_t)((phydir)>>8)); \
|
||||
WIZCHIP_WRITE(_PHYDIR_, (uint8_t)(phydir)); \
|
||||
}while(0);
|
||||
|
||||
#define getPHYDOR() \
|
||||
((((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_,1))) << 8) + WIZCHIP_READ(_PHYDOR_))
|
||||
|
||||
#define setPHYACR(phyacr) \
|
||||
WIZCHIP_WRITE(_PHYACR_,(phyacr))
|
||||
|
||||
#define getPHYACR() \
|
||||
WIZCHIP_READ(_PHYACR_)
|
||||
|
||||
#define setPHYDIVR(phydivr) \
|
||||
WIZCHIP_WRITE(_PHYDIVR_,(phydivr))
|
||||
|
||||
#define getPHYDIVR() \
|
||||
WIZCHIP_READ(_PHYDIVR_)
|
||||
|
||||
#define setPHYCR0(phycr0) \
|
||||
WIZCHIP_WRITE(_PHYCR0_,(phycr0))
|
||||
|
||||
#define setPHYCR1(phycr1) \
|
||||
WIZCHIP_WRITE(_PHYCR1_,(phycr1))
|
||||
|
||||
#define getPHYCR1() \
|
||||
WIZCHIP_READ(_PHYCR1_)
|
||||
|
||||
#define setNET4MR(net4mr) \
|
||||
WIZCHIP_WRITE(_NET4MR_,(net4mr))
|
||||
|
||||
#define setNET6MR(net6mr) \
|
||||
WIZCHIP_WRITE(_NET6MR_,(net6mr))
|
||||
|
||||
#define setNETMR(netmr) \
|
||||
WIZCHIP_WRITE(_NETMR_,(netmr))
|
||||
|
||||
#define setNETMR2(netmr2) \
|
||||
WIZCHIP_WRITE(_NETMR2_,(netmr2))
|
||||
|
||||
#define getNET4MR() \
|
||||
WIZCHIP_READ(_NET4MR_)
|
||||
|
||||
#define getNET6MR() \
|
||||
WIZCHIP_READ(_NET6MR_)
|
||||
|
||||
#define getNETMR() \
|
||||
WIZCHIP_READ(_NETMR_)
|
||||
|
||||
#define getNETMR2() \
|
||||
WIZCHIP_READ(_NETMR2_)
|
||||
|
||||
#define setPTMR(ptmr) \
|
||||
WIZCHIP_WRITE(_PTMR_, (ptmr))
|
||||
|
||||
#define getPTMR() \
|
||||
WIZCHIP_READ(_PTMR_)
|
||||
|
||||
#define setPMNR(pmnr) \
|
||||
WIZCHIP_WRITE(_PMNR_, (pmnr))
|
||||
|
||||
#define getPMNR() \
|
||||
WIZCHIP_READ(_PMNR_)
|
||||
|
||||
#define setPHAR(phar) \
|
||||
WIZCHIP_WRITE_BUF(_PHAR_,(phar),6)
|
||||
|
||||
#define getPHAR(phar) \
|
||||
WIZCHIP_READ_BUF(_PHAR_,(phar),6)
|
||||
|
||||
#define setPSIDR(psidr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_PSIDR_,(uint8_t)((psidr) >> 8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_,1),(uint8_t)(psidr)); \
|
||||
}while(0);
|
||||
|
||||
#define getPSIDR() \
|
||||
((((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_,1)))
|
||||
|
||||
#define setPMRUR(pmrur) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_PMRUR_,(uint8_t)((pmrur) >> 8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_,1),(uint8_t)(pmrur)); \
|
||||
}while(0);
|
||||
|
||||
#define getPMRUR() \
|
||||
((((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_,1)))
|
||||
|
||||
#define setSHAR(shar) \
|
||||
WIZCHIP_WRITE_BUF(_SHAR_,(shar),6)
|
||||
|
||||
#define getSHAR(shar) \
|
||||
WIZCHIP_READ_BUF(_SHAR_,(shar),6)
|
||||
|
||||
#define setGAR(gar) \
|
||||
WIZCHIP_WRITE_BUF(_GAR_,(gar),4)
|
||||
|
||||
#define getGAR(gar) \
|
||||
WIZCHIP_READ_BUF(_GAR_,(gar),4)
|
||||
|
||||
#define setGA4R(ga4r) setGAR(ga4r)
|
||||
#define getGA4R(ga4r) getGAR(ga4r)
|
||||
|
||||
#define setSUBR(subr) \
|
||||
WIZCHIP_WRITE_BUF(_SUBR_,(subr),4)
|
||||
|
||||
#define getSUBR(subr) \
|
||||
WIZCHIP_READ_BUF(_SUBR_,(subr),4)
|
||||
|
||||
#define setSUB4R(sub4r) setSUBR(sub4r)
|
||||
#define getSUB4R(sub4r) getSUBR(sub4r)
|
||||
|
||||
#define setSIPR(sipr) \
|
||||
WIZCHIP_WRITE_BUF(_SIPR_,(sipr),4)
|
||||
|
||||
#define getSIPR(sipr) \
|
||||
WIZCHIP_READ_BUF(_SIPR_,(sipr),4)
|
||||
|
||||
#define setLLAR(llar) \
|
||||
WIZCHIP_WRITE_BUF(_LLAR_,(llar),16)
|
||||
|
||||
#define getLLAR(llar) \
|
||||
WIZCHIP_READ_BUF(_LLAR_,(llar),16)
|
||||
|
||||
#define setGUAR(guar) \
|
||||
WIZCHIP_WRITE_BUF(_GUAR_,(guar),16)
|
||||
|
||||
#define getGUAR(guar) \
|
||||
WIZCHIP_READ_BUF(_GUAR_,(guar),16)
|
||||
|
||||
#define setSUB6R(sub6r) \
|
||||
WIZCHIP_WRITE_BUF(_SUB6R_,(sub6r),16)
|
||||
|
||||
#define getSUB6R(sub6r) \
|
||||
WIZCHIP_READ_BUF(_SUB6R_,(sub6r),16)
|
||||
|
||||
#define setGA6R(ga6r) \
|
||||
WIZCHIP_WRITE_BUF(_GA6R_,(ga6r),16)
|
||||
|
||||
#define getGA6R(ga6r) \
|
||||
WIZCHIP_READ_BUF(_GA6R_,(ga6r),16)
|
||||
|
||||
#define setSLDIPR(sldipr) \
|
||||
WIZCHIP_WRITE_BUF(_SLDIPR_,(sldipr),4)
|
||||
#define setSLDIP4R(sldip4r) setSLDIPR((sldip4r))
|
||||
|
||||
#define getSLDIPR(sldipr) \
|
||||
WIZCHIP_READ_BUF(_SLDIPR_,(sldipr),4)
|
||||
#define getSLDIP4R(sldip4r) getSLDIPR((sldip4r))
|
||||
|
||||
#define setSLDIP6R(sldip6r) \
|
||||
WIZCHIP_WRITE_BUF(_SLDIP6R_, (sldip6r),16)
|
||||
|
||||
#define getSLDIP6R(sldip6r) \
|
||||
WIZCHIP_READ_BUF(_SLDIP6R_,(sldip6r),16)
|
||||
|
||||
#define getSLDHAR(sldhar) \
|
||||
WIZCHIP_READ_BUF(_SLDHAR_,(sldhar),6)
|
||||
|
||||
#define setPINGIDR(pingidr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_PINGIDR_,(uint8_t)((pingidr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_,1),(uint8_t)(pingidr)); \
|
||||
}while(0);
|
||||
|
||||
#define getPINGIDR() \
|
||||
(((int16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_,1)))
|
||||
|
||||
#define setPINGSEQR(pingseqr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_PINGSEQR_,(uint8_t)((pingseqr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_,1),(uint8_t)(pingseqr)); \
|
||||
}while(0);
|
||||
|
||||
#define getPINGSEQR() \
|
||||
(((int16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_,1)))
|
||||
|
||||
#define getUIPR(uipr) \
|
||||
WIZCHIP_READ_BUF(_UIPR_, (uipr), 4)
|
||||
|
||||
#define getUIP4R(uip4r) getUIPR(uip4r)
|
||||
|
||||
#define getUPORTR() \
|
||||
((((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_,1)))
|
||||
|
||||
#define getUPORT4R() getUPORTR()
|
||||
|
||||
#define getUIP6R(uip6r) \
|
||||
WIZCHIP_READ_BUF(_UIP6R_,(uip6r),16)
|
||||
|
||||
#define getUPORT6R(uport6r) \
|
||||
((((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_,1)))
|
||||
|
||||
#define setINTPTMR(intptmr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_INTPTMR_,(uint8_t)((intptmr) >> 8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_,1),(uint8_t)(intptmr)); \
|
||||
}while(0);
|
||||
|
||||
#define getINTPTMR() \
|
||||
((((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_,1)))
|
||||
|
||||
#define getPLR() \
|
||||
WIZCHIP_READ(_PLR_)
|
||||
|
||||
#define getPFR() \
|
||||
WIZCHIP_READ(_PFR_)
|
||||
|
||||
#define getVLTR() \
|
||||
( (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,1))) << 16) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,2))) << 16) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,3))) << 16) )
|
||||
|
||||
#define getPLTR() \
|
||||
( (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,1))) << 16) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,2))) << 16) + \
|
||||
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,3))) << 16) )
|
||||
|
||||
#define getPAR(par) \
|
||||
WIZCHIP_READ_BUF(_PAR_, (par), 16)
|
||||
|
||||
#define setICMP6BLKR(icmp6blkr) \
|
||||
WIZCHIP_WRITE(_ICMP6BLKR_,(icmp6blkr))
|
||||
|
||||
#define getICMP6BLKR() \
|
||||
WIZCHIP_READ(_ICMP6BLKR_)
|
||||
|
||||
#define setCHPLCKR(chplckr) \
|
||||
WIZCHIP_WRITE(_CHPLCKR_, (chplckr))
|
||||
|
||||
#define getCHPLCKR() \
|
||||
((getSYSR() & SYSR_CHPL) >> 7)
|
||||
|
||||
#define CHIPLOCK() setCHPLCKR(0xFF)
|
||||
#define CHIPUNLOCK() setCHPLCKR(0xCE)
|
||||
|
||||
#define setNETLCKR(netlckr) \
|
||||
WIZCHIP_WRITE(_NETLCKR_, (netlckr))
|
||||
|
||||
#define getNETLCKR() \
|
||||
((getSYSR() & SYSR_NETL) >> 6)
|
||||
|
||||
#define NETLOCK() setNETLCKR(0xC5)
|
||||
#define NETUNLOCK() setNETLCKR(0x3A)
|
||||
|
||||
#define setPHYLCKR(phylckr) \
|
||||
WIZCHIP_WRITE(_PHYLCKR_,(phylckr))
|
||||
|
||||
#define getPHYLCKR() \
|
||||
((getSYSR() & SYSR_PHYL) >> 5)
|
||||
|
||||
#define PHYLOCK() setPHYLCKR(0xFF)
|
||||
#define PHYUNLOCK() setPHYLCKR(0x53)
|
||||
|
||||
#define setRTR(rtr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_RTR_,(uint8_t)((rtr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1),(uint8_t)(rtr)); \
|
||||
}while(0);
|
||||
|
||||
#define getRTR() \
|
||||
((((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
|
||||
|
||||
#define setRCR(rcr) \
|
||||
WIZCHIP_WRITE(_RCR_,(rcr))
|
||||
|
||||
#define getRCR() \
|
||||
WIZCHIP_READ(_RCR_)
|
||||
|
||||
#define setSLRTR(slrtr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_SLRTR_,(uint8_t)((slrtr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_,1),(uint8_t)(slrtr)); \
|
||||
}while(0);
|
||||
|
||||
#define getSLRTR() \
|
||||
((((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_,1)))
|
||||
|
||||
#define setSLRCR(slrcr) \
|
||||
WIZCHIP_WRITE(_SLRCR_,(slrcr))
|
||||
|
||||
#define getSLRCR() \
|
||||
WIZCHIP_READ(_SLRCR_)
|
||||
|
||||
#define setSLHOPR(slhopr) \
|
||||
WIZCHIP_WRITE(_SLHOPR_,(slhopr))
|
||||
|
||||
#define getSLHOPR() \
|
||||
WIZCHIP_READ(_SLHOPR_)
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
////////////////////////////////////
|
||||
// SOCKETn register I/O function //
|
||||
////////////////////////////////////
|
||||
/**
|
||||
@addtogroup Socket_register_access_function_W6300
|
||||
@{
|
||||
*/
|
||||
#define setSn_MR(sn,mr) \
|
||||
WIZCHIP_WRITE(_Sn_MR_(sn),(mr))
|
||||
#define getSn_MR(sn) \
|
||||
WIZCHIP_READ(_Sn_MR_(sn))
|
||||
|
||||
#define setSn_PSR(sn,psr) \
|
||||
WIZCHIP_WRITE(_Sn_PSR_(sn),(psr))
|
||||
#define getSn_PSR(sn) \
|
||||
WIZCHIP_READ(_Sn_PSR_(sn))
|
||||
|
||||
#define setSn_CR(sn,cr) \
|
||||
WIZCHIP_WRITE(_Sn_CR_(sn),(cr))
|
||||
#define getSn_CR(sn) \
|
||||
WIZCHIP_READ(_Sn_CR_(sn))
|
||||
|
||||
#define getSn_IR(sn) \
|
||||
WIZCHIP_READ(_Sn_IR_(sn))
|
||||
|
||||
#define setSn_IMR(sn,imr) \
|
||||
WIZCHIP_WRITE(_Sn_IMR_(sn),(imr))
|
||||
#define getSn_IMR(sn) \
|
||||
WIZCHIP_READ(_Sn_IMR_(sn))
|
||||
|
||||
#define setSn_IRCLR(sn,irclr) \
|
||||
WIZCHIP_WRITE(_Sn_IRCLR_(sn),(irclr))
|
||||
#define setSn_IR(sn,ir) setSn_IRCLR(sn,(ir))
|
||||
|
||||
#define getSn_SR(sn) \
|
||||
WIZCHIP_READ(_Sn_SR_(sn))
|
||||
|
||||
#define getSn_ESR(sn) \
|
||||
WIZCHIP_READ(_Sn_ESR_(sn))
|
||||
|
||||
#define setSn_PNR(sn,pnr) \
|
||||
WIZCHIP_WRITE(_Sn_PNR_(sn),(pnr))
|
||||
#define setSn_NHR(sn,nhr) setSn_PNR(_Sn_PNR_(sn),(nhr))
|
||||
|
||||
#define getSn_PNR(sn) \
|
||||
WIZCHIP_READ(_Sn_PNR_(sn))
|
||||
#define getSn_NHR(sn) getSn_PNR(sn)
|
||||
|
||||
#define setSn_TOSR(sn,tosr) \
|
||||
WIZCHIP_WRITE(_Sn_TOSR_(sn),(tosr))
|
||||
#define getSn_TOSR(sn) \
|
||||
WIZCHIP_READ(_Sn_TOSR_(sn))
|
||||
#define getSn_TOS(sn) getSn_TOSR(sn) ///< For compatible ioLibrar
|
||||
#define setSn_TOS(sn,tos) setSn_TOSR(sn,tos) ///< For compatible ioLibrar
|
||||
|
||||
|
||||
#define setSn_TTLR(sn,ttlr) \
|
||||
WIZCHIP_WRITE(_Sn_TTLR_(sn),(ttlr))
|
||||
#define getSn_TTLR(sn) \
|
||||
WIZCHIP_READ(_Sn_TTLR_(sn))
|
||||
#define setSn_TTL(sn,ttl) setSn_TTLR(sn,ttl) ///< For compatible ioLibrary
|
||||
#define getSn_TTL(sn) getSn_TTLR(sn) ///< For compatible ioLibrary
|
||||
|
||||
#define setSn_HOPR(sn,hopr) setSn_TTLR(sn),(ttlr))
|
||||
#define getSn_HOPR(sn) getSn_TTLR(sn)
|
||||
|
||||
#define setSn_FRGR(sn,frgr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_FRGR_(sn),(uint8_t)((frgr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1),(uint8_t)(frgr)); \
|
||||
}while(0);
|
||||
#define getSn_FRGR(sn,frgr) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1)))
|
||||
|
||||
#define setSn_MSSR(sn,mssr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_MSSR_(sn),(uint8_t)((mssr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1),(uint8_t)(mssr)); \
|
||||
}while(0);
|
||||
#define getSn_MSSR(sn) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1)))
|
||||
|
||||
#define setSn_PORTR(sn,portr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_PORTR_(sn),(uint8_t)((portr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1),(uint8_t)(portr)); \
|
||||
}while(0);
|
||||
#define getSn_PORTR(sn) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1)))
|
||||
|
||||
#define setSn_DHAR(sn,dhar) \
|
||||
WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn),(dhar),6)
|
||||
#define getSn_DHAR(sn,dhar) \
|
||||
WIZCHIP_READ_BUF(_Sn_DHAR_(sn),(dhar),6)
|
||||
|
||||
#define setSn_DIPR(sn,dipr) \
|
||||
WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn),(dipr),4)
|
||||
#define getSn_DIPR(sn,dipr) \
|
||||
WIZCHIP_READ_BUF(_Sn_DIPR_(sn),(dipr),4)
|
||||
|
||||
#define setSn_DIP4R(sn,dipr) setSn_DIPR(sn,(dipr))
|
||||
#define getSn_DIP4R(sn,dipr) getSn_DIPR(sn,(dipr))
|
||||
|
||||
#define setSn_DIP6R(sn,dip6r) \
|
||||
WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn),(dip6r),16)
|
||||
#define getSn_DIP6R(sn,dip6r) \
|
||||
WIZCHIP_READ_BUF(_Sn_DIP6R_(sn),(dip6r),16)
|
||||
|
||||
#define setSn_DPORTR(sn,dportr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_DPORTR_(sn),(uint8_t)((dportr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1),(uint8_t)(dportr)); \
|
||||
}while(0);
|
||||
|
||||
|
||||
#define getSn_DPORTR(sn) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1)))
|
||||
|
||||
#define getSn_DPORT(sn) getSn_DPORTR(sn)
|
||||
#define setSn_DPORT(sn,dportr) setSn_DPORTR(sn,dportr)
|
||||
|
||||
|
||||
#define setSn_MR2(sn,mr2) \
|
||||
WIZCHIP_WRITE(_Sn_MR2_(sn),(mr2))
|
||||
#define getSn_MR2(sn) \
|
||||
WIZCHIP_READ(_Sn_MR2_(sn))
|
||||
|
||||
#define setSn_RTR(sn,rtr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_RTR_(sn),(uint8_t)((rtr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1),(uint8_t)(rtr)); \
|
||||
}while(0);
|
||||
#define getSn_RTR(sn) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1)))
|
||||
|
||||
#define setSn_RCR(sn,rcr) \
|
||||
WIZCHIP_WRITE(_Sn_RCR_(sn),(rcr))
|
||||
#define getSn_RCR(sn) \
|
||||
WIZCHIP_READ(_Sn_RCR_(sn))
|
||||
|
||||
#define setSn_KPALVTR(sn,kpalvtr) \
|
||||
WIZCHIP_WRITE(_Sn_KPALVTR_(sn),(kpalvtr))
|
||||
#define getSn_KPALVTR(sn) \
|
||||
WIZCHIP_READ(_Sn_KPALVTR_(sn))
|
||||
|
||||
#define setSn_TX_BSR(sn, tmsr) \
|
||||
WIZCHIP_WRITE(_Sn_TX_BSR_(sn),(tmsr))
|
||||
#define setSn_TXBUF_SIZE(sn, tmsr) setSn_TX_BSR(sn,(tmsr))
|
||||
|
||||
#define getSn_TX_BSR(sn) \
|
||||
WIZCHIP_READ(_Sn_TX_BSR_(sn))
|
||||
#define getSn_TXBUF_SIZE(sn) getSn_TX_BSR(sn)
|
||||
|
||||
#define getSn_TxMAX(sn) \
|
||||
(getSn_TX_BSR(sn) << 10)
|
||||
|
||||
uint16_t getSn_TX_FSR(uint8_t sn);
|
||||
|
||||
#define getSn_TX_RD(sn) \
|
||||
((((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn),1)))
|
||||
|
||||
#define setSn_TX_WR(sn,txwr) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)((txwr)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1), (uint8_t)(txwr)); \
|
||||
}while(0);
|
||||
#define getSn_TX_WR(sn) \
|
||||
(((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1)))
|
||||
|
||||
#define setSn_RX_BSR(sn,rmsr) \
|
||||
WIZCHIP_WRITE(_Sn_RX_BSR_(sn),(rmsr))
|
||||
#define setSn_RXBUF_SIZE(sn,rmsr) setSn_RX_BSR(sn,(rmsr))
|
||||
|
||||
#define getSn_RX_BSR(sn) \
|
||||
WIZCHIP_READ(_Sn_RX_BSR_(sn))
|
||||
#define getSn_RXBUF_SIZE(sn) getSn_RX_BSR(sn)
|
||||
|
||||
#define getSn_RxMAX(sn) \
|
||||
(getSn_RX_BSR(sn) <<10)
|
||||
|
||||
uint16_t getSn_RX_RSR(uint8_t s);
|
||||
|
||||
#define setSn_RX_RD(sn,rxrd) \
|
||||
do{ \
|
||||
WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)((rxrd)>>8)); \
|
||||
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1), (uint8_t)(rxrd)) ; \
|
||||
}while(0);
|
||||
|
||||
#define getSn_RX_RD(sn) \
|
||||
(((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1)))
|
||||
|
||||
#define getSn_RX_WR(sn) \
|
||||
(((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn),1)))
|
||||
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
|
||||
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
|
||||
void wiz_recv_ignore(uint8_t sn, uint16_t len);
|
||||
void wiz_delay_ms(uint32_t ms);
|
||||
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
void wiz_mdio_write(uint8_t phyregaddr, uint16_t var);
|
||||
uint16_t wiz_mdio_read(uint8_t phyregaddr);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //_W6300_H_
|
||||
@@ -0,0 +1,594 @@
|
||||
#include <stddef.h>
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
void wizchip_cris_enter(void) {}
|
||||
void wizchip_cris_exit(void) {}
|
||||
void wizchip_cs_select(void) {}
|
||||
void wizchip_cs_deselect(void) {}
|
||||
|
||||
iodata_t wizchip_bus_readdata(uint32_t AddrSel) {
|
||||
return *((volatile iodata_t *)((ptrdiff_t)AddrSel));
|
||||
}
|
||||
|
||||
void wizchip_bus_writedata(uint32_t AddrSel, iodata_t wb) {
|
||||
*((volatile iodata_t *)((ptrdiff_t)AddrSel)) = wb;
|
||||
}
|
||||
|
||||
void wizchip_bus_read_buf(uint32_t AddrSel, iodata_t* buf, int16_t len, uint8_t addrinc) {
|
||||
if (addrinc) addrinc = sizeof(iodata_t);
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
*buf++ = WIZCHIP.IF.BUS._read_data(AddrSel);
|
||||
AddrSel += (uint32_t)addrinc;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_bus_write_buf(uint32_t AddrSel, iodata_t* buf, int16_t len, uint8_t addrinc) {
|
||||
if (addrinc) addrinc = sizeof(iodata_t);
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
WIZCHIP.IF.BUS._write_data(AddrSel, *buf++);
|
||||
AddrSel += (uint32_t)addrinc;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t wizchip_spi_readbyte(void) { return 0; }
|
||||
void wizchip_spi_writebyte(uint8_t wb) {}
|
||||
|
||||
void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {
|
||||
for (uint16_t i = 0; i < len; i++) *pBuf++ = WIZCHIP.IF.SPI._read_byte();
|
||||
}
|
||||
|
||||
void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {
|
||||
for (uint16_t i = 0; i < len; i++) WIZCHIP.IF.SPI._write_byte(*pBuf++);
|
||||
}
|
||||
|
||||
void wizchip_qspi_read(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len) {}
|
||||
void wizchip_qspi_write(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len) {}
|
||||
|
||||
_WIZCHIP WIZCHIP = {
|
||||
_WIZCHIP_IO_MODE_,
|
||||
_WIZCHIP_ID_,
|
||||
{ wizchip_cris_enter, wizchip_cris_exit },
|
||||
{ wizchip_cs_select, wizchip_cs_deselect },
|
||||
{ { wizchip_bus_readdata, wizchip_bus_writedata } }
|
||||
};
|
||||
|
||||
static uint8_t _DNS_[4];
|
||||
static uint8_t _DNS6_[16];
|
||||
static ipconf_mode _IPMODE_;
|
||||
|
||||
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void)) {
|
||||
if (!cris_en || !cris_ex) {
|
||||
WIZCHIP.CRIS._enter = wizchip_cris_enter;
|
||||
WIZCHIP.CRIS._exit = wizchip_cris_exit;
|
||||
} else {
|
||||
WIZCHIP.CRIS._enter = cris_en;
|
||||
WIZCHIP.CRIS._exit = cris_ex;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void)) {
|
||||
if (!cs_sel || !cs_desel) {
|
||||
WIZCHIP.CS._select = wizchip_cs_select;
|
||||
WIZCHIP.CS._deselect = wizchip_cs_deselect;
|
||||
} else {
|
||||
WIZCHIP.CS._select = cs_sel;
|
||||
WIZCHIP.CS._deselect = cs_desel;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_bus_cbfunc(iodata_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
|
||||
if (!bus_rb || !bus_wb) {
|
||||
WIZCHIP.IF.BUS._read_data = wizchip_bus_readdata;
|
||||
WIZCHIP.IF.BUS._write_data = wizchip_bus_writedata;
|
||||
} else {
|
||||
WIZCHIP.IF.BUS._read_data = bus_rb;
|
||||
WIZCHIP.IF.BUS._write_data = bus_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
|
||||
if (!spi_rb || !spi_wb) {
|
||||
WIZCHIP.IF.SPI._read_byte = wizchip_spi_readbyte;
|
||||
WIZCHIP.IF.SPI._write_byte = wizchip_spi_writebyte;
|
||||
} else {
|
||||
WIZCHIP.IF.SPI._read_byte = spi_rb;
|
||||
WIZCHIP.IF.SPI._write_byte = spi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
|
||||
if (!spi_rb || !spi_wb) {
|
||||
WIZCHIP.IF.SPI._read_burst = wizchip_spi_readburst;
|
||||
WIZCHIP.IF.SPI._write_burst = wizchip_spi_writeburst;
|
||||
} else {
|
||||
WIZCHIP.IF.SPI._read_burst = spi_rb;
|
||||
WIZCHIP.IF.SPI._write_burst = spi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_qspi_cbfunc(void (*qspi_rb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len),
|
||||
void (*qspi_wb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_QSPI_));
|
||||
if (!qspi_rb || !qspi_wb) {
|
||||
WIZCHIP.IF.QSPI._read_qspi = wizchip_qspi_read;
|
||||
WIZCHIP.IF.QSPI._write_qspi = wizchip_qspi_write;
|
||||
} else {
|
||||
WIZCHIP.IF.QSPI._read_qspi = qspi_rb;
|
||||
WIZCHIP.IF.QSPI._write_qspi = qspi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg) {
|
||||
uint8_t tmp = *(uint8_t*)arg;
|
||||
uint8_t* ptmp[2] = {0, 0};
|
||||
switch (cwtype) {
|
||||
case CW_SYS_LOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYLOCK();
|
||||
break;
|
||||
case CW_SYS_UNLOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPUNLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETUNLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYUNLOCK();
|
||||
break;
|
||||
case CW_GET_SYSLOCK:
|
||||
*(uint8_t*)arg = getSYSR() >> 5;
|
||||
break;
|
||||
case CW_RESET_WIZCHIP:
|
||||
wizchip_sw_reset();
|
||||
break;
|
||||
case CW_INIT_WIZCHIP:
|
||||
if (arg != 0) {
|
||||
ptmp[0] = (uint8_t*)arg;
|
||||
ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
|
||||
}
|
||||
return wizchip_init(ptmp[0], ptmp[1]);
|
||||
case CW_CLR_INTERRUPT:
|
||||
wizchip_clrinterrupt(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTERRUPT:
|
||||
*((intr_kind*)arg) = wizchip_getinterrupt();
|
||||
break;
|
||||
case CW_SET_INTRMASK:
|
||||
wizchip_setinterruptmask(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTRMASK:
|
||||
*((intr_kind*)arg) = wizchip_getinterruptmask();
|
||||
break;
|
||||
case CW_SET_INTRTIME:
|
||||
setINTPTMR(*(uint16_t*)arg);
|
||||
break;
|
||||
case CW_GET_INTRTIME:
|
||||
*(uint16_t*)arg = getINTPTMR();
|
||||
break;
|
||||
case CW_GET_ID:
|
||||
((uint8_t*)arg)[0] = WIZCHIP.id[0];
|
||||
((uint8_t*)arg)[1] = WIZCHIP.id[1];
|
||||
((uint8_t*)arg)[2] = WIZCHIP.id[2];
|
||||
((uint8_t*)arg)[3] = WIZCHIP.id[3];
|
||||
((uint8_t*)arg)[4] = WIZCHIP.id[4];
|
||||
((uint8_t*)arg)[5] = WIZCHIP.id[5];
|
||||
((uint8_t*)arg)[6] = 0;
|
||||
break;
|
||||
case CW_GET_VER:
|
||||
*(uint16_t*)arg = getVER();
|
||||
break;
|
||||
case CW_RESET_PHY:
|
||||
wizphy_reset();
|
||||
break;
|
||||
case CW_SET_PHYCONF:
|
||||
wizphy_setphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYCONF:
|
||||
wizphy_getphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYSTATUS:
|
||||
break;
|
||||
case CW_SET_PHYPOWMODE:
|
||||
wizphy_setphypmode(*(uint8_t*)arg);
|
||||
break;
|
||||
case CW_GET_PHYPOWMODE:
|
||||
tmp = wizphy_getphypmode();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
case CW_GET_PHYLINK:
|
||||
tmp = wizphy_getphylink();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg) {
|
||||
switch (cntype) {
|
||||
case CN_SET_NETINFO:
|
||||
wizchip_setnetinfo((wiz_NetInfo*)arg);
|
||||
break;
|
||||
case CN_GET_NETINFO:
|
||||
wizchip_getnetinfo((wiz_NetInfo*)arg);
|
||||
break;
|
||||
case CN_SET_NETMODE:
|
||||
wizchip_setnetmode(*(netmode_type*)arg);
|
||||
break;
|
||||
case CN_GET_NETMODE:
|
||||
*(netmode_type*)arg = wizchip_getnetmode();
|
||||
break;
|
||||
case CN_SET_TIMEOUT:
|
||||
wizchip_settimeout((wiz_NetTimeout*)arg);
|
||||
break;
|
||||
case CN_GET_TIMEOUT:
|
||||
wizchip_gettimeout((wiz_NetTimeout*)arg);
|
||||
break;
|
||||
case CN_SET_PREFER:
|
||||
setSLPSR(*(uint8_t*)arg);
|
||||
break;
|
||||
case CN_GET_PREFER:
|
||||
*(uint8_t*)arg = getSLPSR();
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg) {
|
||||
switch (cnstype) {
|
||||
case CNS_ARP:
|
||||
return wizchip_arp((wiz_ARP*)arg);
|
||||
case CNS_PING:
|
||||
return wizchip_ping((wiz_PING*)arg);
|
||||
case CNS_DAD:
|
||||
return wizchip_dad((uint8_t*)arg);
|
||||
case CNS_SLAAC:
|
||||
return wizchip_slaac((wiz_Prefix*)arg);
|
||||
case CNS_UNSOL_NA:
|
||||
return wizchip_unsolicited();
|
||||
case CNS_GET_PREFIX:
|
||||
return wizchip_getprefix((wiz_Prefix*)arg);
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_sw_reset(void) {
|
||||
uint8_t gw[4], sn[4], sip[4];
|
||||
uint8_t mac[6];
|
||||
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
||||
uint8_t islock = getSYSR();
|
||||
|
||||
CHIPUNLOCK();
|
||||
getSHAR(mac);
|
||||
getGAR(gw); getSUBR(sn); getSIPR(sip);
|
||||
getGA6R(gw6); getSUB6R(sn6); getLLAR(lla); getGUAR(gua);
|
||||
setSYCR0(SYCR0_RST);
|
||||
getSYCR0();
|
||||
|
||||
NETUNLOCK();
|
||||
setSHAR(mac);
|
||||
setGAR(gw); setSUBR(sn); setSIPR(sip);
|
||||
setGA6R(gw6); setSUB6R(sn6); setLLAR(lla); setGUAR(gua);
|
||||
|
||||
if (islock & SYSR_CHPL) CHIPLOCK();
|
||||
if (islock & SYSR_NETL) NETLOCK();
|
||||
}
|
||||
|
||||
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize) {
|
||||
int8_t i;
|
||||
int8_t tmp = 0;
|
||||
wizchip_sw_reset();
|
||||
|
||||
if (txsize) {
|
||||
tmp = 0;
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
tmp += txsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
setSn_TXBUF_SIZE(i, txsize[i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (rxsize) {
|
||||
tmp = 0;
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
tmp += rxsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
setSn_RXBUF_SIZE(i, rxsize[i]);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wizchip_clrinterrupt(intr_kind intr) {
|
||||
uint8_t ir = (uint8_t)intr;
|
||||
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
||||
uint8_t slir = (uint8_t)((uint32_t)intr >> 16);
|
||||
setIRCLR(ir);
|
||||
for (int i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
if (sir & (1 << i)) setSn_IRCLR(i, 0xFF);
|
||||
}
|
||||
setSLIRCLR(slir);
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterrupt(void) {
|
||||
uint8_t ir = getIR();
|
||||
uint8_t sir = getSIR();
|
||||
uint32_t ret = sir;
|
||||
ret = (ret << 8) + ir;
|
||||
ret = (((uint32_t)getSLIR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
void wizchip_setinterruptmask(intr_kind intr) {
|
||||
uint8_t imr = (uint8_t)intr;
|
||||
uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
|
||||
uint8_t slimr = (uint8_t)((uint32_t)intr >> 16);
|
||||
setIMR(imr);
|
||||
setSIMR(simr);
|
||||
setSLIMR(slimr);
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterruptmask(void) {
|
||||
uint8_t imr = getIMR();
|
||||
uint8_t simr = getSIMR();
|
||||
uint32_t ret = simr;
|
||||
ret = (ret << 8) + imr;
|
||||
ret = (((uint32_t)getSLIMR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
int8_t wizphy_getphylink(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
return (getPHYSR() & PHYSR_LNK);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
if (wiz_mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON;
|
||||
return PHY_LINK_OFF;
|
||||
#endif
|
||||
}
|
||||
|
||||
int8_t wizphy_getphypmode(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
if (getPHYCR1() & PHYCR1_PWDN) return PHY_POWER_DOWN;
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
if (wiz_mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN;
|
||||
#endif
|
||||
return PHY_POWER_NORM;
|
||||
}
|
||||
|
||||
void wizphy_reset(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYCR1() | PHYCR1_RST;
|
||||
PHYUNLOCK();
|
||||
setPHYCR1(tmp);
|
||||
PHYLOCK();
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
wiz_mdio_write(PHYRAR_BMCR, wiz_mdio_read(PHYRAR_BMCR) | BMCR_RST);
|
||||
while (wiz_mdio_read(PHYRAR_BMCR) & BMCR_RST);
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_setphyconf(wiz_PhyConf* phyconf) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = 0;
|
||||
if (phyconf->mode == PHY_MODE_TE) {
|
||||
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
||||
tmp = PHYCR0_AUTO;
|
||||
} else {
|
||||
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
||||
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
||||
tmp = PHYCR0_AUTO;
|
||||
} else {
|
||||
tmp |= 0x04;
|
||||
if (phyconf->speed == PHY_SPEED_10) tmp |= 0x02;
|
||||
if (phyconf->duplex == PHY_DUPLEX_HALF) tmp |= 0x01;
|
||||
}
|
||||
}
|
||||
setPHYCR0(tmp);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (phyconf->mode == PHY_MODE_TE) {
|
||||
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
||||
setPHYCR0(PHYCR0_AUTO);
|
||||
} else {
|
||||
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
||||
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
||||
tmp |= BMCR_ANE;
|
||||
} else {
|
||||
tmp &= ~(BMCR_ANE | BMCR_DPX | BMCR_SPD);
|
||||
if (phyconf->duplex == PHY_DUPLEX_FULL) tmp |= BMCR_DPX;
|
||||
if (phyconf->speed == PHY_SPEED_100) tmp |= BMCR_SPD;
|
||||
}
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_getphyconf(wiz_PhyConf* phyconf) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYSR();
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
||||
phyconf->speed = (tmp & (1 << 4)) ? PHY_SPEED_10 : PHY_SPEED_100;
|
||||
phyconf->duplex = (tmp & (1 << 3)) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & BMCR_ANE) ? PHY_MODE_AUTONEGO : PHY_MODE_MANUAL);
|
||||
phyconf->duplex = (tmp & BMCR_DPX) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
|
||||
phyconf->speed = (tmp & BMCR_SPD) ? PHY_SPEED_100 : PHY_SPEED_10;
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_getphystat(wiz_PhyConf* phyconf) {
|
||||
uint8_t tmp = getPHYSR();
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
||||
phyconf->speed = (tmp & PHYSR_SPD) ? PHY_SPEED_10 : PHY_SPEED_100;
|
||||
phyconf->duplex = (tmp & PHYSR_DPX) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
||||
}
|
||||
|
||||
void wizphy_setphypmode(uint8_t pmode) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYCR1();
|
||||
if (pmode == PHY_POWER_DOWN) tmp |= PHYCR1_PWDN;
|
||||
else tmp &= ~PHYCR1_PWDN;
|
||||
setPHYCR1(tmp);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (pmode == PHY_POWER_DOWN) tmp |= BMCR_PWDN;
|
||||
else tmp &= ~BMCR_PWDN;
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo) {
|
||||
setSHAR(pnetinfo->mac);
|
||||
setGAR(pnetinfo->gw);
|
||||
setSUBR(pnetinfo->sn);
|
||||
setSIPR(pnetinfo->ip);
|
||||
setGA6R(pnetinfo->gw6);
|
||||
setSUB6R(pnetinfo->sn6);
|
||||
setLLAR(pnetinfo->lla);
|
||||
setGUAR(pnetinfo->gua);
|
||||
for (uint8_t i = 0; i < 4; i++) _DNS_[i] = pnetinfo->dns[i];
|
||||
for (uint8_t i = 0; i < 16; i++) _DNS6_[i] = pnetinfo->dns6[i];
|
||||
_IPMODE_ = pnetinfo->ipmode;
|
||||
}
|
||||
|
||||
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo) {
|
||||
getSHAR(pnetinfo->mac);
|
||||
getGAR(pnetinfo->gw);
|
||||
getSUBR(pnetinfo->sn);
|
||||
getSIPR(pnetinfo->ip);
|
||||
getGA6R(pnetinfo->gw6);
|
||||
getSUB6R(pnetinfo->sn6);
|
||||
getLLAR(pnetinfo->lla);
|
||||
getGUAR(pnetinfo->gua);
|
||||
for (uint8_t i = 0; i < 4; i++) pnetinfo->dns[i] = _DNS_[i];
|
||||
for (uint8_t i = 0; i < 16; i++) pnetinfo->dns6[i] = _DNS6_[i];
|
||||
pnetinfo->ipmode = _IPMODE_;
|
||||
}
|
||||
|
||||
void wizchip_setnetmode(netmode_type netmode) {
|
||||
uint32_t tmp = (uint32_t)netmode;
|
||||
setNETMR((uint8_t)tmp);
|
||||
setNETMR2((uint8_t)(tmp >> 8));
|
||||
setNET4MR((uint8_t)(tmp >> 16));
|
||||
setNET6MR((uint8_t)(tmp >> 24));
|
||||
}
|
||||
|
||||
netmode_type wizchip_getnetmode(void) {
|
||||
uint32_t ret = getNETMR();
|
||||
ret = (ret << 8) + getNETMR2();
|
||||
ret = (ret << 16) + getNET4MR();
|
||||
ret = (ret << 24) + getNET6MR();
|
||||
return (netmode_type)ret;
|
||||
}
|
||||
|
||||
void wizchip_settimeout(wiz_NetTimeout* nettime) {
|
||||
setRCR(nettime->s_retry_cnt);
|
||||
setRTR(nettime->s_time_100us);
|
||||
setSLRCR(nettime->sl_retry_cnt);
|
||||
setSLRTR(nettime->sl_time_100us);
|
||||
}
|
||||
|
||||
void wizchip_gettimeout(wiz_NetTimeout* nettime) {
|
||||
nettime->s_retry_cnt = getRCR();
|
||||
nettime->s_time_100us = getRTR();
|
||||
nettime->sl_retry_cnt = getSLRCR();
|
||||
nettime->sl_time_100us = getSLRTR();
|
||||
}
|
||||
|
||||
int8_t wizchip_arp(wiz_ARP* arp) {
|
||||
uint8_t tmp;
|
||||
if (arp->destinfo.len == 16) {
|
||||
setSLDIP6R(arp->destinfo.ip);
|
||||
setSLCR(SLCR_ARP6);
|
||||
} else {
|
||||
setSLDIP4R(arp->destinfo.ip);
|
||||
setSLCR(SLCR_ARP4);
|
||||
}
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_ARP4 | SLIR_ARP6)) {
|
||||
getSLDHAR(arp->dha);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_ping(wiz_PING* ping) {
|
||||
uint8_t tmp;
|
||||
setPINGIDR(ping->id);
|
||||
setPINGSEQR(ping->seq);
|
||||
if (ping->destinfo.len == 16) {
|
||||
setSLDIP6R(ping->destinfo.ip);
|
||||
setSLCR(SLCR_PING6);
|
||||
} else {
|
||||
setSLDIP4R(ping->destinfo.ip);
|
||||
setSLCR(SLCR_PING4);
|
||||
}
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_PING4 | SLIR_PING6)) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_dad(uint8_t* ipv6) {
|
||||
uint8_t tmp;
|
||||
setSLDIP6R(ipv6);
|
||||
setSLCR(SLCR_NS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_slaac(wiz_Prefix* prefix) {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_RS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_RS) {
|
||||
prefix->len = getPLR();
|
||||
prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR();
|
||||
prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_unsolicited(void) {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_UNA);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_getprefix(wiz_Prefix* prefix) {
|
||||
if (getSLIR() & SLIR_RA) {
|
||||
prefix->len = getPLR();
|
||||
prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR();
|
||||
prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
setSLIRCLR(SLIR_RA);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
@@ -0,0 +1,321 @@
|
||||
#ifndef _WIZCHIP_CONF_H_
|
||||
#define _WIZCHIP_CONF_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define W6300 6300
|
||||
|
||||
#ifndef _WIZCHIP_
|
||||
#define _WIZCHIP_ W6300
|
||||
#endif
|
||||
|
||||
#define _WIZCHIP_IO_MODE_NONE_ 0x0000
|
||||
#define _WIZCHIP_IO_MODE_BUS_ 0x0100
|
||||
#define _WIZCHIP_IO_MODE_SPI_ 0x0200
|
||||
#define _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1)
|
||||
#define _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2)
|
||||
#define _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1)
|
||||
#define _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2)
|
||||
#define _WIZCHIP_IO_MODE_SPI_5500_ (_WIZCHIP_IO_MODE_SPI_ + 3)
|
||||
#define _WIZCHIP_IO_MODE_SPI_QSPI_ (_WIZCHIP_IO_MODE_SPI_ + 4)
|
||||
|
||||
#define _PHY_IO_MODE_PHYCR_ 0x0000
|
||||
#define _PHY_IO_MODE_MII_ 0x0010
|
||||
#define _PHY_IO_MODE_ _PHY_IO_MODE_MII_
|
||||
|
||||
#define QSPI_SINGLE_MODE (0x00 << 6)
|
||||
#define QSPI_DUAL_MODE (0x01 << 6)
|
||||
#define QSPI_QUAD_MODE (0x02 << 6)
|
||||
|
||||
#ifndef _WIZCHIP_QSPI_MODE_
|
||||
#define _WIZCHIP_QSPI_MODE_ QSPI_SINGLE_MODE
|
||||
#endif
|
||||
|
||||
#define _WIZCHIP_ID_ "W6300\0"
|
||||
#define _WIZCHIP_IO_MODE_ ((_WIZCHIP_IO_MODE_SPI_ & 0xff00) | (_WIZCHIP_QSPI_MODE_ & 0x00ff))
|
||||
|
||||
typedef uint8_t iodata_t;
|
||||
typedef int16_t datasize_t;
|
||||
#include "w6300.h"
|
||||
|
||||
#ifndef _WIZCHIP_IO_BASE_
|
||||
#define _WIZCHIP_IO_BASE_ 0x00000000
|
||||
#endif
|
||||
|
||||
#define _WIZCHIP_SOCK_NUM_ 8
|
||||
|
||||
typedef struct __WIZCHIP {
|
||||
uint16_t if_mode;
|
||||
uint8_t id[8];
|
||||
struct _CRIS {
|
||||
void (*_enter)(void);
|
||||
void (*_exit)(void);
|
||||
} CRIS;
|
||||
struct _CS {
|
||||
void (*_select)(void);
|
||||
void (*_deselect)(void);
|
||||
} CS;
|
||||
union _IF {
|
||||
struct {
|
||||
iodata_t (*_read_data)(uint32_t AddrSel);
|
||||
void (*_write_data)(uint32_t AddrSel, iodata_t wb);
|
||||
void (*_read_data_buf)(uint32_t AddrSel, iodata_t* pBuf, int16_t len, uint8_t addrinc);
|
||||
void (*_write_data_buf)(uint32_t AddrSel, iodata_t* pBuf, int16_t len, uint8_t addrinc);
|
||||
} BUS;
|
||||
struct {
|
||||
uint8_t (*_read_byte)(void);
|
||||
void (*_write_byte)(uint8_t wb);
|
||||
void (*_read_burst)(uint8_t* pBuf, uint16_t len);
|
||||
void (*_write_burst)(uint8_t* pBuf, uint16_t len);
|
||||
} SPI;
|
||||
struct {
|
||||
void (*_read_qspi)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
void (*_write_qspi)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
} QSPI;
|
||||
} IF;
|
||||
} _WIZCHIP;
|
||||
|
||||
extern _WIZCHIP WIZCHIP;
|
||||
|
||||
typedef enum {
|
||||
CW_SYS_LOCK,
|
||||
CW_SYS_UNLOCK,
|
||||
CW_GET_SYSLOCK,
|
||||
CW_RESET_WIZCHIP,
|
||||
CW_INIT_WIZCHIP,
|
||||
CW_GET_INTERRUPT,
|
||||
CW_CLR_INTERRUPT,
|
||||
CW_SET_INTRMASK,
|
||||
CW_GET_INTRMASK,
|
||||
CW_SET_INTRTIME,
|
||||
CW_GET_INTRTIME,
|
||||
CW_SET_IEN,
|
||||
CW_GET_IEN,
|
||||
CW_GET_ID,
|
||||
CW_GET_VER,
|
||||
CW_SET_SYSCLK,
|
||||
CW_GET_SYSCLK,
|
||||
CW_RESET_PHY,
|
||||
CW_SET_PHYCONF,
|
||||
CW_GET_PHYCONF,
|
||||
CW_GET_PHYSTATUS,
|
||||
CW_SET_PHYPOWMODE,
|
||||
CW_GET_PHYPOWMODE,
|
||||
CW_GET_PHYLINK
|
||||
} ctlwizchip_type;
|
||||
|
||||
typedef enum {
|
||||
CN_SET_NETINFO,
|
||||
CN_GET_NETINFO,
|
||||
CN_SET_NETMODE,
|
||||
CN_GET_NETMODE,
|
||||
CN_SET_TIMEOUT,
|
||||
CN_GET_TIMEOUT,
|
||||
CN_SET_PREFER,
|
||||
CN_GET_PREFER,
|
||||
} ctlnetwork_type;
|
||||
|
||||
typedef enum {
|
||||
CNS_ARP,
|
||||
CNS_PING,
|
||||
CNS_DAD,
|
||||
CNS_SLAAC,
|
||||
CNS_UNSOL_NA,
|
||||
CNS_GET_PREFIX
|
||||
} ctlnetservice_type;
|
||||
|
||||
typedef enum {
|
||||
IK_PPPOE_TERMINATED = (1 << 0),
|
||||
IK_DEST_UNREACH = (1 << 1),
|
||||
IK_IP_CONFLICT = (1 << 2),
|
||||
IK_DEST_UNREACH6 = (1 << 4),
|
||||
IK_WOL = (1 << 7),
|
||||
IK_NET_ALL = (0x97),
|
||||
IK_SOCK_0 = (1 << 8),
|
||||
IK_SOCK_1 = (1 << 9),
|
||||
IK_SOCK_2 = (1 << 10),
|
||||
IK_SOCK_3 = (1 << 11),
|
||||
IK_SOCK_4 = (1 << 12),
|
||||
IK_SOCK_5 = (1 << 13),
|
||||
IK_SOCK_6 = (1 << 14),
|
||||
IK_SOCK_7 = (1 << 15),
|
||||
IK_SOCK_ALL = (0xFF << 8),
|
||||
IK_SOCKL_TOUT = (1 << 16),
|
||||
IK_SOCKL_ARP4 = (1 << 17),
|
||||
IK_SOCKL_PING4 = (1 << 18),
|
||||
IK_SOCKL_ARP6 = (1 << 19),
|
||||
IK_SOCKL_PING6 = (1 << 20),
|
||||
IK_SOCKL_NS = (1 << 21),
|
||||
IK_SOCKL_RS = (1 << 22),
|
||||
IK_SOCKL_RA = (1 << 23),
|
||||
IK_SOCKL_ALL = (0xFF << 16),
|
||||
IK_INT_ALL = (0x00FFFF97)
|
||||
} intr_kind;
|
||||
|
||||
#define SYS_CHIP_LOCK (1<<2)
|
||||
#define SYS_NET_LOCK (1<<1)
|
||||
#define SYS_PHY_LOCK (1<<0)
|
||||
|
||||
#define SYSCLK_100MHZ 0
|
||||
#define SYSCLK_25MHZ 1
|
||||
|
||||
#define PHY_MODE_MANUAL 0
|
||||
#define PHY_MODE_AUTONEGO 1
|
||||
#define PHY_MODE_TE 2
|
||||
|
||||
#define IPV6_ADDR_AUTO 0x00
|
||||
#define IPV6_ADDR_LLA 0x02
|
||||
#define IPV6_ADDR_GUA 0x03
|
||||
|
||||
#define PHY_CONFBY_HW 0
|
||||
#define PHY_CONFBY_SW 1
|
||||
#define PHY_SPEED_10 0
|
||||
#define PHY_SPEED_100 1
|
||||
#define PHY_DUPLEX_HALF 0
|
||||
#define PHY_DUPLEX_FULL 1
|
||||
#define PHY_LINK_OFF 0
|
||||
#define PHY_LINK_ON 1
|
||||
#define PHY_POWER_NORM 0
|
||||
#define PHY_POWER_DOWN 1
|
||||
|
||||
typedef struct wiz_PhyConf_t {
|
||||
uint8_t by;
|
||||
uint8_t mode;
|
||||
uint8_t speed;
|
||||
uint8_t duplex;
|
||||
} wiz_PhyConf;
|
||||
|
||||
typedef enum {
|
||||
NETINFO_NONE = 0x00,
|
||||
NETINFO_STATIC_V4 = 0x01,
|
||||
NETINFO_STATIC_V6 = 0x02,
|
||||
NETINFO_STATIC_ALL = 0x03,
|
||||
NETINFO_SLAAC_V6 = 0x04,
|
||||
NETINFO_DHCP_V4 = 0x10,
|
||||
NETINFO_DHCP_V6 = 0x20,
|
||||
NETINFO_DHCP_ALL = 0x30
|
||||
} ipconf_mode;
|
||||
|
||||
typedef enum {
|
||||
NETINFO_STATIC = 1,
|
||||
NETINFO_DHCP
|
||||
} dhcp_mode;
|
||||
|
||||
typedef struct wiz_NetInfo_t {
|
||||
uint8_t mac[6];
|
||||
uint8_t ip[4];
|
||||
uint8_t sn[4];
|
||||
uint8_t gw[4];
|
||||
uint8_t lla[16];
|
||||
uint8_t gua[16];
|
||||
uint8_t sn6[16];
|
||||
uint8_t gw6[16];
|
||||
uint8_t dns[4];
|
||||
uint8_t dns6[16];
|
||||
ipconf_mode ipmode;
|
||||
dhcp_mode dhcp;
|
||||
} wiz_NetInfo;
|
||||
|
||||
typedef enum {
|
||||
NM_IPB_V4 = (1 << 0),
|
||||
NM_IPB_V6 = (1 << 1),
|
||||
NM_WOL = (1 << 2),
|
||||
NM_PB6_MULTI = (1 << 4),
|
||||
NM_PB6_ALLNODE = (1 << 5),
|
||||
NM_MR_MASK = (0x37),
|
||||
NM_PPPoE = (1 << 8),
|
||||
NM_DHA_SELECT = (1 << 15),
|
||||
NM_MR2_MASK = (0x09 << 8),
|
||||
NM_PB4_ALL = (1 << 16),
|
||||
NM_TRSTB_V4 = (1 << 17),
|
||||
NM_PARP_V4 = (1 << 18),
|
||||
NM_UNRB_V4 = (1 << 19),
|
||||
NM_NET4_MASK = (0x0F << 16),
|
||||
NM_PB6_ALL = (1 << 24),
|
||||
NM_TRSTB_V6 = (1 << 25),
|
||||
NM_PARP_V6 = (1 << 26),
|
||||
NM_UNRB_V6 = (1 << 27),
|
||||
NM_NET6_MASK = (0x0F << 24),
|
||||
NM_MASK_ALL = (0x0F0F0937)
|
||||
} netmode_type;
|
||||
|
||||
typedef struct wiz_NetTimeout_t {
|
||||
uint8_t s_retry_cnt;
|
||||
uint16_t s_time_100us;
|
||||
uint8_t sl_retry_cnt;
|
||||
uint16_t sl_time_100us;
|
||||
} wiz_NetTimeout;
|
||||
|
||||
typedef struct wiz_IPAddress_t {
|
||||
uint8_t ip[16];
|
||||
uint8_t len;
|
||||
} wiz_IPAddress;
|
||||
|
||||
typedef struct wiz_Prefix_t {
|
||||
uint8_t len;
|
||||
uint8_t flag;
|
||||
uint32_t valid_lifetime;
|
||||
uint32_t preferred_lifetime;
|
||||
uint8_t prefix[16];
|
||||
} wiz_Prefix;
|
||||
|
||||
typedef struct wiz_ARP_t {
|
||||
wiz_IPAddress destinfo;
|
||||
uint8_t dha[6];
|
||||
} wiz_ARP;
|
||||
|
||||
typedef struct wiz_PING_t {
|
||||
uint16_t id;
|
||||
uint16_t seq;
|
||||
wiz_IPAddress destinfo;
|
||||
} wiz_PING;
|
||||
|
||||
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void));
|
||||
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void));
|
||||
void reg_wizchip_bus_cbfunc(iodata_t (*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb));
|
||||
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb));
|
||||
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len));
|
||||
void reg_wizchip_qspi_cbfunc(void (*qspi_rb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len), void (*qspi_wb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len));
|
||||
|
||||
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg);
|
||||
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg);
|
||||
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg);
|
||||
|
||||
void wizchip_sw_reset(void);
|
||||
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize);
|
||||
void wizchip_clrinterrupt(intr_kind intr);
|
||||
intr_kind wizchip_getinterrupt(void);
|
||||
void wizchip_setinterruptmask(intr_kind intr);
|
||||
intr_kind wizchip_getinterruptmask(void);
|
||||
|
||||
int8_t wizphy_getphylink(void);
|
||||
int8_t wizphy_getphypmode(void);
|
||||
void wizphy_reset(void);
|
||||
void wizphy_setphyconf(wiz_PhyConf* phyconf);
|
||||
void wizphy_getphyconf(wiz_PhyConf* phyconf);
|
||||
void wizphy_getphystat(wiz_PhyConf* phyconf);
|
||||
void wizphy_setphypmode(uint8_t pmode);
|
||||
|
||||
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo);
|
||||
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo);
|
||||
void wizchip_setnetmode(netmode_type netmode);
|
||||
netmode_type wizchip_getnetmode(void);
|
||||
void wizchip_settimeout(wiz_NetTimeout* nettime);
|
||||
void wizchip_gettimeout(wiz_NetTimeout* nettime);
|
||||
|
||||
int8_t wizchip_arp(wiz_ARP* arp);
|
||||
int8_t wizchip_ping(wiz_PING* ping);
|
||||
int8_t wizchip_dad(uint8_t* ipv6);
|
||||
int8_t wizchip_slaac(wiz_Prefix* prefix);
|
||||
int8_t wizchip_unsolicited(void);
|
||||
int8_t wizchip_getprefix(wiz_Prefix* prefix);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,9 +1,3 @@
|
||||
/*
|
||||
Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
@@ -33,24 +27,12 @@
|
||||
#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
|
||||
#endif
|
||||
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
|
||||
#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
|
||||
#define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits)
|
||||
#define PIO_OFFSET_WRITE_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits_end)
|
||||
#define PIO_OFFSET_READ_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_read_bits_end)
|
||||
|
||||
#else
|
||||
#define PIO_PROGRAM_NAME wiznet_spi_write_read
|
||||
#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
|
||||
#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
|
||||
#define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits)
|
||||
#define PIO_OFFSET_WRITE_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_write_end)
|
||||
#define PIO_OFFSET_READ_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_read_end)
|
||||
// All wiznet spi operations must start with writing a 3 byte header
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef PICO_WIZNET_SPI_PIO_INSTANCE_COUNT
|
||||
#define PICO_WIZNET_SPI_PIO_INSTANCE_COUNT 1
|
||||
#endif
|
||||
@@ -116,9 +98,7 @@ static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
|
||||
// Initialise our gpios
|
||||
static void pio_spi_gpio_setup(spi_pio_state_t *state) {
|
||||
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
|
||||
// Setup DO and DI
|
||||
gpio_init(state->spi_config->data_io0_pin);
|
||||
gpio_init(state->spi_config->data_io1_pin);
|
||||
gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
|
||||
@@ -126,7 +106,6 @@ static void pio_spi_gpio_setup(spi_pio_state_t *state) {
|
||||
gpio_put(state->spi_config->data_io0_pin, false);
|
||||
gpio_put(state->spi_config->data_io1_pin, false);
|
||||
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
|
||||
// Setup DO and DI
|
||||
gpio_init(state->spi_config->data_io0_pin);
|
||||
gpio_init(state->spi_config->data_io1_pin);
|
||||
gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
|
||||
@@ -134,7 +113,6 @@ static void pio_spi_gpio_setup(spi_pio_state_t *state) {
|
||||
gpio_put(state->spi_config->data_io0_pin, false);
|
||||
gpio_put(state->spi_config->data_io1_pin, false);
|
||||
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
|
||||
// Setup DO and DI
|
||||
gpio_init(state->spi_config->data_io0_pin);
|
||||
gpio_init(state->spi_config->data_io1_pin);
|
||||
gpio_init(state->spi_config->data_io2_pin);
|
||||
@@ -149,31 +127,13 @@ static void pio_spi_gpio_setup(spi_pio_state_t *state) {
|
||||
gpio_put(state->spi_config->data_io3_pin, false);
|
||||
#endif
|
||||
|
||||
// Setup CS
|
||||
gpio_init(state->spi_config->cs_pin);
|
||||
gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->cs_pin, true);
|
||||
|
||||
// Setup reset
|
||||
gpio_init(state->spi_config->irq_pin);
|
||||
gpio_set_dir(state->spi_config->irq_pin, GPIO_IN);
|
||||
gpio_set_pulls(state->spi_config->irq_pin, false, false);
|
||||
#else //W55RP20
|
||||
// Setup MOSI, MISO and IRQ
|
||||
gpio_init(state->spi_config->data_out_pin);
|
||||
gpio_set_dir(state->spi_config->data_out_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->data_out_pin, false);
|
||||
|
||||
// Setup CS
|
||||
gpio_init(state->spi_config->cs_pin);
|
||||
gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->cs_pin, true);
|
||||
|
||||
// Setup IRQ
|
||||
gpio_init(state->spi_config->irq_pin);
|
||||
gpio_set_dir(state->spi_config->irq_pin, GPIO_IN);
|
||||
gpio_set_pulls(state->spi_config->irq_pin, false, false);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@@ -220,14 +180,7 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
state->pio_offset = pio_add_program(state->pio, &PIO_PROGRAM_FUNC);
|
||||
|
||||
uint64_t f_sys = clock_get_hz(clk_sys); // Hz
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
const char *wizchip_pio_clock_str = "PIO QSPI CLOCK SPEED";
|
||||
#else
|
||||
const char *wizchip_pio_clock_str = "PIO SPI CLOCK SPEED";
|
||||
#endif
|
||||
|
||||
printf("[%s : %.2f MHz] (sys=%.2f MHz)\r\n\r\n",
|
||||
wizchip_pio_clock_str,
|
||||
printf("[PIO QSPI CLOCK SPEED : %.2f MHz] (sys=%.2f MHz)\r\n\r\n",
|
||||
(double)f_sys / (2.0 * (state->spi_config->clock_div_major +
|
||||
state->spi_config->clock_div_minor / 256.0)) / 1e6,
|
||||
f_sys / 1e6);
|
||||
@@ -244,9 +197,7 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
PADS_BANK0_GPIO0_SLEWFAST_BITS
|
||||
);
|
||||
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
|
||||
printf("\r\n[QSPI SINGLE MODE]\r\n");
|
||||
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 1);
|
||||
sm_config_set_in_pins(&sm_config, state->spi_config->data_io1_pin);
|
||||
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
|
||||
@@ -269,7 +220,6 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
|
||||
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
|
||||
printf("[QSPI DUAL MODE]\r\n\r\n");
|
||||
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 2);
|
||||
sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
|
||||
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
|
||||
@@ -293,7 +243,6 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
|
||||
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
|
||||
printf("\r\n[QSPI QUAD MODE]\r\n");
|
||||
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 4);
|
||||
sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
|
||||
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 4);
|
||||
@@ -322,26 +271,6 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io2_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io3_pin, true);
|
||||
/* @todo: Implement to use. */
|
||||
#endif
|
||||
#else //W55RP20
|
||||
sm_config_set_out_pins(&sm_config, state->spi_config->data_out_pin, 1);
|
||||
sm_config_set_in_pins(&sm_config, state->spi_config->data_in_pin);
|
||||
sm_config_set_set_pins(&sm_config, state->spi_config->data_out_pin, 1);
|
||||
sm_config_set_sideset(&sm_config, 1, false, false);
|
||||
sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
|
||||
|
||||
sm_config_set_in_shift(&sm_config, false, true, 8);
|
||||
sm_config_set_out_shift(&sm_config, false, true, 8);
|
||||
hw_set_bits(&state->pio->input_sync_bypass, 1u << state->spi_config->data_in_pin);
|
||||
pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
|
||||
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
|
||||
gpio_set_function(state->spi_config->data_out_pin, state->pio_func_sel);
|
||||
gpio_set_function(state->spi_config->clock_pin, state->pio_func_sel);
|
||||
|
||||
// Set data pin to pull down and schmitt
|
||||
gpio_set_pulls(state->spi_config->data_in_pin, false, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_in_pin, true);
|
||||
#endif
|
||||
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
|
||||
@@ -392,7 +321,6 @@ static __noinline void ns_delay(uint32_t ns) {
|
||||
|
||||
static void wiznet_spi_pio_frame_start(void) {
|
||||
assert(active_state);
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
|
||||
gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
|
||||
@@ -404,15 +332,9 @@ static void wiznet_spi_pio_frame_start(void) {
|
||||
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io2_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io3_pin, active_state->pio_func_sel);
|
||||
/* @todo: Implement to use. */
|
||||
#endif
|
||||
gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
|
||||
gpio_pull_down(active_state->spi_config->clock_pin);
|
||||
#else
|
||||
gpio_set_function(active_state->spi_config->data_out_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
|
||||
gpio_pull_down(active_state->spi_config->clock_pin);
|
||||
#endif
|
||||
// Pull CS low
|
||||
cs_set(active_state, false);
|
||||
}
|
||||
@@ -427,8 +349,6 @@ static void wiznet_spi_pio_frame_end(void) {
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
// To read a byte we must first have been asked to write a 3 byte spi header
|
||||
void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, uint16_t rx_length) {
|
||||
uint8_t command_buf[8] = {0,};
|
||||
uint16_t command_len = mk_cmd_buf(command_buf, op_code, AddrSel);
|
||||
@@ -578,141 +498,6 @@ void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, u
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
// send tx then receive rx
|
||||
// rx can be null if you just want to send, but tx and tx_length must be valid
|
||||
static bool pio_spi_transfer(spi_pio_state_t *state, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length) {
|
||||
assert(state);
|
||||
if (!state || (tx == NULL)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (rx != NULL && tx != NULL) {
|
||||
assert(tx && tx_length && rx_length);
|
||||
|
||||
pio_sm_set_enabled(state->pio, state->pio_sm, false); // disable sm
|
||||
pio_sm_set_wrap(state->pio, state->pio_sm, state->pio_offset + PIO_OFFSET_WRITE_BITS, state->pio_offset + PIO_OFFSET_READ_BITS_END - 1);
|
||||
pio_sm_clear_fifos(state->pio, state->pio_sm); // clear fifos from previous run
|
||||
pio_sm_set_pindirs_with_mask(state->pio, state->pio_sm, 1u << state->spi_config->data_out_pin, 1u << state->spi_config->data_out_pin);
|
||||
pio_sm_restart(state->pio, state->pio_sm);
|
||||
pio_sm_clkdiv_restart(state->pio, state->pio_sm);
|
||||
pio_sm_put(state->pio, state->pio_sm, tx_length * 8 - 1); // set x
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_out(pio_x, 32));
|
||||
pio_sm_put(state->pio, state->pio_sm, rx_length - 1); // set y
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_out(pio_y, 32));
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_jmp(state->pio_offset)); // setup pc
|
||||
dma_channel_abort(state->dma_out);
|
||||
dma_channel_abort(state->dma_in);
|
||||
|
||||
dma_channel_config out_config = dma_channel_get_default_config(state->dma_out);
|
||||
channel_config_set_dreq(&out_config, pio_get_dreq(state->pio, state->pio_sm, true));
|
||||
channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
|
||||
dma_channel_configure(state->dma_out, &out_config, &state->pio->txf[state->pio_sm], tx, tx_length, true);
|
||||
|
||||
dma_channel_config in_config = dma_channel_get_default_config(state->dma_in);
|
||||
channel_config_set_dreq(&in_config, pio_get_dreq(state->pio, state->pio_sm, false));
|
||||
channel_config_set_write_increment(&in_config, true);
|
||||
channel_config_set_read_increment(&in_config, false);
|
||||
channel_config_set_transfer_data_size(&in_config, DMA_SIZE_8);
|
||||
dma_channel_configure(state->dma_in, &in_config, rx, &state->pio->rxf[state->pio_sm], rx_length, true);
|
||||
|
||||
pio_sm_set_enabled(state->pio, state->pio_sm, true);
|
||||
__compiler_memory_barrier();
|
||||
|
||||
dma_channel_wait_for_finish_blocking(state->dma_out);
|
||||
dma_channel_wait_for_finish_blocking(state->dma_in);
|
||||
|
||||
__compiler_memory_barrier();
|
||||
} else if (tx != NULL) {
|
||||
assert(tx_length);
|
||||
|
||||
pio_sm_set_enabled(state->pio, state->pio_sm, false);
|
||||
pio_sm_set_wrap(state->pio, state->pio_sm, state->pio_offset + PIO_OFFSET_WRITE_BITS, state->pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
|
||||
pio_sm_clear_fifos(state->pio, state->pio_sm);
|
||||
pio_sm_restart(state->pio, state->pio_sm);
|
||||
pio_sm_clkdiv_restart(state->pio, state->pio_sm);
|
||||
pio_sm_put(state->pio, state->pio_sm, tx_length * 8 - 1);
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_out(pio_x, 32));
|
||||
pio_sm_put(state->pio, state->pio_sm, tx_length - 1);
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_out(pio_y, 32));
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 0));
|
||||
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->data_out_pin, 1, true);
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_jmp(state->pio_offset + PIO_OFFSET_WRITE_BITS));
|
||||
dma_channel_abort(state->dma_out);
|
||||
|
||||
dma_channel_config out_config = dma_channel_get_default_config(state->dma_out);
|
||||
channel_config_set_dreq(&out_config, pio_get_dreq(state->pio, state->pio_sm, true));
|
||||
|
||||
channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
|
||||
dma_channel_configure(state->dma_out, &out_config, &state->pio->txf[state->pio_sm], tx, tx_length, true);
|
||||
|
||||
const uint32_t fDebugTxStall = 1u << (PIO_FDEBUG_TXSTALL_LSB + state->pio_sm);
|
||||
state->pio->fdebug = fDebugTxStall;
|
||||
pio_sm_set_enabled(state->pio, state->pio_sm, true);
|
||||
while (!(state->pio->fdebug & fDebugTxStall)) {
|
||||
tight_loop_contents(); // todo timeout
|
||||
}
|
||||
__compiler_memory_barrier();
|
||||
pio_sm_set_enabled(state->pio, state->pio_sm, false);
|
||||
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->data_in_pin, 1, false);
|
||||
} else if (rx != NULL) {
|
||||
panic_unsupported(); // shouldn't be used
|
||||
}
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_mov(pio_pins, pio_null)); // for next time we turn output on
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t wiznet_spi_pio_read_byte(void) {
|
||||
assert(active_state);
|
||||
assert(active_state->spi_header_count == SPI_HEADER_LEN);
|
||||
uint8_t ret;
|
||||
if (!pio_spi_transfer(active_state, active_state->spi_header, active_state->spi_header_count, &ret, 1)) {
|
||||
panic("spi failed read");
|
||||
}
|
||||
active_state->spi_header_count = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
// This is not used when the burst functions are provided
|
||||
static void wiznet_spi_pio_write_byte(uint8_t wb) {
|
||||
panic_unsupported(); // shouldn't be used
|
||||
}
|
||||
|
||||
// To read a buffer we must first have been asked to write a 3 byte spi header
|
||||
static void wiznet_spi_pio_read_buffer(uint8_t* pBuf, uint16_t len) {
|
||||
|
||||
assert(active_state);
|
||||
assert(active_state->spi_header_count == SPI_HEADER_LEN);
|
||||
if (!pio_spi_transfer(active_state, active_state->spi_header, active_state->spi_header_count, pBuf, len)) {
|
||||
panic("spi failed reading buffer");
|
||||
}
|
||||
active_state->spi_header_count = 0;
|
||||
}
|
||||
|
||||
// If we have been asked to write a spi header already, then write it and the rest of the buffer
|
||||
// or else if we've been given enough data for just the spi header, save it until the next call
|
||||
// or we're writing a byte in which case we're given a buffer including the spi header
|
||||
static void wiznet_spi_pio_write_buffer(uint8_t* pBuf, uint16_t len) {
|
||||
assert(active_state);
|
||||
if (len == SPI_HEADER_LEN && active_state->spi_header_count == 0) {
|
||||
memcpy(active_state->spi_header, pBuf, SPI_HEADER_LEN); // expect another call
|
||||
active_state->spi_header_count = SPI_HEADER_LEN;
|
||||
} else {
|
||||
if (active_state->spi_header_count == SPI_HEADER_LEN) {
|
||||
if (!pio_spi_transfer(active_state, active_state->spi_header, SPI_HEADER_LEN, NULL, 0)) {
|
||||
panic("spi failed writing header");
|
||||
}
|
||||
active_state->spi_header_count = 0;
|
||||
}
|
||||
assert(active_state->spi_header_count == 0);
|
||||
if (!pio_spi_transfer(active_state, pBuf, len, NULL, 0)) {
|
||||
panic("spi failed writing buffer");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void wiznet_spi_pio_set_active(wiznet_spi_handle_t handle) {
|
||||
@@ -743,10 +528,6 @@ static wiznet_spi_funcs_t *get_wiznet_spi_pio_impl(void) {
|
||||
.frame_end = wiznet_spi_pio_frame_end,
|
||||
.read_byte = wiznet_spi_pio_read_byte,
|
||||
.write_byte = wiznet_spi_pio_write_byte,
|
||||
#if (_WIZCHIP_ == W5500)
|
||||
.read_buffer = wiznet_spi_pio_read_buffer,
|
||||
.write_buffer = wiznet_spi_pio_write_buffer,
|
||||
#endif
|
||||
.reset = wizchip_spi_pio_reset,
|
||||
};
|
||||
return &funcs;
|
||||
@@ -1,16 +1,10 @@
|
||||
/*
|
||||
Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _WIZNET_SPI_FUNCS_H_
|
||||
#define _WIZNET_SPI_FUNCS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct wiznet_spi_funcs** wiznet_spi_handle_t;
|
||||
#if (_WIZCHIP_ == W6300)
|
||||
|
||||
typedef struct wiznet_spi_config {
|
||||
uint16_t clock_div_major;
|
||||
uint8_t clock_div_minor;
|
||||
@@ -36,33 +30,6 @@ typedef struct wiznet_spi_funcs {
|
||||
void (*write_buffer)(uint8_t *pBuf, uint16_t len);
|
||||
void (*reset)(wiznet_spi_handle_t funcs);
|
||||
} wiznet_spi_funcs_t;
|
||||
#else
|
||||
typedef struct wiznet_spi_config {
|
||||
uint8_t data_in_pin;
|
||||
uint8_t data_out_pin;
|
||||
uint8_t cs_pin;
|
||||
uint8_t clock_pin;
|
||||
uint8_t irq_pin;
|
||||
uint8_t reset_pin;
|
||||
uint16_t clock_div_major;
|
||||
uint8_t clock_div_minor;
|
||||
uint8_t spi_hw_instance;
|
||||
} wiznet_spi_config_t;
|
||||
|
||||
typedef struct wiznet_spi_funcs {
|
||||
void (*close)(wiznet_spi_handle_t funcs);
|
||||
void (*set_active)(wiznet_spi_handle_t funcs);
|
||||
void (*set_inactive)(void);
|
||||
void (*frame_start)(void);
|
||||
void (*frame_end)(void);
|
||||
uint8_t (*read_byte)(void);
|
||||
void (*write_byte)(uint8_t tx_data);
|
||||
void (*read_buffer)(uint8_t *pBuf, uint16_t len);
|
||||
void (*write_buffer)(uint8_t *pBuf, uint16_t len);
|
||||
void (*reset)(wiznet_spi_handle_t funcs);
|
||||
} wiznet_spi_funcs_t;
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -71,7 +38,6 @@ typedef struct wiznet_spi_funcs {
|
||||
|
||||
#include "wizchip_spi.h"
|
||||
|
||||
|
||||
wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,9 +1,3 @@
|
||||
;
|
||||
; Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
|
||||
;
|
||||
; SPDX-License-Identifier: BSD-3-Clause
|
||||
;
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Normal SPI for W55RP20
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
@@ -0,0 +1,76 @@
|
||||
#include <stdio.h>
|
||||
|
||||
#include "port_common.h"
|
||||
#include "wizchip_conf.h"
|
||||
#include "wizchip_spi.h"
|
||||
#include "wizchip_qspi_pio.h"
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/binary_info.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "hardware/dma.h"
|
||||
|
||||
static critical_section_t g_wizchip_cri_sec;
|
||||
|
||||
wiznet_spi_config_t g_spi_config = {
|
||||
.clock_div_major = WIZNET_SPI_CLKDIV_MAJOR_DEFAULT,
|
||||
.clock_div_minor = WIZNET_SPI_CLKDIV_MINOR_DEFAULT,
|
||||
.clock_pin = PIO_SPI_SCK_PIN,
|
||||
.data_io0_pin = PIO_SPI_DATA_IO0_PIN,
|
||||
.data_io1_pin = PIO_SPI_DATA_IO1_PIN,
|
||||
.data_io2_pin = PIO_SPI_DATA_IO2_PIN,
|
||||
.data_io3_pin = PIO_SPI_DATA_IO3_PIN,
|
||||
.cs_pin = PIN_CS,
|
||||
.reset_pin = PIN_RST,
|
||||
.irq_pin = PIN_INT,
|
||||
};
|
||||
|
||||
wiznet_spi_handle_t spi_handle;
|
||||
|
||||
void wizchip_reset() {
|
||||
gpio_init(PIN_RST);
|
||||
gpio_set_dir(PIN_RST, GPIO_OUT);
|
||||
gpio_put(PIN_RST, 0);
|
||||
sleep_ms(100);
|
||||
gpio_put(PIN_RST, 1);
|
||||
sleep_ms(100);
|
||||
}
|
||||
|
||||
static void wizchip_critical_section_lock(void) {
|
||||
critical_section_enter_blocking(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
static void wizchip_critical_section_unlock(void) {
|
||||
critical_section_exit(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
void wizchip_spi_initialize(void) {
|
||||
spi_handle = wiznet_spi_pio_open(&g_spi_config);
|
||||
(*spi_handle)->set_active(spi_handle);
|
||||
}
|
||||
|
||||
void wizchip_cris_initialize(void) {
|
||||
critical_section_init(&g_wizchip_cri_sec);
|
||||
reg_wizchip_cris_cbfunc(wizchip_critical_section_lock, wizchip_critical_section_unlock);
|
||||
}
|
||||
|
||||
void wizchip_initialize(void) {
|
||||
(*spi_handle)->frame_end();
|
||||
reg_wizchip_qspi_cbfunc((*spi_handle)->read_byte, (*spi_handle)->write_byte);
|
||||
reg_wizchip_cs_cbfunc((*spi_handle)->frame_start, (*spi_handle)->frame_end);
|
||||
|
||||
uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}};
|
||||
ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize);
|
||||
}
|
||||
|
||||
void wizchip_check(void) {
|
||||
if (getCIDR() != 0x6300) {
|
||||
printf("W6300 ACCESS ERR: CIDR = 0x%04x\n", getCIDR());
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
void network_initialize(wiz_NetInfo net_info) {
|
||||
uint8_t syslock = SYS_NET_LOCK;
|
||||
ctlwizchip(CW_SYS_UNLOCK, &syslock);
|
||||
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
#ifndef _WIZCHIP_SPI_H_
|
||||
#define _WIZCHIP_SPI_H_
|
||||
|
||||
#include "board_list.h"
|
||||
|
||||
#define USE_PIO
|
||||
#define WIZNET_SPI_CLKDIV_MAJOR_DEFAULT 2
|
||||
#define WIZNET_SPI_CLKDIV_MINOR_DEFAULT 0
|
||||
|
||||
#define PIN_INT 15
|
||||
#define PIN_CS 16
|
||||
#define PIO_SPI_SCK_PIN 17
|
||||
#define PIO_SPI_DATA_IO0_PIN 18
|
||||
#define PIO_SPI_DATA_IO1_PIN 19
|
||||
#define PIO_SPI_DATA_IO2_PIN 20
|
||||
#define PIO_SPI_DATA_IO3_PIN 21
|
||||
#define PIN_RST 22
|
||||
|
||||
void wizchip_spi_initialize(void);
|
||||
void wizchip_cris_initialize(void);
|
||||
void wizchip_reset(void);
|
||||
void wizchip_initialize(void);
|
||||
void wizchip_check(void);
|
||||
void network_initialize(wiz_NetInfo net_info);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user