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BCM84891L MDIO command handler — transcription

Full visual transcription (tables intact) of an excerpt of the Broadcom datasheet 84891L-DS101 (rev July 9, 2019), file BCM84891L-MDIO Command Descriptions-.pdf. The excerpt contains the cover, the table of contents, and datasheet pages 41–59: §1.24 MDIO Command Handler Function, §1.25 Command Descriptions (all 45 commands), and the start of §1.26 General-Purpose LED Programmability (the excerpt ends there).

Cabletest field notes discovered on hardware are called out inline as Field note and are distinct from the datasheet text.

Device headline features (cover page): single-chip transceiver-MAC to magnetics for 10GBASE-T (802.3an) / 5GBASE-T / 2.5GBASE-T (802.3bz) / 1000BASE-T (802.3ab) / 100BASE-TX (802.3u) on Cat 6/6A/7 (5G/2.5G/1G/100M also on Cat 5e); IEEE 802.3z, 802.3az; XFI/10GBASE-KR, USXGMII, 5000BASE-R/X, 2500BASE-R/X, 1000BASE-X (SGMII) MAC interface; IEEE 1588-2008 v2-compliant; IEEE fast retrain and link monitoring; EEE with AutogrEEEn; trace-matched output impedance; line-side loopback; low EMI; enhanced cable diagnostics; jumbo packets up to 18 KB; detection/correction of pair swaps (MDI crossover), pair skew, pair polarity; autonegotiation with next-page; JTAG/AC-JTAG boundary scan; 0.8 V CMOS core; 1.2/1.8/2.5/3.3 V MDIO I/O; 8 mm × 8 mm BGA.

Chapters the TOC lists but the excerpt omits

Field note (our analysis, not datasheet text): the excerpt's own table of contents names chapters absent from these pages — gaps to source elsewhere.

  • §1.17 EEE / AutogrEEEn narrative (enabling/disabling AutogrEEEn, monitoring EEE readiness §1.17.5, fast-retrain modes §1.17.6: IEEE FR, Negotiated FR (NFR), BCM-proprietary FR)
  • §1.18 Jumbo Packets, §1.19 HiGig2 Messages Support
  • §1.20 Loopback Operation — per-speed PCS/PMA system loopbacks (§1.20.1.1–1.20.1.5) and §1.20.2 Copper Line Loopback at PMD/PCS of XFI/10GBASE-KR
  • §1.21 Management Interface, §1.22 TRD (MDI) Interface Pair Swapping, §1.23 SPI Interface (modes, functional description, READ, memory power-up sequence)
  • §1.26 remainder (LED source table / register-bit detail), §1.27 Power Supplies, §1.28 Reset
  • Chapter 2: Register Summary (datasheet p62+)
  • Not in this TOC at all: the ECD (cable-diagnostics) register chapter and the 1588 operation chapter.

§1.24 MDIO Command Handler Function

The MDIO Command Handler is a handshake process to provision and monitor features and guarantee the feature is set properly. The command CODE is written to the Command register CMD (0x1E.0x4005). During the 2-second training phase the status returns CMD_SYSTEM_BUSY; wait up to 2 seconds for the command to execute.

Table 5: Features/Commands Using MDIO Command Handler Process

Feature/Command Name Description Command Code
CMD_GET_PAIR_SWAP — 0x8000
CMD_SET_PAIR_SWAP — 0x8001
Reserved — 0x8002
Reserved — 0x8003
CMD_GET_1588_ENABLE — 0x8004
CMD_SET_1588_ENABLE — 0x8005
GET_LIMITED_REACH_MODE_ENABLE Gets limited reach mode setting. 0x8006
SET_LIMITED_REACH_MODE_ENABLE Enables or disables limited reach mode setting. 0x8007
CMD_GET_EEE_MODE — 0x8008
CMD_SET_EEE_MODE — 0x8009
CMD_GET_EMI_MODE_ENABLE — 0x800A
CMD_SET_EMI_MODE_ENABLE — 0x800B
CMD_GET_SUB_LF_RF_STATUS — 0x800D
GET_KR_MODE_ENABLE Gets KR mode setting. 0x800E
SET_KR_MODE_ENABLE Enables or disables KR mode setting. 0x800F
CMD_CLEAR_SUB_LF_RF — 0x8010
CMD_SET_SUB_LF_RF — 0x8011
GET_SYNC_E_ENABLE Get SyncE enable status 0x8012
SET_SYNC_E_ENABLE Set SyncE enable 0x8013
GET_XFI_2P5G_5G_MODE — 0x8016
SET_XFI_2P5G_5G_MODE — 0x8017
SET_EEE_STATISTICS — 0x801A
GET_EEE_STATISTICS — 0x801B
GET_JUMBO_PACKET — 0x801D
SET_JUMBO_PACKET — 0x801C
GET_PAUSE_FRAME_MODE — 0x801F
SET_PAUSE_FRAME_MODE — 0x8020
GET_LED_TYPE — 0x8021
SET_LED_TYPE — 0x8022
GET_WAP_MODE_FRAME_TYPE — 0x8023
SET_WAP_MODE_FRAME_TYPE — 0x8024
SET_USXGMII — 0x8026
GET_USXGMII — 0x8027
GET_XFI_TX_FILTERS — 0x802B
SET_XFI_TX_FILTERS — 0x802C
GET_XFI_POLARITY — 0x802D
SET_XFI_POLARITY — 0x802E
GET_CURRENT_VOLTAGE — 0x802F
CMD_GET_SNR — 0x8030
CMD_GET_CURRENT_TEMP — 0x8031
CMD_SET_UPPER_TEMP_WARNING_LEVEL — 0x8032
CMD_GET_UPPER_TEMP_WARNING_LEVEL — 0x8033
CMD_SET_LOWER_TEMP_WARNING_LEVEL — 0x8034
CMD_GET_LOWER_TEMP_WARNING_LEVEL — 0x8035
SET_WOL_ENABLE Enable/disable wake-on-LAN 0x805A
GET_WOL_ENABLE Get wake-on-LAN settings 0x805B

To execute a feature, write the associated code (command CODE) in the CMD register.

Table 6: MDIO Command Handler Register Set

Register Name Description Address
CMD Command 0x1E.0x4005
STATUS Status of command 0x1E.0x4037
DATA1_REG Data 1 register 0x1E.0x4038
DATA2_REG Data 2 register 0x1E.0x4039
DATA3_REG Data 3 register 0x1E.0x403A
DATA4_REG Data 4 register 0x1E.0x403B
DATA5_REG Data 5 register 0x1E.0x403C

The STATUS register is a special bidirectional register that reports the status and can be written by the user.

Table 7: STATUS Codes

STATUS Code Name Set by Description Code Value
CMD_RECEIVED FW A command has been received. 0x0001
CMD_IN_PROGRESS FW A command is being serviced. 0x0002
CMD_COMPLETE_PASS / CMD_OPEN_FOR_CMDS FW Last command has been executed successfully. 0x0004
CMD_COMPLETE_ERROR / CMD_OPEN_FOR_CMDS FW Execution of the last command produced an error. 0x0008
CMD_SYSTEM_BUSY FW System is not ready to accept commands. 0xBBBB

§1.24.1 Theory of Operation

After boot, firmware initializes STATUS to CMD_COMPLETE_PASS/CMD_OPEN_FOR_CMDS and CMD to 0x0 (no-op). The user polls STATUS to check handler availability. If STATUS is CMD_IN_PROGRESS or SYSTEM_BUSY, wait and check again. Otherwise the user writes the command to CMD; if CMD bit 15 is written as 1, an interrupt is generated and firmware sets STATUS to CMD_RECEIVED and sends a message to the Service thread to execute the command.

The Service thread calls the MDIO Command Handler, which uses the command value as an index into a command array and returns a function pointer that executes the command. Each command function sets STATUS to CMD_IN_PROGRESS, processes, then returns CMD_COMPLETE_PASS/CMD_OPEN_FOR_CMDS or CMD_COMPLETE_ERROR/CMD_OPEN_FOR_CMDS so the user can poll and read the register results.

§1.24.2 Command Procedure

  1. Poll STATUS until the previous command is neither CMD_IN_PROGRESS nor SYSTEM_BUSY.
  2. If parameters are required, write them to the DATA registers (see §1.25).
  3. When firmware is ready, write the command code/value from Table 5 to the CMD register.
  4. Poll STATUS until CMD_COMPLETE_PASS/CMD_OPEN_FOR_CMDS or CMD_COMPLETE_ERROR/CMD_OPEN_FOR_CMDS.
  5. Read the specified DATA registers for saved results, if applicable.
  6. For provisioning features that alter port configuration, restart autonegotiation to reestablish link with the new parameters (most provisioning processes require this step).

NOTE: The recommended STATUS polling period is 100 ms. During the 10GBASE-T training phase the handler status register does not change for up to two seconds; avoid issuing commands during training or start polling only after link is up.

§1.24.3 Provisioning and Monitoring Sequences (Figure 15)

Provisioning flow: Start → Read Status Register → is Status = CMD_IN_PROGRESS || CMD_SYSTEM_BUSY? If Yes, loop back to read again. If No → Write Data Register → Write Command Register → Read Status Register → is Status = CMD_COMPLETE_PASS || CMD_COMPLETE_ERROR? If No, loop back to read again. If Yes → End.

Handler field notes (hardware-verified)

  • The handler does not clear DATA registers it does not use — stale values persist across commands. Write every parameter register explicitly before any SET, and see CMD_GET_SNR for a GET that must be issued with no DATA1 write.

§1.25 Command Descriptions

§1.25.1.1 CMD_GET_PAIR_SWAP (0x8000)

  • Description: Gets pair swap values.
  • Input Parameters: None.
  • Return Results: DATA1_REG = Forced/requested current swap pair value. DATA2_REG = Current swap pair value.

§1.25.1.2 CMD_SET_PAIR_SWAP (0x8001)

  • Description: Sets pair swap values.
  • Input Parameters: DATA2_REG = Swap pair value to be forced.
  • Return Results: None.
  • NOTE: CMD_SET_PAIR_SWAP requires autonegotiation to take place in order to take effect.

§1.25.1.3 Pair Swap Values (Table 8)

Bits Description
[15:8] Reserved.
[7:6] PAIR_D_SEL: 00 = Pair A, 01 = Pair B, 10 = Pair C, 11 = Pair D
[5:4] PAIR_C_SEL: 00 = Pair A, 01 = Pair B, 10 = Pair C, 11 = Pair D
[3:2] PAIR_B_SEL: 00 = Pair A, 01 = Pair B, 10 = Pair C, 11 = Pair D
[1:0] PAIR_A_SEL: 00 = Pair A, 01 = Pair B, 10 = Pair C, 11 = Pair D

Field note: on the FS, reading 0x8000 returns DATA2 = 0x00E4 = identity map (A/B/C/D straight through), which verifies MDI wiring.

§1.25.1.4 CMD_GET_1588_ENABLE (0x8004)

  • Description: Returns current value set for internal variable used to enable/disable IEEE 1588 functionality.
  • Input Parameters: None.
  • Return Results: DATA1: 0 = IEEE 1588 is disabled, 1 = IEEE 1588 is enabled. DATA2 to DATA5: Not used.

§1.25.1.5 CMD_SET_1588_ENABLE (0x8005)

  • Description: Sets internal variable used to enable/disable IEEE 1588 functionality. Setting to 1 enables IEEE 1588, 0 disables it. Enable or disable prior to link up. If changing while the link is already up, bring the link down and back up using an AUTONEG restart or similar mechanism.
  • Input Parameters: DATA1: 0 = Disable IEEE 1588, 1 = Enable IEEE 1588. DATA2 to DATA5: Not used.
  • Return Results: None.
  • NOTE: CMD_SET_1588_ENABLE requires autonegotiation to take place to take effect.

§1.25.1.6 GET_LIMITED_REACH_MODE_ENABLE (0x8006)

  • Description: Returns current value set for internal variable used to enable/disable limited reach mode functionality.
  • Input Parameters: None.
  • Return Results:
    • DATA1: 0 = Limited reach mode is disabled, 1 = enabled.
    • DATA2 (only valid when DATA1 = 1): 0 = Dynamically switch to LR power saving mode level 2 based on cable length; 1 = Always forced to LR power saving mode level 1 (most power saving); 2 = Always forced to level 2 (less saving); 3 = Always forced to level 3 (least saving).
    • DATA3 (valid only when DATA1 = 1): 0 = Currently not linked in limited reach mode, 1 = Currently linked in limited reach mode.
    • DATA4 to DATA5: Not used.

Field note: DATA3 = "currently linked in LR mode" is the only handler-visible trace of the DSP's internal cable-length estimate.

§1.25.1.7 SET_LIMITED_REACH_MODE_ENABLE (0x8007)

  • Description: Enables/disables limited reach mode functionality.
  • Input Parameters:
    • DATA1: 0 = Exit limited reach mode, 1 = Enter limited reach mode.
    • DATA2 (only valid when DATA1 = 1): 0 = Dynamically switch to LR power saving mode level 2 based on cable length; 1 = level 1 (most saving); 2 = level 2 (less saving); 3 = level 3 (least saving).
    • DATA3 to DATA5: Not used.
  • Return Results: None.

§1.25.1.8 CMD_GET_EEE_MODE (0x8008)

  • Description: Gets AutogrEEEn parameters.
  • Input Parameters: None.
  • Return Results:
Register Field 5G 2.5G 1G/100M 10G
DATA1_REG Bits 7:6 5:4 3:2 1:0
EEE Disabled 0 0 0 0
Native EEE 1 1 1 1
AutogrEEEn Fixed Latency 2 2 2 2
AutogrEEEn Variable Latency 3 3 N/A 3
DATA2_REG AutogrEEEn High Threshold 0 0 N/A 0
DATA3_REG AutogrEEEn Low Threshold 0x7A12 0x7A12 N/A 0x7A12
DATA4_REG AutogrEEEn Latency 0x480 0x480 N/A 0x480
DATA5_REG Reserved 0 0 0 0
  • NOTE:
    • DATA1_REG bit[11:10] defines how bit[3:2] works: 0 = bit[3:2] for 1G/100TX EEE; 1 = bit[3:2] for 100TX EEE only; 2 = bit[3:2] for 1G EEE only; 3 = bit[3:2] for 1G/100TX EEE.
    • Although the EEE modes can differ between speeds, the AutogrEEEn parameters for 2.5G/5G/10G in DATA2_REG–DATA4_REG are shared. The 1G/100M AutogrEEEn parameters are not programmable and are unaffected by DATA2_REG–DATA4_REG. DATA1_REG[15:8] = Reserved.
    • Example: When DATA1_REG is 0x00B1, 5G EEE is fixed latency, 2.5G EEE is variable latency, 1G/100M does not advertise EEE, and 10G is native EEE mode. If the data rate is 10G, DATA2_REG–DATA4_REG are ignored. If 5G, DATA4_REG is ignored. If 2.5G or 5G, the AutogrEEEn threshold applies.

§1.25.1.9 CMD_SET_EEE_MODE (0x8009)

  • Description: Configures IEEE-EEE and AutogrEEEn.
  • Input Parameters: Same DATA1–DATA5 layout as CMD_GET_EEE_MODE (Table above): DATA1_REG per-speed mode fields (5G [7:6], 2.5G [5:4], 1G/100M [3:2], 10G [1:0]; 0 = EEE disabled, 1 = native EEE, 2 = AutogrEEEn fixed latency, 3 = AutogrEEEn variable latency); DATA2_REG = AutogrEEEn high threshold; DATA3_REG = low threshold (default 0x7A12); DATA4_REG = AutogrEEEn latency (default 0x480); DATA5_REG = Reserved. Same NOTE and example as GET.
  • Return Results: None.
  • NOTE: CMD_SET_EEE_MODE requires autonegotiation to take place to take effect.

§1.25.1.10 CMD_GET_EMI_MODE_ENABLE (0x800A)

  • Description: Gets SW Fast Retrain current enable status.
  • Input Parameters: None.
  • Return Results:
    • DATA1: 10G fast retrain enable — 0 = disabled, 1 = enabled.
    • DATA2: 5G fast retrain enable — 0 = disabled, 1 = enabled.
    • DATA3: 2.5G fast retrain enable — 0 = disabled, 1 = enabled.

§1.25.1.11 CMD_SET_EMI_MODE_ENABLE (0x800B)

  • Description: (titled EMI; body reads) Gets/sets SW Fast Retrain enable status.
  • Input Parameters:
    • DATA1: 10G fast retrain — 0 = Disable, 1 = Enable.
    • DATA2: 5G fast retrain — 0 = Disable, 1 = Enable.
    • DATA3: 2.5G fast retrain — 0 = Disable, 1 = Enable.
  • Return Results: None.
  • NOTE: CMD_SET_EMI_MODE_ENABLE requires autonegotiation to take place to take effect.

§1.25.1.12 CMD_GET_SUB_LF_RF_STATUS (0x800D)

  • Description: Gets current status on the substitution of FAULTS with IDLE going to the line direction.
  • Input Parameters: None.
  • Return Results: Status. DATA1: 0 = Copper TX direction LF/RF is passing through, 1 = Copper TX direction LF/RF is replaced with IDLE. DATA2 to DATA5: Not used.

§1.25.1.13 CMD_CLEAR_SUB_LF_RF (0x8010)

  • Description: Disables substitution of FAULTS with IDLE going to the line direction.
  • Input Parameters: None.
  • Return Results: None.

§1.25.1.14 CMD_SET_SUB_LF_RF (0x8011)

  • Description: Enables substitution of FAULTS with IDLE going to the line direction.
  • Input Parameters: None.
  • Return Results: None.

§1.25.1.15 GET_KR_MODE_ENABLE (0x800E)

  • Description: Gets KR mode status setting (enable/disable).
  • Input Parameters: None.
  • Return Results: DATA1: 0 = BCM84891L KR mode is disabled, 1 = enabled. DATA2 to 5: Reserved.

§1.25.1.16 SET_KR_MODE_ENABLE (0x800F)

  • Description: Sets KR mode status setting (enable/disable).
  • Input Parameters: DATA1: 0 = BCM84891L KR mode is disabled, 1 = enabled. DATA2 to 5: Reserved.
  • Return Results: None.

§1.25.1.17 GET_SYNC_E_ENABLE (0x8012)

  • Description: Get SyncE enable setting.
  • Input Parameters: None.
  • Return Results:
    • DATA1: SyncE enable — 0 = disabled, 1 = enabled.
    • DATA2: M0 mux select — 0 = P0 10G clock/lock on M0; 1 = P1 10G/1G; 2 = P2 10G/1G; 3 = P3 10G/1G; 8 = P0 1G clock/lock on M0.
    • DATA3: M1 mux select — 0 = P0 10G clock/lock on M1; 1 = P1 10G/1G; 2 = P2 10G/1G; 3 = P3 10G/1G; 8 = P0 1G clock/lock on M1.
    • DATA4: FW Control SyncE Configuration — 0 = User control, 1 = FW control.
    • DATA5[0]: M0 mux SYNCE_OEN. DATA5[1]: M1 mux SYNCE_OEN — 0 = Output enabled, 1 = Output disable. DATA5[15:2]: Reserved.

§1.25.1.18 SET_SYNC_E_ENABLE (0x8013)

  • Description: Set SyncE enable setting.
  • Input Parameters:
    • DATA1: SyncE enable — 0 = disabled, 1 = enabled.
    • DATA2: M0 mux select — 0 = P0 10G clock/lock on M0 (default); 1 = P1 10G/1G; 2 = P2 10G/1G; 3 = P3 10G/1G; 8 = P0 1G on M0.
    • DATA3: M1 mux select — 0 = P0 10G clock/lock on M1 (default); 1 = P1 10G/1G; 2 = P2 10G/1G; 3 = P3 10G/1G; 8 = P0 1G on M1.
    • DATA4: FW Control SyncE Configuration — 0 = User control (default), 1 = Firmware control.
    • DATA5[0]: M0 mux SYNCE_OEN. DATA5[1]: M1 mux SYNCE_OEN — 0 = Output enabled, 1 = Output disable. DATA5[15:2]: Reserved.
  • Return Results: None.

§1.25.1.19 GET_XFI_TX_FILTERS (0x802B)

  • Description: Gets current XFI TX filter taps.
  • Input Parameters: None.
  • Return Results:
    • DATA2: Bit[0:7] = Pre tap, Bit[8:15] = Main tap.
    • DATA3: Bit[0:7] = Post1 tap, Bit[8:15] = Post2 tap.
    • DATA4: Bit[8:15] = TX HPF.
    • DATA5: Reserved.
  • NOTE: The current link speed is the filter for that speed. If a link is down, the filter tap is invalid.

§1.25.1.20 SET_XFI_TX_FILTERS (0x802C)

  • Description: Sets XFI TX filter taps.
  • Input Parameters:
    • DATA1: Bit[0:7] = Reserved; Bit[8:15] = Speed — 0 = Backward-compatible 10G, 1 = 100BT, 2 = 1G, 3 = 10G, 4 = 2.5G, 5 = 5G.
    • DATA2: Bit[0:7] = Pre tap, Bit[8:15] = Main tap.
    • DATA3: Bit[0:7] = Post1 tap, Bit[8:15] = Post2 tap.
    • DATA4: Bit[8:15] = TX HPF.
    • DATA5: Reserved.
  • Return Results: None.
  • NOTE: Speed = 0 means 10G; this is for backward-compatibility.

§1.25.1.21 GET_XFI_POLARITY (0x802D)

  • Description: Gets XFI polarity.
  • Input Parameters: None.
  • Return Results: DATA2: TX polarity. DATA3: RX polarity.

§1.25.1.22 SET_XFI_POLARITY (0x802E)

  • Description: Sets XFI polarity.
  • Input Parameters: DATA2: TX polarity. DATA3: RX polarity.
  • Return Results: None.

§1.25.1.23 GET_CURRENT_VOLTAGE (0x802F)

  • Description: Gets current voltage.
  • Input Parameters: None.
  • Return Results: DATA1 = For 0.8V measurement. DATA2 = For 0.8V measurement. DATA3 = For 1.88V measurement. DATA4 = Reserved.

Field note: observed in tenths of mV — the 0.8 V rails and a 1.88 V rail.

§1.25.1.24 CMD_GET_SNR (0x8030)

  • Description: Gets SNR value.
  • Input Parameters: DATA1: 0 = Do not display SNR in IEEE registers, 1 = Display SNR in IEEE registers.
  • Return Results: DATA2/10 = SNR for Channel A in dB; DATA3/10 = Channel B; DATA4/10 = Channel C; DATA5/10 = Channel D.

Field note (hardware-verified): on this ODM firmware, write nothing to DATA1 — writing the display flag (either value) makes the firmware return zeros, and the IEEE registers 1.133–1.140 never populate (they read a constant 0x8080) regardless. Bare invocation returns live per-pair SNR (~27–32 dB on a bench cable, 0.1–0.4 dB jitter per read). Values are absolute receiver SNR, not IEEE SNR margin, so there is no documented green/orange/red threshold — the 10GBASE-T operating point must be established empirically (the graded-noise correlation run) rather than assumed.

§1.25.1.25 CMD_GET_CURRENT_TEMP (0x8031)

  • Description: Returns the internally derived temperature of the die. DATA1_REG returns the temperature, when supported.
  • Input Parameters: None.
  • Return Results: DATA1_REG = Temperature value.

Field note: observed ~68–70 °C on the bench. See also the firmware-reliability caveat — temperature-like values can leak into other commands' DATA1.

§1.25.1.26 CMD_SET_UPPER_TEMP_WARNING_LEVEL (0x8032)

  • Description: Sets the upper-bound of the temperature warning to the value in DATA1_REG.
  • Input Parameters: DATA1: Upper temperature limit in °C (2s compliment). DATA2: Upper temperature limit margin in °C (positive number). DATA3: Enable upper temperature warning — 0 = Disable, 1 = Enable.
  • Return Results: None.

§1.25.1.27 CMD_GET_UPPER_TEMP_WARNING_LEVEL (0x8033)

  • Description: Gets the upper-bound of the temperature warning and saves the value to DATA1_REG.
  • Input Parameters: None.
  • Return Results: DATA1: Upper temperature limit in °C (2s compliment). DATA2: Upper temperature limit margin in °C (positive number). DATA3: Enable upper temperature warning — 0 = Disable, 1 = Enable.

§1.25.1.28 CMD_SET_LOWER_TEMP_WARNING_LEVEL (0x8034)

  • Description: Sets the lower-bound of the temperature warning and saves the value to DATA1_REG.
  • Input Parameters: DATA1: Lower temperature limit in °C (2s compliment). DATA2: Lower temperature limit margin in °C (positive number). DATA3: Enable upper temperature warning — 0 = Disable, 1 = Enable.
  • Return Results: None.

§1.25.1.29 CMD_GET_LOWER_TEMP_WARNING_LEVEL (0x8035)

  • Description: Gets the lower bound of the temperature warning to the value in DATA1_REG.
  • Input Parameters: None.
  • Return Results: DATA1: Lower temperature limit in °C (2s compliment). DATA2: Lower temperature limit margin in °C (positive number). DATA3: Enable upper temperature warning — 0 = Disable, 1 = Enable.

§1.25.1.30 GET_WAP_MODE_FRAME_TYPE (0x8023)

  • Description: —
  • Input Parameters: None.
  • Return Results:
    • DATA1: 0 = Reserved; 1 = Priority protocol is IEEE 802.3bz.
    • DATA2: Current link frame type — 0 = Reserved, 1 = IEEE 802.3bz, 2 = NBASE-T, 3 = Reserved.
    • DATA3 to DATA5: Reserved.

§1.25.1.31 SET_WAP_MODE_FRAME_TYPE (0x8024)

  • Description: —
  • Input Parameters: DATA1: Frame type priority — 0 = Reserved, 1 = IEEE 802.3bz. DATA2 to DATA5: Reserved.
  • Return Results: None.

§1.25.1.32 GET_XFI_2P5G_5G_MODE (0x8016)

  • Description: —
  • Input Parameters: None.
  • Return Results:
    • DATA1: 0 = 10G Idle Stuffing mode for 2.5G; 1 = 2500BASE-X_5000BASE-X mode for 2.5G; 2 = 2500BASE-R_5000BASE-R mode for 2.5G.
    • DATA2: 0 = 10G Idle Stuffing mode for 5G; 1 = 2500BASE-X_5000BASE-X mode for 5G; 2 = 2500BASE-R_5000BASE-R mode for 5G.
    • DATA3 to DATA5: Not used.

§1.25.1.33 SET_XFI_2P5G_5G_MODE (0x8017)

  • Description: —
  • Input Parameters:
    • DATA1: 0 = 10G Idle Stuffing mode for 2.5G; 1 = 2500BASE-X_5000BASE-X mode for 2.5G; 2 = 2500BASE-R_5000BASE-R mode for 2.5G.
    • DATA2: 0 = 10G Idle Stuffing mode for 5G; 1 = 2500BASE-X_5000BASE-X mode for 5G; 2 = 2500BASE-R_5000BASE-R mode for 5G.
    • DATA3 to DATA5: Not used.
  • Return Results: None.
  • NOTE: KR mode is not supported when 2500X or 5000X mode is enabled.

§1.25.1.34 SET_EEE_STATISTICS (0x801A)

  • Description: Enable EEE statistics.
  • Input Parameters: None.
  • Return Results: None.
  • NOTE: This command must be issued after the link is up.

§1.25.1.35 GET_EEE_STATISTICS (0x801B)

  • Description: —
  • Input Parameters: Counter selection — 0 = Select event counters, 1 = Select time duration.
  • Return Results: DATA2: TX (LOC) counters/time lower 16 bits. DATA3: TX (LOC) counters/time upper 16 bits. DATA4: RX (REM) counters/time lower 16 bits. DATA5: RX (REM) counters/time upper 16 bits.
  • NOTE: PHY selects 10G or 1G based on current link speed.

§1.25.1.36 GET_JUMBO_PACKET (0x801D)

  • Description: Gets jumbo packet status setting (enable/disable).
  • Input Parameters: None.
  • Return Results: DATA1: Current jumbo packet enable status — 0 = disabled, 1 = enabled. DATA2: Jumbo packet size option — 0 = 10K packet, 1 = 18k packet, 2 = 9k packet. DATA3 to DATA5: Not used.

§1.25.1.37 SET_JUMBO_PACKET (0x801C)

  • Description: Sets jumbo packet status setting (enable/disable).
  • Input Parameters: DATA1: Enable or disable jumbo packet — 0 = Disable, 1 = Enable. DATA2: Jumbo packet size option — 0 = 10K packet, 1 = 18k packet, 2 = 9k packet. DATA3 to DATA5: Not used.
  • Return Results: None.

§1.25.1.38 GET_PAUSE_FRAME_MODE (0x801F)

  • Description: Gets the pause frame mode status (enable/disable).
  • Input Parameters: None.
  • Return Results: DATA1: Pause frame enable status — 0 = No pause frame, 1 = Pause frame is enabled. DATA2 to 5: Reserved.
  • NOTE: This is only valid for 2.5/5G Idle Stuffing mode in 10G XFI WAP mode.

§1.25.1.39 SET_PAUSE_FRAME_MODE (0x8020)

  • Description: Sets the pause frame mode status (enable/disable).
  • Input Parameters: DATA1: Pause frame enable status — 0 = No pause frame, 1 = Pause frame is enabled.
  • Return Results: None.
  • NOTE: This is only valid for 2.5/5G Idle Stuffing mode in 10G XFI WAP mode.

§1.25.1.40 GET_LED_TYPE (0x8021)

  • Description: Gets the LED control mode status (enable/disable).
  • Input Parameters: None.
  • Return Results: DATA1: Current LED type — 0 = Firmware control, 1 = User control. DATA2 to DATA5: Reserved.

§1.25.1.41 SET_LED_TYPE (0x8022)

  • Description: Sets the LED control mode status (enable/disable).
  • Input Parameters: DATA1: Current LED type — 0 = FW control, 1 = User control. DATA2 to DATA5: Reserved.
  • Return Results: None.

§1.25.1.42 GET_USXGMII (0x8027)

  • Description: Gets the USXGMII mode and AUTONEG function (enable/disable).
  • Input Parameters: None.
  • Return Results:
    • DATA1: USXGMII enable status — 0 = disabled, 1 = enabled.
    • DATA2: USXGMII autonegotiation enable status (only valid if USXGMII is enabled) — 0 = disabled, 1 = enabled.
    • DATA3: [0:2] = single_max_speed — 1 = 2.5G, 2 = 5G, 4 = 10G.
    • DATA4: Reserved.
    • DATA5: 1 = MAC/PHY frequency unlocked, 0 = MAC/PHY frequency is locked.

§1.25.1.43 SET_USXGMII (0x8026)

  • Description: Sets the USXGMII mode and AUTONEG function (enable/disable).
  • Input Parameters:
    • DATA1: USXGMII enable — 0 = Disable USXGMII, 1 = Enable USXGMII.
    • DATA2: USXGMII autonegotiation enable status (only valid if USXGMII is enabled) — 0 = Disable autonegotiation, 1 = Enable autonegotiation.
    • DATA3: [0:2] = single_max_speed — 1 = 2.5G, 2 = 5G, 4 = 10G.
    • DATA4: Reserved.
    • DATA5: 1 = MAC/PHY frequency unlocked, 0 = MAC/PHY frequency is locked.
  • Return Results: None.

§1.25.1.44 SET_WOL_ENABLE (0x805A)

  • Description: Enable/disable wake-on-LAN (WOL) mode.
  • Input Parameters: DATA1: WOL mode enable — 0 = Disable WOL mode, 1 = Enable WOL mode. DATA2 to DATA5: Reserved.
  • Return Results: None.
  • NOTE: This command takes effect immediately without need of link re-establishment. After WOL mode is set, do a soft reset to the PHY prior to its normal operation. WOL mode is only necessary for 2.5G speed and above.

§1.25.1.45 GET_WOL_ENABLE (0x805B)

  • Description: Get wake-on-LAN (WOL) mode settings.
  • Input Parameters: None.
  • Return Results: DATA1: WOL mode enable — 0 = Disable WOL mode, 1 = Enable WOL mode. DATA2 to DATA5: Reserved.

§1.26 General-Purpose LED Programmability (excerpt start)

The BCM84891L has five LED pins, LED1 through LED5, that can be functionally programmed. Control register words select LED functions for each pin, located in register LED Control (DEVAD = 1, Address = 0xA83B).

  • LED sources are masked in the Control LEDx Mask register. An LED mask bit should be set to 1 to allow the source to drive the LED pin. When multiple bits in the Control LEDx Mask register are set, the LED sources are OR'd together.
  • The LEDs are driven by LED Control (DEVAD = 1, Address = 0xA83B) and LED Control Source (DEVAD = 1, Address = 0xA83C) when the mask associated with the LED is enabled.
  • In 10G mode, each LED is controlled separately by individual bits of PHYC_CTL_LED_CTL. The LEDx_OE_N enables the LEDx output. LEDx_CTL controls the mode:
    • 00 = LED is off.
    • 01 = LED blinks based on the selected source. The blink cycle is programmed by 10GBASE-T Control LEDx bit [3:0].
    • 10 = LED is ON based on the selected source registers.
    • 11 = reserved.
  • Each of the five LEDs has a maskable source register bit (see Table 9 — not in this excerpt).
  • Activity LED: unmask bit 1 (receiver activity) and/or bit 2 (transmitter activity) in the associated Control LEDx Mask register. In LED Control Source (DEVAD = 1, Address = 0xA83C), bit 1 provides receiver activity status and bit 2 provides transmitter activity status. To make the activity pulse visible, set the Stretch_En bit associated with the selected LED pin.

(The excerpt ends here; the LED source table and the remainder of §1.26–§1.28 are not included — see the omitted-chapters list above.)

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