4 Commits

Include renames

Author	SHA1	Message	Date
flamingcow	06fa759b1a	Restructure stats into delta, mask, and aggregate layers	2026-08-31 09:35:32 -07:00
flamingcow	66ff49f9d2	Noise ripped out after the bench verdict (tightly-wrapped unshielded cables move victim SNR only 0.2-0.3 dB, recorded in measurement.md dead ends): noise.go deleted with the noiser, phase clock and panel lane; configureNoise/checkPrivFlag gone so the X710 pair is untouched; console noise column, NOISE links rows and lane colors removed; driverPair rehomed to system.go, carrierUp to phy.go; history anchors to run start (frame-rate sampling and draw-clock roll kept — they fix display latency for every lane); goals/hardware/state/nics docs updated; verified on hardware (20.00G, zero errors, ECD 41m, SNR +7.6)	2026-08-17 21:37:18 -07:00
flamingcow	be2bf56fa7	Unplugged-cable behavior fixed end to end: heat grid rolls on the slot boundary (view computes the newest slot from the draw clock; history sampled every frame so slots color within a frame; noise phase displayed as commanded straight from the shared clock — radiating and the per-slot vote deleted), SNR ghost panic disambiguated via the PMA 1.1 latch (link dropped mid-read discards the batch, ghost on a proven-up link still dies), measure skips the 25s relink wait when the ECD verdict says faulted and the header says MEASURING instead of GOOD while a diag runs, RollBall mailbox deadline resized to 10s from bench measurement (<25ms linked, ~220ms no-link, >3s during a live plug's training; docs/modules/wiitek updated)	2026-08-17 21:29:02 -07:00
flamingcow	fb4b4596e9	Panel rebuilt as the heat matrix: verdict header (ring + newest fault named with its age, cable cell top right), one row per check with NOW / last-90s-at-5s-a-cell / since-reset columns, noise as a blue context lane; history.go keeps the 18-slot wall-time ring (per-class fault deltas, SNR minima, rate verdicts, measuring gray) plus since-reset aggregates and fault ages that clear on reset; noise cycle grid-locked to the shared slot clock so cells never straddle a phase and flicker, presence granted at boot until the first up-phase verdict; check/cross stroked as capsule marks (font has neither), line rate is a pure verdict everywhere, footer is a three-line stat stack beside hold-to-reset; old panel/chip/stat-grid machinery deleted; mockups/ gitignored	2026-08-17 12:22:55 -07:00