1845 lines
74 KiB
C++
1845 lines
74 KiB
C++
#include <cstdio>
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#include <cstring>
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#include <initializer_list>
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#include "pico/stdlib.h"
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#include "pico/error.h"
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#include "pico/critical_section.h"
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#include "hardware/dma.h"
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#include "hardware/clocks.h"
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#include "w6300.h"
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#include "qspi.pio.h"
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namespace {
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#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
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#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
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#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
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#define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits)
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#define PIO_OFFSET_WRITE_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits_end)
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#define PIO_OFFSET_READ_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_read_bits_end)
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constexpr uint8_t PIN_INT = 15;
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constexpr uint8_t PIN_CS = 16;
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constexpr uint8_t PIO_SPI_SCK_PIN = 17;
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constexpr uint8_t PIO_SPI_DATA_IO0_PIN = 18;
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constexpr uint8_t PIO_SPI_DATA_IO1_PIN = 19;
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constexpr uint8_t PIO_SPI_DATA_IO2_PIN = 20;
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constexpr uint8_t PIO_SPI_DATA_IO3_PIN = 21;
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constexpr uint8_t PIN_RST = 22;
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constexpr uint16_t WIZNET_SPI_CLKDIV_MAJOR_DEFAULT = 2;
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constexpr uint8_t WIZNET_SPI_CLKDIV_MINOR_DEFAULT = 0;
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constexpr uint32_t PADS_DRIVE = PADS_BANK0_GPIO0_DRIVE_VALUE_12MA;
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constexpr uint32_t IRQ_DELAY_NS = 100;
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constexpr uint32_t QSPI_LOOP_CNT = 2;
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struct {
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pio_hw_t *pio;
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uint8_t pio_func_sel;
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int8_t pio_offset;
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int8_t pio_sm;
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int8_t dma_out;
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int8_t dma_in;
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} state;
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uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
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pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
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pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
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pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
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pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
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pdst[4] = (uint8_t)(addr >> 8);
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pdst[5] = (uint8_t)(addr);
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pdst[6] = 0;
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return 7;
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}
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uint32_t data_pin_mask() {
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return (1u << PIO_SPI_DATA_IO0_PIN) | (1u << PIO_SPI_DATA_IO1_PIN) |
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(1u << PIO_SPI_DATA_IO2_PIN) | (1u << PIO_SPI_DATA_IO3_PIN);
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}
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__noinline void ns_delay(uint32_t ns) {
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uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u);
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busy_wait_at_least_cycles(cycles);
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}
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void wizchip_pio_init() {
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for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) {
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gpio_init(pin);
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gpio_set_dir(pin, GPIO_OUT);
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gpio_put(pin, false);
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}
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gpio_init(PIN_CS);
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gpio_set_dir(PIN_CS, GPIO_OUT);
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gpio_put(PIN_CS, true);
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gpio_init(PIN_INT);
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gpio_set_dir(PIN_INT, GPIO_IN);
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gpio_set_pulls(PIN_INT, false, false);
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pio_hw_t *pios[2] = {pio0, pio1};
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uint pio_index = 1;
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if (!pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC)) {
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pio_index ^= 1;
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assert(pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC));
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}
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state.pio = pios[pio_index];
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state.dma_in = -1;
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state.dma_out = -1;
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static_assert(GPIO_FUNC_PIO1 == GPIO_FUNC_PIO0 + 1);
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state.pio_func_sel = GPIO_FUNC_PIO0 + pio_index;
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state.pio_sm = (int8_t)pio_claim_unused_sm(state.pio, true);
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state.pio_offset = pio_add_program(state.pio, &PIO_PROGRAM_FUNC);
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pio_sm_config sm_config = PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC(state.pio_offset);
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sm_config_set_clkdiv_int_frac(&sm_config, WIZNET_SPI_CLKDIV_MAJOR_DEFAULT, WIZNET_SPI_CLKDIV_MINOR_DEFAULT);
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hw_write_masked(&pads_bank0_hw->io[PIO_SPI_SCK_PIN],
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(uint)PADS_DRIVE << PADS_BANK0_GPIO0_DRIVE_LSB,
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PADS_BANK0_GPIO0_DRIVE_BITS);
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hw_write_masked(&pads_bank0_hw->io[PIO_SPI_SCK_PIN],
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1u << PADS_BANK0_GPIO0_SLEWFAST_LSB,
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PADS_BANK0_GPIO0_SLEWFAST_BITS);
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sm_config_set_out_pins(&sm_config, PIO_SPI_DATA_IO0_PIN, 4);
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sm_config_set_in_pins(&sm_config, PIO_SPI_DATA_IO0_PIN);
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sm_config_set_set_pins(&sm_config, PIO_SPI_DATA_IO0_PIN, 4);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_sideset_pins(&sm_config, PIO_SPI_SCK_PIN);
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sm_config_set_in_shift(&sm_config, false, true, 8);
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sm_config_set_out_shift(&sm_config, false, true, 8);
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hw_set_bits(&state.pio->input_sync_bypass, data_pin_mask());
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pio_sm_set_config(state.pio, state.pio_sm, &sm_config);
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pio_sm_set_consecutive_pindirs(state.pio, state.pio_sm, PIO_SPI_SCK_PIN, 1, true);
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for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) {
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gpio_set_function(pin, (gpio_function_t)state.pio_func_sel);
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gpio_set_pulls(pin, false, true);
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gpio_set_input_hysteresis_enabled(pin, true);
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}
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_set(pio_pins, 1));
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state.dma_out = (int8_t)dma_claim_unused_channel(true);
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state.dma_in = (int8_t)dma_claim_unused_channel(true);
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}
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void wizchip_pio_frame_start() {
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for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN})
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gpio_set_function(pin, (gpio_function_t)state.pio_func_sel);
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gpio_set_function(PIO_SPI_SCK_PIN, (gpio_function_t)state.pio_func_sel);
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gpio_pull_down(PIO_SPI_SCK_PIN);
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gpio_put(PIN_CS, false);
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}
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void wizchip_pio_frame_end() {
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gpio_put(PIN_CS, true);
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ns_delay(IRQ_DELAY_NS);
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}
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void wizchip_pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) {
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uint8_t cmd[8] = {};
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uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr);
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pio_sm_set_enabled(state.pio, state.pio_sm, false);
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pio_sm_set_wrap(state.pio, state.pio_sm, state.pio_offset, state.pio_offset + PIO_OFFSET_READ_BITS_END - 1);
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pio_sm_clear_fifos(state.pio, state.pio_sm);
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pio_sm_set_pindirs_with_mask(state.pio, state.pio_sm, data_pin_mask(), data_pin_mask());
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pio_sm_restart(state.pio, state.pio_sm);
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pio_sm_clkdiv_restart(state.pio, state.pio_sm);
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pio_sm_put(state.pio, state.pio_sm, cmd_len * QSPI_LOOP_CNT - 1);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_x, 32));
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pio_sm_put(state.pio, state.pio_sm, len - 1);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_y, 32));
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_jmp(state.pio_offset));
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dma_channel_abort(state.dma_out);
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dma_channel_abort(state.dma_in);
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dma_channel_config out_cfg = dma_channel_get_default_config(state.dma_out);
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channel_config_set_transfer_data_size(&out_cfg, DMA_SIZE_8);
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channel_config_set_bswap(&out_cfg, true);
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channel_config_set_dreq(&out_cfg, pio_get_dreq(state.pio, state.pio_sm, true));
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dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], cmd, cmd_len, true);
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dma_channel_config in_cfg = dma_channel_get_default_config(state.dma_in);
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channel_config_set_transfer_data_size(&in_cfg, DMA_SIZE_8);
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channel_config_set_bswap(&in_cfg, true);
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channel_config_set_dreq(&in_cfg, pio_get_dreq(state.pio, state.pio_sm, false));
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channel_config_set_write_increment(&in_cfg, true);
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channel_config_set_read_increment(&in_cfg, false);
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dma_channel_configure(state.dma_in, &in_cfg, buf, &state.pio->rxf[state.pio_sm], len, true);
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pio_sm_set_enabled(state.pio, state.pio_sm, true);
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__compiler_memory_barrier();
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dma_channel_wait_for_finish_blocking(state.dma_out);
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dma_channel_wait_for_finish_blocking(state.dma_in);
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__compiler_memory_barrier();
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pio_sm_set_enabled(state.pio, state.pio_sm, false);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_mov(pio_pins, pio_null));
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}
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void wizchip_pio_write(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) {
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uint8_t cmd[8] = {};
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uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr);
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uint16_t total = len + cmd_len;
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pio_sm_set_enabled(state.pio, state.pio_sm, false);
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pio_sm_set_wrap(state.pio, state.pio_sm, state.pio_offset, state.pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
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pio_sm_clear_fifos(state.pio, state.pio_sm);
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pio_sm_set_pindirs_with_mask(state.pio, state.pio_sm, data_pin_mask(), data_pin_mask());
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pio_sm_restart(state.pio, state.pio_sm);
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pio_sm_clkdiv_restart(state.pio, state.pio_sm);
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pio_sm_put(state.pio, state.pio_sm, total * QSPI_LOOP_CNT - 1);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_x, 32));
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pio_sm_put(state.pio, state.pio_sm, 0);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_y, 32));
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_jmp(state.pio_offset));
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dma_channel_abort(state.dma_out);
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dma_channel_config out_cfg = dma_channel_get_default_config(state.dma_out);
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channel_config_set_transfer_data_size(&out_cfg, DMA_SIZE_8);
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channel_config_set_bswap(&out_cfg, true);
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channel_config_set_dreq(&out_cfg, pio_get_dreq(state.pio, state.pio_sm, true));
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pio_sm_set_enabled(state.pio, state.pio_sm, true);
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dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], cmd, cmd_len, true);
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dma_channel_wait_for_finish_blocking(state.dma_out);
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dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], buf, len, true);
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dma_channel_wait_for_finish_blocking(state.dma_out);
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const uint32_t stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + state.pio_sm);
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state.pio->fdebug = stall;
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while (!(state.pio->fdebug & stall)) tight_loop_contents();
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__compiler_memory_barrier();
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pio_sm_set_consecutive_pindirs(state.pio, state.pio_sm, PIO_SPI_DATA_IO0_PIN, 4, false);
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pio_sm_exec(state.pio, state.pio_sm, pio_encode_mov(pio_pins, pio_null));
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pio_sm_set_enabled(state.pio, state.pio_sm, false);
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}
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constexpr int _WIZCHIP_ = 6300;
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constexpr uint8_t _WIZCHIP_QSPI_MODE_ = 0x02 << 6;
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constexpr int _WIZCHIP_SOCK_NUM_ = WIZCHIP_SOCK_NUM;
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constexpr uint16_t _PHY_IO_MODE_PHYCR_ = 0x0000;
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constexpr uint16_t _PHY_IO_MODE_MII_ = 0x0010;
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constexpr uint16_t _PHY_IO_MODE_ = _PHY_IO_MODE_MII_;
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constexpr uint8_t W6300_SPI_READ = (0x00 << 5);
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constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5);
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constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00;
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constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; }
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constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; }
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constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; }
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constexpr uint32_t WIZCHIP_OFFSET_INC(uint32_t addr, uint32_t n) { return addr + (n << 8); }
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constexpr uint32_t _CIDR_ = (0x0000 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _RTL_ = (0x0004 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _VER_ = (0x0002 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SYSR_ = (0x2000 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SYCR0_ = (0x2004 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SYCR1_ = WIZCHIP_OFFSET_INC(_SYCR0_, 1);
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constexpr uint32_t _TCNTR_ = (0x2016 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _TCNTRCLR_ = (0x2020 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _IR_ = (0x2100 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SIR_ = (0x2101 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLIR_ = (0x2102 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _IMR_ = (0x2104 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _IRCLR_ = (0x2108 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SIMR_ = (0x2114 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLIMR_ = (0x2124 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLIRCLR_ = (0x2128 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLPSR_ = (0x212C << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLCR_ = (0x2130 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYSR_ = (0x3000 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYRAR_ = (0x3008 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYDIR_ = (0x300C << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYDOR_ = (0x3010 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYACR_ = (0x3014 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYDIVR_ = (0x3018 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYCR0_ = (0x301C << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHYCR1_ = WIZCHIP_OFFSET_INC(_PHYCR0_, 1);
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constexpr uint32_t _NET4MR_ = (0x4000 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _NET6MR_ = (0x4004 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _NETMR_ = (0x4008 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _NETMR2_ = (0x4009 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PTMR_ = (0x4100 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PMNR_ = (0x4104 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PHAR_ = (0x4108 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PSIDR_ = (0x4110 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PMRUR_ = (0x4114 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SHAR_ = (0x4120 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _GAR_ = (0x4130 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _GA4R_ = _GAR_;
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constexpr uint32_t _SUBR_ = (0x4134 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SUB4R_ = _SUBR_;
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constexpr uint32_t _SIPR_ = (0x4138 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SIP4R_ = _SIPR_;
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constexpr uint32_t _LLAR_ = (0x4140 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _GUAR_ = (0x4150 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SUB6R_ = (0x4160 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _GA6R_ = (0x4170 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLDIP6R_ = (0x4180 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLDIPR_ = (0x418C << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _SLDIP4R_ = _SLDIPR_;
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constexpr uint32_t _SLDHAR_ = (0x4190 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PINGIDR_ = (0x4198 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _PINGSEQR_ = (0x419C << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _UIPR_ = (0x41A0 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _UIP4R_ = _UIPR_;
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constexpr uint32_t _UPORTR_ = (0x41A4 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _UPORT4R_ = _UPORTR_;
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constexpr uint32_t _UIP6R_ = (0x41B0 << 8) + WIZCHIP_CREG_BLOCK;
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constexpr uint32_t _UPORT6R_ = (0x41C0 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _INTPTMR_ = (0x41C5 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _PLR_ = (0x41D0 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _PFR_ = (0x41D4 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _VLTR_ = (0x41D8 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _PLTR_ = (0x41DC << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _PAR_ = (0x41E0 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _CHPLCKR_ = (0x41F4 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _NETLCKR_ = (0x41F5 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _PHYLCKR_ = (0x41F6 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _RTR_ = (0x4200 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _RCR_ = (0x4204 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _SLRTR_ = (0x4208 << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _SLRCR_ = (0x420C << 8) + WIZCHIP_CREG_BLOCK;
|
|
constexpr uint32_t _SLHOPR_ = (0x420F << 8) + WIZCHIP_CREG_BLOCK;
|
|
|
|
constexpr uint32_t _Sn_MR_(uint8_t n) { return (0x0000 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_PSR_(uint8_t n) { return (0x0004 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_CR_(uint8_t n) { return (0x0010 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_IR_(uint8_t n) { return (0x0020 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_IMR_(uint8_t n) { return (0x0024 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_IRCLR_(uint8_t n) { return (0x0028 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_SR_(uint8_t n) { return (0x0030 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_ESR_(uint8_t n) { return (0x0031 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_PNR_(uint8_t n) { return (0x0100 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_NHR_(uint8_t n) { return _Sn_PNR_(n); }
|
|
constexpr uint32_t _Sn_TOSR_(uint8_t n) { return (0x0104 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_TTLR_(uint8_t n) { return (0x0108 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_HOPR_(uint8_t n) { return _Sn_TTLR_(n); }
|
|
constexpr uint32_t _Sn_FRGR_(uint8_t n) { return (0x010C << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_MSSR_(uint8_t n) { return (0x0110 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_PORTR_(uint8_t n) { return (0x0114 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_DHAR_(uint8_t n) { return (0x0118 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_DIPR_(uint8_t n) { return (0x0120 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_DIP4R_(uint8_t n) { return _Sn_DIPR_(n); }
|
|
constexpr uint32_t _Sn_DIP6R_(uint8_t n) { return (0x0130 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_DPORTR_(uint8_t n) { return (0x0140 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_MR2_(uint8_t n) { return (0x0144 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RTR_(uint8_t n) { return (0x0180 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RCR_(uint8_t n) { return (0x0184 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_TX_BSR_(uint8_t n) { return (0x0200 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_TX_FSR_(uint8_t n) { return (0x0204 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_TX_RD_(uint8_t n) { return (0x0208 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_TX_WR_(uint8_t n) { return (0x020C << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RX_BSR_(uint8_t n) { return (0x0220 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RX_RSR_(uint8_t n) { return (0x0224 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RX_RD_(uint8_t n) { return (0x0228 << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
constexpr uint32_t _Sn_RX_WR_(uint8_t n) { return (0x022C << 8) + WIZCHIP_SREG_BLOCK(n); }
|
|
|
|
constexpr uint8_t SYSR_CHPL = 1 << 7;
|
|
constexpr uint8_t SYSR_NETL = 1 << 6;
|
|
constexpr uint8_t SYSR_PHYL = 1 << 5;
|
|
constexpr uint8_t SYSR_IND = 1 << 5;
|
|
constexpr uint8_t SYSR_SPI = 1 << 0;
|
|
constexpr uint8_t SYCR0_RST = 0x00;
|
|
constexpr uint8_t SYCR1_IEN = 1 << 7;
|
|
constexpr uint8_t SYCR1_CLKSEL = 1 << 0;
|
|
constexpr uint8_t SYCR1_CLKSEL_25M = 1;
|
|
constexpr uint8_t SYCR1_CLKSEL_100M = 0;
|
|
constexpr uint8_t IR_WOL = 1 << 7;
|
|
constexpr uint8_t IR_UNR6 = 1 << 4;
|
|
constexpr uint8_t IR_IPCONF = 1 << 2;
|
|
constexpr uint8_t IR_UNR4 = 1 << 1;
|
|
constexpr uint8_t IR_PTERM = 1 << 0;
|
|
constexpr uint8_t SIR_INT(uint8_t n) { return 1 << n; }
|
|
constexpr uint8_t SLIR_TOUT = 1 << 7;
|
|
constexpr uint8_t SLIR_ARP4 = 1 << 6;
|
|
constexpr uint8_t SLIR_PING4 = 1 << 5;
|
|
constexpr uint8_t SLIR_ARP6 = 1 << 4;
|
|
constexpr uint8_t SLIR_PING6 = 1 << 3;
|
|
constexpr uint8_t SLIR_NS = 1 << 2;
|
|
constexpr uint8_t SLIR_RS = 1 << 1;
|
|
constexpr uint8_t SLIR_RA = 1 << 0;
|
|
constexpr uint8_t PSR_AUTO = 0x00;
|
|
constexpr uint8_t PSR_LLA = 0x02;
|
|
constexpr uint8_t PSR_GUA = 0x03;
|
|
constexpr uint8_t SLCR_ARP4 = 1 << 6;
|
|
constexpr uint8_t SLCR_PING4 = 1 << 5;
|
|
constexpr uint8_t SLCR_ARP6 = 1 << 4;
|
|
constexpr uint8_t SLCR_PING6 = 1 << 3;
|
|
constexpr uint8_t SLCR_NS = 1 << 2;
|
|
constexpr uint8_t SLCR_RS = 1 << 1;
|
|
constexpr uint8_t SLCR_UNA = 1 << 0;
|
|
constexpr uint8_t PHYSR_CAB = 1 << 7;
|
|
constexpr uint8_t PHYSR_CAB_OFF = 1 << 7;
|
|
constexpr uint8_t PHYSR_CAB_ON = 0 << 7;
|
|
constexpr uint8_t PHYSR_MODE = 7 << 3;
|
|
constexpr uint8_t PHYSR_MODE_AUTO = 0 << 3;
|
|
constexpr uint8_t PHYSR_MODE_100F = 4 << 3;
|
|
constexpr uint8_t PHYSR_MODE_100H = 5 << 3;
|
|
constexpr uint8_t PHYSR_MODE_10F = 6 << 3;
|
|
constexpr uint8_t PHYSR_MODE_10H = 7 << 3;
|
|
constexpr uint8_t PHYSR_DPX = 1 << 2;
|
|
constexpr uint8_t PHYSR_DPX_HALF = 1 << 2;
|
|
constexpr uint8_t PHYSR_DPX_FULL = 0 << 2;
|
|
constexpr uint8_t PHYSR_SPD = 1 << 1;
|
|
constexpr uint8_t PHYSR_SPD_10M = 1 << 1;
|
|
constexpr uint8_t PHYSR_SPD_100M = 0 << 1;
|
|
constexpr uint8_t PHYSR_LNK = 1 << 0;
|
|
constexpr uint8_t PHYSR_LNK_UP = 1 << 0;
|
|
constexpr uint8_t PHYSR_LNK_DOWN = 0 << 0;
|
|
constexpr uint8_t PHYACR_READ = 0x02;
|
|
constexpr uint8_t PHYACR_WRITE = 0x01;
|
|
constexpr uint8_t PHYDIVR_32 = 0x00;
|
|
constexpr uint8_t PHYDIVR_64 = 0x01;
|
|
constexpr uint8_t PHYDIVR_128 = 0xFF;
|
|
constexpr uint8_t PHYCR0_AUTO = 0x00;
|
|
constexpr uint8_t PHYCR0_100F = 0x04;
|
|
constexpr uint8_t PHYCR0_100H = 0x05;
|
|
constexpr uint8_t PHYCR0_10F = 0x06;
|
|
constexpr uint8_t PHYCR0_10H = 0x07;
|
|
constexpr uint8_t PHYCR1_PWDN = 1 << 5;
|
|
constexpr uint8_t PHYCR1_TE = 1 << 3;
|
|
constexpr uint8_t PHYCR1_RST = 1 << 0;
|
|
constexpr uint8_t NETxMR_UNRB = 1 << 3;
|
|
constexpr uint8_t NETxMR_PARP = 1 << 2;
|
|
constexpr uint8_t NETxMR_RSTB = 1 << 1;
|
|
constexpr uint8_t NETxMR_PB = 1 << 0;
|
|
constexpr uint8_t NETMR_ANB = 1 << 5;
|
|
constexpr uint8_t NETMR_M6B = 1 << 4;
|
|
constexpr uint8_t NETMR_WOL = 1 << 2;
|
|
constexpr uint8_t NETMR_IP6B = 1 << 1;
|
|
constexpr uint8_t NETMR_IP4B = 1 << 0;
|
|
constexpr uint8_t NETMR2_DHAS = 1 << 7;
|
|
constexpr uint8_t NETMR2_DHAS_ARP = 1 << 7;
|
|
constexpr uint8_t NETMR2_DHAS_ETH = 0 << 7;
|
|
constexpr uint8_t NETMR2_PPPoE = 1 << 0;
|
|
constexpr uint8_t ICMP6BLKR_PING6 = 1 << 4;
|
|
constexpr uint8_t ICMP6BLKR_MLD = 1 << 3;
|
|
constexpr uint8_t ICMP6BLKR_RA = 1 << 2;
|
|
constexpr uint8_t ICMP6BLKR_NA = 1 << 1;
|
|
constexpr uint8_t ICMP6BLKR_NS = 1 << 0;
|
|
constexpr uint8_t Sn_MR_MULTI = 1 << 7;
|
|
constexpr uint8_t Sn_MR_MF = 1 << 7;
|
|
constexpr uint8_t Sn_MR_BRDB = 1 << 6;
|
|
constexpr uint8_t Sn_MR_FPSH = 1 << 6;
|
|
constexpr uint8_t Sn_MR_ND = 1 << 5;
|
|
constexpr uint8_t Sn_MR_MC = 1 << 5;
|
|
constexpr uint8_t Sn_MR_SMB = 1 << 5;
|
|
constexpr uint8_t Sn_MR_MMB = 1 << 5;
|
|
constexpr uint8_t Sn_MR_MMB4 = Sn_MR_MMB;
|
|
constexpr uint8_t Sn_MR_UNIB = 1 << 4;
|
|
constexpr uint8_t Sn_MR_MMB6 = 1 << 4;
|
|
constexpr uint8_t Sn_MR_CLOSE = 0x00;
|
|
constexpr uint8_t Sn_MR_TCP = 0x01;
|
|
constexpr uint8_t Sn_MR_TCP4 = Sn_MR_TCP;
|
|
constexpr uint8_t Sn_MR_UDP = 0x02;
|
|
constexpr uint8_t Sn_MR_UDP4 = Sn_MR_UDP;
|
|
constexpr uint8_t Sn_MR_IPRAW = 0x03;
|
|
constexpr uint8_t Sn_MR_IPRAW4 = Sn_MR_IPRAW;
|
|
constexpr uint8_t Sn_MR_MACRAW = 0x07;
|
|
constexpr uint8_t Sn_MR_TCP6 = 0x09;
|
|
constexpr uint8_t Sn_MR_UDP6 = 0x0A;
|
|
constexpr uint8_t Sn_MR_IPRAW6 = 0x0B;
|
|
constexpr uint8_t Sn_MR_TCPD = 0x0D;
|
|
constexpr uint8_t Sn_MR_UDPD = 0x0E;
|
|
constexpr uint8_t Sn_CR_OPEN = 0x01;
|
|
constexpr uint8_t Sn_CR_LISTEN = 0x02;
|
|
constexpr uint8_t Sn_CR_CONNECT = 0x04;
|
|
constexpr uint8_t Sn_CR_CONNECT6 = 0x84;
|
|
constexpr uint8_t Sn_CR_DISCON = 0x08;
|
|
constexpr uint8_t Sn_CR_CLOSE = 0x10;
|
|
constexpr uint8_t Sn_CR_SEND = 0x20;
|
|
constexpr uint8_t Sn_CR_SEND6 = 0xA0;
|
|
constexpr uint8_t Sn_CR_SEND_KEEP = 0x22;
|
|
constexpr uint8_t Sn_CR_RECV = 0x40;
|
|
constexpr uint8_t Sn_IR_SENDOK = 0x10;
|
|
constexpr uint8_t Sn_IR_TIMEOUT = 0x08;
|
|
constexpr uint8_t Sn_IR_RECV = 0x04;
|
|
constexpr uint8_t Sn_IR_DISCON = 0x02;
|
|
constexpr uint8_t Sn_IR_CON = 0x01;
|
|
constexpr uint8_t SOCK_CLOSED = 0x00;
|
|
constexpr uint8_t SOCK_INIT = 0x13;
|
|
constexpr uint8_t SOCK_LISTEN = 0x14;
|
|
constexpr uint8_t SOCK_SYNSENT = 0x15;
|
|
constexpr uint8_t SOCK_SYNRECV = 0x16;
|
|
constexpr uint8_t SOCK_ESTABLISHED = 0x17;
|
|
constexpr uint8_t SOCK_FIN_WAIT = 0x18;
|
|
constexpr uint8_t SOCK_TIME_WAIT = 0x1B;
|
|
constexpr uint8_t SOCK_CLOSE_WAIT = 0x1C;
|
|
constexpr uint8_t SOCK_LAST_ACK = 0x1D;
|
|
constexpr uint8_t SOCK_UDP = 0x22;
|
|
constexpr uint8_t SOCK_IPRAW4 = 0x32;
|
|
constexpr uint8_t SOCK_IPRAW = SOCK_IPRAW4;
|
|
constexpr uint8_t SOCK_IPRAW6 = 0x33;
|
|
constexpr uint8_t SOCK_MACRAW = 0x42;
|
|
constexpr uint8_t Sn_ESR_TCPM = 1 << 2;
|
|
constexpr uint8_t Sn_ESR_TCPM_IPV4 = 0 << 2;
|
|
constexpr uint8_t Sn_ESR_TCPM_IPV6 = 1 << 2;
|
|
constexpr uint8_t Sn_ESR_TCPOP = 1 << 1;
|
|
constexpr uint8_t Sn_ESR_TCPOP_SVR = 0 << 1;
|
|
constexpr uint8_t Sn_ESR_TCPOP_CLT = 1 << 1;
|
|
constexpr uint8_t Sn_ESR_IP6T = 1 << 0;
|
|
constexpr uint8_t Sn_ESR_IP6T_LLA = 0 << 0;
|
|
constexpr uint8_t Sn_ESR_IP6T_GUA = 1 << 0;
|
|
constexpr uint8_t Sn_MR2_DHAM = 1 << 1;
|
|
constexpr uint8_t Sn_MR2_DHAM_AUTO = 0 << 1;
|
|
constexpr uint8_t Sn_MR2_DHAM_MANUAL = 1 << 1;
|
|
constexpr uint8_t Sn_MR2_FARP = 1 << 0;
|
|
constexpr uint8_t PHYRAR_BMCR = 0x00;
|
|
constexpr uint8_t PHYRAR_BMSR = 0x01;
|
|
constexpr uint16_t BMCR_RST = 1 << 15;
|
|
constexpr uint16_t BMCR_LB = 1 << 14;
|
|
constexpr uint16_t BMCR_SPD = 1 << 13;
|
|
constexpr uint16_t BMCR_ANE = 1 << 12;
|
|
constexpr uint16_t BMCR_PWDN = 1 << 11;
|
|
constexpr uint16_t BMCR_ISOL = 1 << 10;
|
|
constexpr uint16_t BMCR_REAN = 1 << 9;
|
|
constexpr uint16_t BMCR_DPX = 1 << 8;
|
|
constexpr uint16_t BMCR_COLT = 1 << 7;
|
|
constexpr uint16_t BMSR_100_T4 = 1 << 15;
|
|
constexpr uint16_t BMSR_100_FDX = 1 << 14;
|
|
constexpr uint16_t BMSR_100_HDX = 1 << 13;
|
|
constexpr uint16_t BMSR_10_FDX = 1 << 12;
|
|
constexpr uint16_t BMSR_10_HDX = 1 << 11;
|
|
constexpr uint16_t BMSR_MF_SUP = 1 << 6;
|
|
constexpr uint16_t BMSR_AN_COMP = 1 << 5;
|
|
constexpr uint16_t BMSR_REMOTE_FAULT = 1 << 4;
|
|
constexpr uint16_t BMSR_AN_ABILITY = 1 << 3;
|
|
constexpr uint16_t BMSR_LINK_STATUS = 1 << 2;
|
|
constexpr uint16_t BMSR_JABBER_DETECT = 1 << 1;
|
|
constexpr uint16_t BMSR_EXT_CAPA = 1 << 0;
|
|
|
|
void wizchip_cris_enter();
|
|
void wizchip_cris_exit();
|
|
inline void WIZCHIP_CRITICAL_ENTER() { wizchip_cris_enter(); }
|
|
inline void WIZCHIP_CRITICAL_EXIT() { wizchip_cris_exit(); }
|
|
|
|
uint8_t WIZCHIP_READ(uint32_t AddrSel);
|
|
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
|
|
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
|
|
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
|
|
uint16_t getSn_TX_FSR(uint8_t sn);
|
|
uint16_t getSn_RX_RSR(uint8_t sn);
|
|
|
|
inline uint8_t getRTL() { return WIZCHIP_READ(_RTL_); }
|
|
inline uint16_t getCIDR() { return (((uint16_t)WIZCHIP_READ(_CIDR_) | (((WIZCHIP_READ(_RTL_)) & 0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_, 1)); }
|
|
inline uint16_t getVER() { return (((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_, 1)); }
|
|
inline uint8_t getSYSR() { return WIZCHIP_READ(_SYSR_); }
|
|
inline uint8_t getSYCR0() { return WIZCHIP_READ(_SYCR0_); }
|
|
inline void setSYCR0(uint8_t v) { WIZCHIP_WRITE(_SYCR0_, v); }
|
|
inline uint8_t getSYCR1() { return WIZCHIP_READ(_SYCR1_); }
|
|
inline void setSYCR1(uint8_t v) { WIZCHIP_WRITE(_SYCR1_, v); }
|
|
inline uint16_t getTCNTR() { return (((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_, 1)); }
|
|
inline void setTCNTRCLR(uint8_t v) { WIZCHIP_WRITE(_TCNTRCLR_, v); }
|
|
inline uint8_t getIR() { return WIZCHIP_READ(_IR_); }
|
|
inline uint8_t getSIR() { return WIZCHIP_READ(_SIR_); }
|
|
inline uint8_t getSLIR() { return WIZCHIP_READ(_SLIR_); }
|
|
inline void setIMR(uint8_t v) { WIZCHIP_WRITE(_IMR_, v); }
|
|
inline uint8_t getIMR() { return WIZCHIP_READ(_IMR_); }
|
|
inline void setIRCLR(uint8_t v) { WIZCHIP_WRITE(_IRCLR_, v); }
|
|
inline void setIR(uint8_t v) { setIRCLR(v); }
|
|
inline void setSIMR(uint8_t v) { WIZCHIP_WRITE(_SIMR_, v); }
|
|
inline uint8_t getSIMR() { return WIZCHIP_READ(_SIMR_); }
|
|
inline void setSLIMR(uint8_t v) { WIZCHIP_WRITE(_SLIMR_, v); }
|
|
inline uint8_t getSLIMR() { return WIZCHIP_READ(_SLIMR_); }
|
|
inline void setSLIRCLR(uint8_t v) { WIZCHIP_WRITE(_SLIRCLR_, v); }
|
|
inline void setSLIR(uint8_t v) { setSLIRCLR(v); }
|
|
inline void setSLPSR(uint8_t v) { WIZCHIP_WRITE(_SLPSR_, v); }
|
|
inline uint8_t getSLPSR() { return WIZCHIP_READ(_SLPSR_); }
|
|
inline void setSLCR(uint8_t v) { WIZCHIP_WRITE(_SLCR_, v); }
|
|
inline uint8_t getSLCR() { return WIZCHIP_READ(_SLCR_); }
|
|
inline uint8_t getPHYSR() { return WIZCHIP_READ(_PHYSR_); }
|
|
inline void setPHYRAR(uint8_t v) { WIZCHIP_WRITE(_PHYRAR_, v); }
|
|
inline uint8_t getPHYRAR() { return WIZCHIP_READ(_PHYRAR_); }
|
|
inline void setPHYDIR(uint16_t v) {
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_, 1), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(_PHYDIR_, (uint8_t)v);
|
|
}
|
|
inline uint16_t getPHYDOR() { return (((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_, 1))) << 8) + WIZCHIP_READ(_PHYDOR_); }
|
|
inline void setPHYACR(uint8_t v) { WIZCHIP_WRITE(_PHYACR_, v); }
|
|
inline uint8_t getPHYACR() { return WIZCHIP_READ(_PHYACR_); }
|
|
inline void setPHYDIVR(uint8_t v) { WIZCHIP_WRITE(_PHYDIVR_, v); }
|
|
inline uint8_t getPHYDIVR() { return WIZCHIP_READ(_PHYDIVR_); }
|
|
inline void setPHYCR0(uint8_t v) { WIZCHIP_WRITE(_PHYCR0_, v); }
|
|
inline void setPHYCR1(uint8_t v) { WIZCHIP_WRITE(_PHYCR1_, v); }
|
|
inline uint8_t getPHYCR1() { return WIZCHIP_READ(_PHYCR1_); }
|
|
inline void setNET4MR(uint8_t v) { WIZCHIP_WRITE(_NET4MR_, v); }
|
|
inline void setNET6MR(uint8_t v) { WIZCHIP_WRITE(_NET6MR_, v); }
|
|
inline void setNETMR(uint8_t v) { WIZCHIP_WRITE(_NETMR_, v); }
|
|
inline void setNETMR2(uint8_t v) { WIZCHIP_WRITE(_NETMR2_, v); }
|
|
inline uint8_t getNET4MR() { return WIZCHIP_READ(_NET4MR_); }
|
|
inline uint8_t getNET6MR() { return WIZCHIP_READ(_NET6MR_); }
|
|
inline uint8_t getNETMR() { return WIZCHIP_READ(_NETMR_); }
|
|
inline uint8_t getNETMR2() { return WIZCHIP_READ(_NETMR2_); }
|
|
inline void setPTMR(uint8_t v) { WIZCHIP_WRITE(_PTMR_, v); }
|
|
inline uint8_t getPTMR() { return WIZCHIP_READ(_PTMR_); }
|
|
inline void setPMNR(uint8_t v) { WIZCHIP_WRITE(_PMNR_, v); }
|
|
inline uint8_t getPMNR() { return WIZCHIP_READ(_PMNR_); }
|
|
inline void setPHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_PHAR_, v, 6); }
|
|
inline void getPHAR(uint8_t* v) { WIZCHIP_READ_BUF(_PHAR_, v, 6); }
|
|
inline void setPSIDR(uint16_t v) {
|
|
WIZCHIP_WRITE(_PSIDR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getPSIDR() { return (((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_, 1)); }
|
|
inline void setPMRUR(uint16_t v) {
|
|
WIZCHIP_WRITE(_PMRUR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getPMRUR() { return (((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_, 1)); }
|
|
inline void setSHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SHAR_, v, 6); }
|
|
inline void getSHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SHAR_, v, 6); }
|
|
inline void setGAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GAR_, v, 4); }
|
|
inline void getGAR(uint8_t* v) { WIZCHIP_READ_BUF(_GAR_, v, 4); }
|
|
inline void setGA4R(uint8_t* v) { setGAR(v); }
|
|
inline void getGA4R(uint8_t* v) { getGAR(v); }
|
|
inline void setSUBR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUBR_, v, 4); }
|
|
inline void getSUBR(uint8_t* v) { WIZCHIP_READ_BUF(_SUBR_, v, 4); }
|
|
inline void setSUB4R(uint8_t* v) { setSUBR(v); }
|
|
inline void getSUB4R(uint8_t* v) { getSUBR(v); }
|
|
inline void setSIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SIPR_, v, 4); }
|
|
inline void getSIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SIPR_, v, 4); }
|
|
inline void setLLAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_LLAR_, v, 16); }
|
|
inline void getLLAR(uint8_t* v) { WIZCHIP_READ_BUF(_LLAR_, v, 16); }
|
|
inline void setGUAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GUAR_, v, 16); }
|
|
inline void getGUAR(uint8_t* v) { WIZCHIP_READ_BUF(_GUAR_, v, 16); }
|
|
inline void setSUB6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUB6R_, v, 16); }
|
|
inline void getSUB6R(uint8_t* v) { WIZCHIP_READ_BUF(_SUB6R_, v, 16); }
|
|
inline void setGA6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_GA6R_, v, 16); }
|
|
inline void getGA6R(uint8_t* v) { WIZCHIP_READ_BUF(_GA6R_, v, 16); }
|
|
inline void setSLDIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIPR_, v, 4); }
|
|
inline void setSLDIP4R(uint8_t* v) { setSLDIPR(v); }
|
|
inline void getSLDIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIPR_, v, 4); }
|
|
inline void getSLDIP4R(uint8_t* v) { getSLDIPR(v); }
|
|
inline void setSLDIP6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIP6R_, v, 16); }
|
|
inline void getSLDIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIP6R_, v, 16); }
|
|
inline void getSLDHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDHAR_, v, 6); }
|
|
inline void setPINGIDR(uint16_t v) {
|
|
WIZCHIP_WRITE(_PINGIDR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getPINGIDR() { return ((uint16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_, 1)); }
|
|
inline void setPINGSEQR(uint16_t v) {
|
|
WIZCHIP_WRITE(_PINGSEQR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getPINGSEQR() { return ((uint16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1)); }
|
|
inline void getUIPR(uint8_t* v) { WIZCHIP_READ_BUF(_UIPR_, v, 4); }
|
|
inline void getUIP4R(uint8_t* v) { getUIPR(v); }
|
|
inline uint16_t getUPORTR() { return (((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_, 1)); }
|
|
inline uint16_t getUPORT4R() { return getUPORTR(); }
|
|
inline void getUIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_UIP6R_, v, 16); }
|
|
inline uint16_t getUPORT6R() { return (((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_, 1)); }
|
|
inline void setINTPTMR(uint16_t v) {
|
|
WIZCHIP_WRITE(_INTPTMR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getINTPTMR() { return (((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_, 1)); }
|
|
inline uint8_t getPLR() { return WIZCHIP_READ(_PLR_); }
|
|
inline uint8_t getPFR() { return WIZCHIP_READ(_PFR_); }
|
|
inline uint32_t getVLTR() {
|
|
return (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) +
|
|
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 1))) << 16) +
|
|
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 2))) << 8) +
|
|
((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 3)));
|
|
}
|
|
inline uint32_t getPLTR() {
|
|
return (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) +
|
|
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 1))) << 16) +
|
|
(((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 2))) << 8) +
|
|
((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 3)));
|
|
}
|
|
inline void getPAR(uint8_t* v) { WIZCHIP_READ_BUF(_PAR_, v, 16); }
|
|
inline void setICMP6BLKR(uint8_t v) { WIZCHIP_WRITE(_ICMP6BLKR_, v); }
|
|
inline uint8_t getICMP6BLKR() { return WIZCHIP_READ(_ICMP6BLKR_); }
|
|
inline void setCHPLCKR(uint8_t v) { WIZCHIP_WRITE(_CHPLCKR_, v); }
|
|
inline uint8_t getCHPLCKR() { return (getSYSR() & SYSR_CHPL) >> 7; }
|
|
inline void CHIPLOCK() { setCHPLCKR(0xFF); }
|
|
inline void CHIPUNLOCK() { setCHPLCKR(0xCE); }
|
|
inline void setNETLCKR(uint8_t v) { WIZCHIP_WRITE(_NETLCKR_, v); }
|
|
inline uint8_t getNETLCKR() { return (getSYSR() & SYSR_NETL) >> 6; }
|
|
inline void NETLOCK() { setNETLCKR(0xC5); }
|
|
inline void NETUNLOCK() { setNETLCKR(0x3A); }
|
|
inline void setPHYLCKR(uint8_t v) { WIZCHIP_WRITE(_PHYLCKR_, v); }
|
|
inline uint8_t getPHYLCKR() { return (getSYSR() & SYSR_PHYL) >> 5; }
|
|
inline void PHYLOCK() { setPHYLCKR(0xFF); }
|
|
inline void PHYUNLOCK() { setPHYLCKR(0x53); }
|
|
inline void setRTR(uint16_t v) {
|
|
WIZCHIP_WRITE(_RTR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getRTR() { return (((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); }
|
|
inline void setRCR(uint8_t v) { WIZCHIP_WRITE(_RCR_, v); }
|
|
inline uint8_t getRCR() { return WIZCHIP_READ(_RCR_); }
|
|
inline void setSLRTR(uint16_t v) {
|
|
WIZCHIP_WRITE(_SLRTR_, (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_, 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSLRTR() { return (((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_, 1)); }
|
|
inline void setSLRCR(uint8_t v) { WIZCHIP_WRITE(_SLRCR_, v); }
|
|
inline uint8_t getSLRCR() { return WIZCHIP_READ(_SLRCR_); }
|
|
inline void setSLHOPR(uint8_t v) { WIZCHIP_WRITE(_SLHOPR_, v); }
|
|
inline uint8_t getSLHOPR() { return WIZCHIP_READ(_SLHOPR_); }
|
|
|
|
inline void setSn_MR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR_(sn), v); }
|
|
inline uint8_t getSn_MR(uint8_t sn) { return WIZCHIP_READ(_Sn_MR_(sn)); }
|
|
inline void setSn_PSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PSR_(sn), v); }
|
|
inline uint8_t getSn_PSR(uint8_t sn) { return WIZCHIP_READ(_Sn_PSR_(sn)); }
|
|
inline void setSn_CR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_CR_(sn), v); }
|
|
inline uint8_t getSn_CR(uint8_t sn) { return WIZCHIP_READ(_Sn_CR_(sn)); }
|
|
inline uint8_t getSn_IR(uint8_t sn) { return WIZCHIP_READ(_Sn_IR_(sn)); }
|
|
inline void setSn_IMR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IMR_(sn), v); }
|
|
inline uint8_t getSn_IMR(uint8_t sn) { return WIZCHIP_READ(_Sn_IMR_(sn)); }
|
|
inline void setSn_IRCLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IRCLR_(sn), v); }
|
|
inline void setSn_IR(uint8_t sn, uint8_t v) { setSn_IRCLR(sn, v); }
|
|
inline uint8_t getSn_SR(uint8_t sn) { return WIZCHIP_READ(_Sn_SR_(sn)); }
|
|
inline uint8_t getSn_ESR(uint8_t sn) { return WIZCHIP_READ(_Sn_ESR_(sn)); }
|
|
inline void setSn_PNR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PNR_(sn), v); }
|
|
inline void setSn_NHR(uint8_t sn, uint8_t v) { setSn_PNR(sn, v); }
|
|
inline uint8_t getSn_PNR(uint8_t sn) { return WIZCHIP_READ(_Sn_PNR_(sn)); }
|
|
inline uint8_t getSn_NHR(uint8_t sn) { return getSn_PNR(sn); }
|
|
inline void setSn_TOSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TOSR_(sn), v); }
|
|
inline uint8_t getSn_TOSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TOSR_(sn)); }
|
|
inline uint8_t getSn_TOS(uint8_t sn) { return getSn_TOSR(sn); }
|
|
inline void setSn_TOS(uint8_t sn, uint8_t v) { setSn_TOSR(sn, v); }
|
|
inline void setSn_TTLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TTLR_(sn), v); }
|
|
inline uint8_t getSn_TTLR(uint8_t sn) { return WIZCHIP_READ(_Sn_TTLR_(sn)); }
|
|
inline void setSn_TTL(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); }
|
|
inline uint8_t getSn_TTL(uint8_t sn) { return getSn_TTLR(sn); }
|
|
inline void setSn_HOPR(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); }
|
|
inline uint8_t getSn_HOPR(uint8_t sn) { return getSn_TTLR(sn); }
|
|
inline void setSn_FRGR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_FRGR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1)); }
|
|
inline void setSn_MSSR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_MSSR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1)); }
|
|
inline void setSn_PORTR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_PORTR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1)); }
|
|
inline void setSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn), v, 6); }
|
|
inline void getSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DHAR_(sn), v, 6); }
|
|
inline void setSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn), v, 4); }
|
|
inline void getSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIPR_(sn), v, 4); }
|
|
inline void setSn_DIP4R(uint8_t sn, uint8_t* v) { setSn_DIPR(sn, v); }
|
|
inline void getSn_DIP4R(uint8_t sn, uint8_t* v) { getSn_DIPR(sn, v); }
|
|
inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn), v, 16); }
|
|
inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIP6R_(sn), v, 16); }
|
|
inline void setSn_DPORTR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_DPORTR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1)); }
|
|
inline uint16_t getSn_DPORT(uint8_t sn) { return getSn_DPORTR(sn); }
|
|
inline void setSn_DPORT(uint8_t sn, uint16_t v) { setSn_DPORTR(sn, v); }
|
|
inline void setSn_MR2(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR2_(sn), v); }
|
|
inline uint8_t getSn_MR2(uint8_t sn) { return WIZCHIP_READ(_Sn_MR2_(sn)); }
|
|
inline void setSn_RTR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_RTR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1)); }
|
|
inline void setSn_RCR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RCR_(sn), v); }
|
|
inline uint8_t getSn_RCR(uint8_t sn) { return WIZCHIP_READ(_Sn_RCR_(sn)); }
|
|
inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_KPALVTR_(sn), v); }
|
|
inline uint8_t getSn_KPALVTR(uint8_t sn) { return WIZCHIP_READ(_Sn_KPALVTR_(sn)); }
|
|
inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TX_BSR_(sn), v); }
|
|
inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_TX_BSR(sn, v); }
|
|
inline uint8_t getSn_TX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TX_BSR_(sn)); }
|
|
inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) { return getSn_TX_BSR(sn); }
|
|
inline uint16_t getSn_TxMAX(uint8_t sn) { return getSn_TX_BSR(sn) << 10; }
|
|
|
|
inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn), 1)); }
|
|
inline void setSn_TX_WR(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1)); }
|
|
inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RX_BSR_(sn), v); }
|
|
inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_RX_BSR(sn, v); }
|
|
inline uint8_t getSn_RX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_RX_BSR_(sn)); }
|
|
inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) { return getSn_RX_BSR(sn); }
|
|
inline uint16_t getSn_RxMAX(uint8_t sn) { return getSn_RX_BSR(sn) << 10; }
|
|
|
|
inline void setSn_RX_RD(uint8_t sn, uint16_t v) {
|
|
WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)(v >> 8));
|
|
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1), (uint8_t)v);
|
|
}
|
|
inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1)); }
|
|
inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn), 1)); }
|
|
static critical_section_t g_cris_sec;
|
|
|
|
void wizchip_cris_enter() {
|
|
critical_section_enter_blocking(&g_cris_sec);
|
|
}
|
|
|
|
void wizchip_cris_exit() {
|
|
critical_section_exit(&g_cris_sec);
|
|
}
|
|
|
|
static uint8_t make_opcode(uint32_t addr, uint8_t rw) {
|
|
return static_cast<uint8_t>((addr & 0xFF) | rw | _WIZCHIP_QSPI_MODE_);
|
|
}
|
|
|
|
static uint16_t make_addr(uint32_t addr) {
|
|
return static_cast<uint16_t>((addr & 0x00FFFF00) >> 8);
|
|
}
|
|
|
|
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
|
|
WIZCHIP_CRITICAL_ENTER();
|
|
wizchip_pio_frame_start();
|
|
wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), &wb, 1);
|
|
wizchip_pio_frame_end();
|
|
WIZCHIP_CRITICAL_EXIT();
|
|
}
|
|
|
|
uint8_t WIZCHIP_READ(uint32_t AddrSel) {
|
|
uint8_t ret[2] = {0};
|
|
WIZCHIP_CRITICAL_ENTER();
|
|
wizchip_pio_frame_start();
|
|
wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), ret, 1);
|
|
wizchip_pio_frame_end();
|
|
WIZCHIP_CRITICAL_EXIT();
|
|
return ret[0];
|
|
}
|
|
|
|
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
|
WIZCHIP_CRITICAL_ENTER();
|
|
wizchip_pio_frame_start();
|
|
wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), pBuf, len);
|
|
wizchip_pio_frame_end();
|
|
WIZCHIP_CRITICAL_EXIT();
|
|
}
|
|
|
|
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
|
|
WIZCHIP_CRITICAL_ENTER();
|
|
wizchip_pio_frame_start();
|
|
wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), pBuf, len);
|
|
wizchip_pio_frame_end();
|
|
WIZCHIP_CRITICAL_EXIT();
|
|
}
|
|
|
|
uint16_t getSn_TX_FSR(uint8_t sn) {
|
|
uint16_t prev_val = -1, val = 0;
|
|
do {
|
|
prev_val = val;
|
|
val = WIZCHIP_READ(_Sn_TX_FSR_(sn));
|
|
val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_FSR_(sn), 1));
|
|
} while (val != prev_val);
|
|
return val;
|
|
}
|
|
|
|
uint16_t getSn_RX_RSR(uint8_t sn) {
|
|
uint16_t prev_val = -1, val = 0;
|
|
do {
|
|
prev_val = val;
|
|
val = WIZCHIP_READ(_Sn_RX_RSR_(sn));
|
|
val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RSR_(sn), 1));
|
|
} while (val != prev_val);
|
|
return val;
|
|
}
|
|
|
|
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
|
|
uint16_t ptr = getSn_TX_WR(sn);
|
|
uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
|
|
WIZCHIP_WRITE_BUF(addrsel, wizdata, len);
|
|
ptr += len;
|
|
setSn_TX_WR(sn, ptr);
|
|
}
|
|
|
|
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
|
|
if (len == 0) return;
|
|
uint16_t ptr = getSn_RX_RD(sn);
|
|
uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
|
WIZCHIP_READ_BUF(addrsel, wizdata, len);
|
|
ptr += len;
|
|
setSn_RX_RD(sn, ptr);
|
|
}
|
|
|
|
void wiz_recv_ignore(uint8_t sn, uint16_t len) {
|
|
setSn_RX_RD(sn, getSn_RX_RD(sn) + len);
|
|
}
|
|
|
|
|
|
void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
|
|
setPHYRAR(phyregaddr);
|
|
setPHYDIR(var);
|
|
setPHYACR(PHYACR_WRITE);
|
|
while (getPHYACR());
|
|
}
|
|
|
|
uint16_t wiz_mdio_read(uint8_t phyregaddr) {
|
|
setPHYRAR(phyregaddr);
|
|
setPHYACR(PHYACR_READ);
|
|
while (getPHYACR());
|
|
return getPHYDOR();
|
|
}
|
|
|
|
} // namespace
|
|
|
|
static uint8_t dns_[4];
|
|
static uint8_t dns6_[16];
|
|
static ipconf_mode ipmode_;
|
|
|
|
static constexpr char WIZCHIP_ID[] = "W6300";
|
|
|
|
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg) {
|
|
uint8_t tmp = *(uint8_t*)arg;
|
|
uint8_t* ptmp[2] = {0, 0};
|
|
switch (cwtype) {
|
|
case CW_SYS_LOCK:
|
|
if (tmp & SYS_CHIP_LOCK) CHIPLOCK();
|
|
if (tmp & SYS_NET_LOCK) NETLOCK();
|
|
if (tmp & SYS_PHY_LOCK) PHYLOCK();
|
|
break;
|
|
case CW_SYS_UNLOCK:
|
|
if (tmp & SYS_CHIP_LOCK) CHIPUNLOCK();
|
|
if (tmp & SYS_NET_LOCK) NETUNLOCK();
|
|
if (tmp & SYS_PHY_LOCK) PHYUNLOCK();
|
|
break;
|
|
case CW_GET_SYSLOCK:
|
|
*(uint8_t*)arg = getSYSR() >> 5;
|
|
break;
|
|
case CW_RESET_WIZCHIP:
|
|
wizchip_sw_reset();
|
|
break;
|
|
case CW_INIT_WIZCHIP:
|
|
if (arg) {
|
|
ptmp[0] = (uint8_t*)arg;
|
|
ptmp[1] = ptmp[0] + WIZCHIP_SOCK_NUM;
|
|
}
|
|
return wizchip_init(ptmp[0], ptmp[1]);
|
|
case CW_CLR_INTERRUPT:
|
|
wizchip_clrinterrupt(*((intr_kind*)arg));
|
|
break;
|
|
case CW_GET_INTERRUPT:
|
|
*((intr_kind*)arg) = wizchip_getinterrupt();
|
|
break;
|
|
case CW_SET_INTRMASK:
|
|
wizchip_setinterruptmask(*((intr_kind*)arg));
|
|
break;
|
|
case CW_GET_INTRMASK:
|
|
*((intr_kind*)arg) = wizchip_getinterruptmask();
|
|
break;
|
|
case CW_SET_INTRTIME:
|
|
setINTPTMR(*(uint16_t*)arg);
|
|
break;
|
|
case CW_GET_INTRTIME:
|
|
*(uint16_t*)arg = getINTPTMR();
|
|
break;
|
|
case CW_GET_ID:
|
|
memcpy(arg, WIZCHIP_ID, sizeof(WIZCHIP_ID));
|
|
break;
|
|
case CW_GET_VER:
|
|
*(uint16_t*)arg = getVER();
|
|
break;
|
|
case CW_RESET_PHY:
|
|
wizphy_reset();
|
|
break;
|
|
case CW_SET_PHYCONF:
|
|
wizphy_setphyconf((wiz_PhyConf*)arg);
|
|
break;
|
|
case CW_GET_PHYCONF:
|
|
wizphy_getphyconf((wiz_PhyConf*)arg);
|
|
break;
|
|
case CW_GET_PHYSTATUS:
|
|
break;
|
|
case CW_SET_PHYPOWMODE:
|
|
wizphy_setphypmode(*(uint8_t*)arg);
|
|
break;
|
|
case CW_GET_PHYPOWMODE:
|
|
tmp = wizphy_getphypmode();
|
|
if ((int8_t)tmp == -1) return -1;
|
|
*(uint8_t*)arg = tmp;
|
|
break;
|
|
case CW_GET_PHYLINK:
|
|
tmp = wizphy_getphylink();
|
|
if ((int8_t)tmp == -1) return -1;
|
|
*(uint8_t*)arg = tmp;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg) {
|
|
switch (cntype) {
|
|
case CN_SET_NETINFO: wizchip_setnetinfo((wiz_NetInfo*)arg); break;
|
|
case CN_GET_NETINFO: wizchip_getnetinfo((wiz_NetInfo*)arg); break;
|
|
case CN_SET_NETMODE: wizchip_setnetmode(*(netmode_type*)arg); break;
|
|
case CN_GET_NETMODE: *(netmode_type*)arg = wizchip_getnetmode(); break;
|
|
case CN_SET_TIMEOUT: wizchip_settimeout((wiz_NetTimeout*)arg); break;
|
|
case CN_GET_TIMEOUT: wizchip_gettimeout((wiz_NetTimeout*)arg); break;
|
|
case CN_SET_PREFER: setSLPSR(*(uint8_t*)arg); break;
|
|
case CN_GET_PREFER: *(uint8_t*)arg = getSLPSR(); break;
|
|
default: return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg) {
|
|
switch (cnstype) {
|
|
case CNS_ARP: return wizchip_arp((wiz_ARP*)arg);
|
|
case CNS_PING: return wizchip_ping((wiz_PING*)arg);
|
|
case CNS_DAD: return wizchip_dad((uint8_t*)arg);
|
|
case CNS_SLAAC: return wizchip_slaac((wiz_Prefix*)arg);
|
|
case CNS_UNSOL_NA: return wizchip_unsolicited();
|
|
case CNS_GET_PREFIX: return wizchip_getprefix((wiz_Prefix*)arg);
|
|
default: return -1;
|
|
}
|
|
}
|
|
|
|
void wizchip_sw_reset() {
|
|
uint8_t gw[4], sn[4], sip[4], mac[6];
|
|
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
|
uint8_t islock = getSYSR();
|
|
|
|
CHIPUNLOCK();
|
|
getSHAR(mac); getGAR(gw); getSUBR(sn); getSIPR(sip);
|
|
getGA6R(gw6); getSUB6R(sn6); getLLAR(lla); getGUAR(gua);
|
|
setSYCR0(SYCR0_RST);
|
|
getSYCR0();
|
|
|
|
NETUNLOCK();
|
|
setSHAR(mac); setGAR(gw); setSUBR(sn); setSIPR(sip);
|
|
setGA6R(gw6); setSUB6R(sn6); setLLAR(lla); setGUAR(gua);
|
|
|
|
if (islock & SYSR_CHPL) CHIPLOCK();
|
|
if (islock & SYSR_NETL) NETLOCK();
|
|
}
|
|
|
|
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize) {
|
|
wizchip_sw_reset();
|
|
if (txsize) {
|
|
int8_t tmp = 0;
|
|
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) {
|
|
tmp += txsize[i];
|
|
if (tmp > 32) return -1;
|
|
}
|
|
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) setSn_TXBUF_SIZE(i, txsize[i]);
|
|
}
|
|
if (rxsize) {
|
|
int8_t tmp = 0;
|
|
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) {
|
|
tmp += rxsize[i];
|
|
if (tmp > 32) return -1;
|
|
}
|
|
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) setSn_RXBUF_SIZE(i, rxsize[i]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void wizchip_clrinterrupt(intr_kind intr) {
|
|
setIRCLR((uint8_t)intr);
|
|
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
|
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++)
|
|
if (sir & (1 << i)) setSn_IRCLR(i, 0xFF);
|
|
setSLIRCLR((uint8_t)((uint32_t)intr >> 16));
|
|
}
|
|
|
|
intr_kind wizchip_getinterrupt() {
|
|
uint32_t ret = getSIR();
|
|
ret = (ret << 8) + getIR();
|
|
ret = (((uint32_t)getSLIR()) << 16) | ret;
|
|
return (intr_kind)ret;
|
|
}
|
|
|
|
void wizchip_setinterruptmask(intr_kind intr) {
|
|
setIMR((uint8_t)intr);
|
|
setSIMR((uint8_t)((uint16_t)intr >> 8));
|
|
setSLIMR((uint8_t)((uint32_t)intr >> 16));
|
|
}
|
|
|
|
intr_kind wizchip_getinterruptmask() {
|
|
uint32_t ret = getSIMR();
|
|
ret = (ret << 8) + getIMR();
|
|
ret = (((uint32_t)getSLIMR()) << 16) | ret;
|
|
return (intr_kind)ret;
|
|
}
|
|
|
|
int8_t wizphy_getphylink() {
|
|
if (wiz_mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON;
|
|
return PHY_LINK_OFF;
|
|
}
|
|
|
|
int8_t wizphy_getphypmode() {
|
|
if (wiz_mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN;
|
|
return PHY_POWER_NORM;
|
|
}
|
|
|
|
void wizphy_reset() {
|
|
wiz_mdio_write(PHYRAR_BMCR, wiz_mdio_read(PHYRAR_BMCR) | BMCR_RST);
|
|
while (wiz_mdio_read(PHYRAR_BMCR) & BMCR_RST);
|
|
}
|
|
|
|
void wizphy_setphyconf(wiz_PhyConf* phyconf) {
|
|
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
|
if (phyconf->mode == PHY_MODE_TE) {
|
|
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
|
setPHYCR0(PHYCR0_AUTO);
|
|
} else {
|
|
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
|
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
|
tmp |= BMCR_ANE;
|
|
} else {
|
|
tmp &= ~(BMCR_ANE | BMCR_DPX | BMCR_SPD);
|
|
if (phyconf->duplex == PHY_DUPLEX_FULL) tmp |= BMCR_DPX;
|
|
if (phyconf->speed == PHY_SPEED_100) tmp |= BMCR_SPD;
|
|
}
|
|
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
|
}
|
|
}
|
|
|
|
void wizphy_getphyconf(wiz_PhyConf* phyconf) {
|
|
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
|
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & BMCR_ANE) ? PHY_MODE_AUTONEGO : PHY_MODE_MANUAL);
|
|
phyconf->duplex = (tmp & BMCR_DPX) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
|
|
phyconf->speed = (tmp & BMCR_SPD) ? PHY_SPEED_100 : PHY_SPEED_10;
|
|
}
|
|
|
|
void wizphy_getphystat(wiz_PhyConf* phyconf) {
|
|
uint8_t tmp = getPHYSR();
|
|
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
|
phyconf->speed = (tmp & PHYSR_SPD) ? PHY_SPEED_10 : PHY_SPEED_100;
|
|
phyconf->duplex = (tmp & PHYSR_DPX) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
|
}
|
|
|
|
void wizphy_setphypmode(uint8_t pmode) {
|
|
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
|
if (pmode == PHY_POWER_DOWN) tmp |= BMCR_PWDN;
|
|
else tmp &= ~BMCR_PWDN;
|
|
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
|
}
|
|
|
|
void wizchip_setnetinfo(wiz_NetInfo* p) {
|
|
setSHAR(p->mac); setGAR(p->gw); setSUBR(p->sn); setSIPR(p->ip);
|
|
setGA6R(p->gw6); setSUB6R(p->sn6); setLLAR(p->lla); setGUAR(p->gua);
|
|
memcpy(dns_, p->dns, 4);
|
|
memcpy(dns6_, p->dns6, 16);
|
|
ipmode_ = p->ipmode;
|
|
}
|
|
|
|
void wizchip_getnetinfo(wiz_NetInfo* p) {
|
|
getSHAR(p->mac); getGAR(p->gw); getSUBR(p->sn); getSIPR(p->ip);
|
|
getGA6R(p->gw6); getSUB6R(p->sn6); getLLAR(p->lla); getGUAR(p->gua);
|
|
memcpy(p->dns, dns_, 4);
|
|
memcpy(p->dns6, dns6_, 16);
|
|
p->ipmode = ipmode_;
|
|
}
|
|
|
|
void wizchip_setnetmode(netmode_type netmode) {
|
|
uint32_t tmp = (uint32_t)netmode;
|
|
setNETMR((uint8_t)tmp);
|
|
setNETMR2((uint8_t)(tmp >> 8));
|
|
setNET4MR((uint8_t)(tmp >> 16));
|
|
setNET6MR((uint8_t)(tmp >> 24));
|
|
}
|
|
|
|
netmode_type wizchip_getnetmode() {
|
|
uint32_t ret = getNETMR();
|
|
ret = (ret << 8) + getNETMR2();
|
|
ret = (ret << 16) + getNET4MR();
|
|
ret = (ret << 24) + getNET6MR();
|
|
return (netmode_type)ret;
|
|
}
|
|
|
|
void wizchip_settimeout(wiz_NetTimeout* t) {
|
|
setRCR(t->s_retry_cnt); setRTR(t->s_time_100us);
|
|
setSLRCR(t->sl_retry_cnt); setSLRTR(t->sl_time_100us);
|
|
}
|
|
|
|
void wizchip_gettimeout(wiz_NetTimeout* t) {
|
|
t->s_retry_cnt = getRCR(); t->s_time_100us = getRTR();
|
|
t->sl_retry_cnt = getSLRCR(); t->sl_time_100us = getSLRTR();
|
|
}
|
|
|
|
int8_t wizchip_arp(wiz_ARP* arp) {
|
|
uint8_t tmp;
|
|
if (arp->destinfo.len == 16) { setSLDIP6R(arp->destinfo.ip); setSLCR(SLCR_ARP6); }
|
|
else { setSLDIP4R(arp->destinfo.ip); setSLCR(SLCR_ARP4); }
|
|
while (getSLCR());
|
|
while ((tmp = getSLIR()) == 0x00);
|
|
setSLIRCLR(~SLIR_RA);
|
|
if (tmp & (SLIR_ARP4 | SLIR_ARP6)) { getSLDHAR(arp->dha); return 0; }
|
|
return -1;
|
|
}
|
|
|
|
int8_t wizchip_ping(wiz_PING* ping) {
|
|
uint8_t tmp;
|
|
setPINGIDR(ping->id); setPINGSEQR(ping->seq);
|
|
if (ping->destinfo.len == 16) { setSLDIP6R(ping->destinfo.ip); setSLCR(SLCR_PING6); }
|
|
else { setSLDIP4R(ping->destinfo.ip); setSLCR(SLCR_PING4); }
|
|
while (getSLCR());
|
|
while ((tmp = getSLIR()) == 0x00);
|
|
setSLIRCLR(~SLIR_RA);
|
|
if (tmp & (SLIR_PING4 | SLIR_PING6)) return 0;
|
|
return -1;
|
|
}
|
|
|
|
int8_t wizchip_dad(uint8_t* ipv6) {
|
|
uint8_t tmp;
|
|
setSLDIP6R(ipv6); setSLCR(SLCR_NS);
|
|
while (getSLCR());
|
|
while ((tmp = getSLIR()) == 0x00);
|
|
setSLIRCLR(~SLIR_RA);
|
|
if (tmp & SLIR_TOUT) return 0;
|
|
return -1;
|
|
}
|
|
|
|
int8_t wizchip_slaac(wiz_Prefix* prefix) {
|
|
uint8_t tmp;
|
|
setSLCR(SLCR_RS);
|
|
while (getSLCR());
|
|
while ((tmp = getSLIR()) == 0x00);
|
|
setSLIRCLR(~SLIR_RA);
|
|
if (tmp & SLIR_RS) {
|
|
prefix->len = getPLR(); prefix->flag = getPFR();
|
|
prefix->valid_lifetime = getVLTR(); prefix->preferred_lifetime = getPLTR();
|
|
getPAR(prefix->prefix);
|
|
return 0;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
int8_t wizchip_unsolicited() {
|
|
uint8_t tmp;
|
|
setSLCR(SLCR_UNA);
|
|
while (getSLCR());
|
|
while ((tmp = getSLIR()) == 0x00);
|
|
setSLIRCLR(~SLIR_RA);
|
|
if (tmp & SLIR_TOUT) return 0;
|
|
return -1;
|
|
}
|
|
|
|
int8_t wizchip_getprefix(wiz_Prefix* prefix) {
|
|
if (getSLIR() & SLIR_RA) {
|
|
prefix->len = getPLR(); prefix->flag = getPFR();
|
|
prefix->valid_lifetime = getVLTR(); prefix->preferred_lifetime = getPLTR();
|
|
getPAR(prefix->prefix);
|
|
setSLIRCLR(SLIR_RA);
|
|
}
|
|
return -1;
|
|
}
|
|
constexpr uint16_t SOCK_ANY_PORT_NUM = 0xC000;
|
|
|
|
static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
|
|
static uint16_t sock_io_mode = 0;
|
|
static uint16_t sock_is_sending = 0;
|
|
static uint16_t sock_remained_size[_WIZCHIP_SOCK_NUM_] = {0,};
|
|
uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
|
|
|
|
#define CHECK_SOCKNUM() do { if(sn >= _WIZCHIP_SOCK_NUM_) return SOCKERR_SOCKNUM; } while(0)
|
|
#define CHECK_SOCKMODE(mode) do { if((getSn_MR(sn) & 0x0F) != mode) return SOCKERR_SOCKMODE; } while(0)
|
|
#define CHECK_TCPMODE() do { if((getSn_MR(sn) & 0x03) != 0x01) return SOCKERR_SOCKMODE; } while(0)
|
|
#define CHECK_UDPMODE() do { if((getSn_MR(sn) & 0x03) != 0x02) return SOCKERR_SOCKMODE; } while(0)
|
|
#define CHECK_IPMODE() do { if((getSn_MR(sn) & 0x07) != 0x03) return SOCKERR_SOCKMODE; } while(0)
|
|
#define CHECK_DGRAMMODE() do { if(getSn_MR(sn) == Sn_MR_CLOSED) return SOCKERR_SOCKMODE; if((getSn_MR(sn) & 0x03) == 0x01) return SOCKERR_SOCKMODE; } while(0)
|
|
#define CHECK_SOCKINIT() do { if((getSn_SR(sn) != SOCK_INIT)) return SOCKERR_SOCKINIT; } while(0)
|
|
#define CHECK_SOCKDATA() do { if(len == 0) return SOCKERR_DATALEN; } while(0)
|
|
#define CHECK_IPZERO(addr, addrlen) do { uint16_t ipzero=0; for(uint8_t i=0; i<addrlen; i++) ipzero += (uint16_t)addr[i]; if(ipzero == 0) return SOCKERR_IPINVALID; } while(0)
|
|
|
|
int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag) {
|
|
uint8_t taddr[16];
|
|
CHECK_SOCKNUM();
|
|
switch (protocol & 0x0F) {
|
|
case Sn_MR_TCP4:
|
|
getSIPR(taddr);
|
|
CHECK_IPZERO(taddr, 4);
|
|
break;
|
|
case Sn_MR_TCP6:
|
|
getLLAR(taddr);
|
|
CHECK_IPZERO(taddr, 16);
|
|
break;
|
|
case Sn_MR_TCPD:
|
|
getSIPR(taddr);
|
|
CHECK_IPZERO(taddr, 4);
|
|
getLLAR(taddr);
|
|
CHECK_IPZERO(taddr, 16);
|
|
break;
|
|
case Sn_MR_UDP:
|
|
case Sn_MR_UDP6:
|
|
case Sn_MR_UDPD:
|
|
case Sn_MR_MACRAW:
|
|
case Sn_MR_IPRAW4:
|
|
case Sn_MR_IPRAW6:
|
|
break;
|
|
default:
|
|
return SOCKERR_SOCKMODE;
|
|
}
|
|
if ((flag & 0x04) != 0) return SOCKERR_SOCKFLAG;
|
|
|
|
if (flag != 0) {
|
|
switch (protocol) {
|
|
case Sn_MR_MACRAW:
|
|
if ((flag & (SF_DHA_MANUAL | SF_FORCE_ARP)) != 0) return SOCKERR_SOCKFLAG;
|
|
break;
|
|
case Sn_MR_TCP4:
|
|
case Sn_MR_TCP6:
|
|
case Sn_MR_TCPD:
|
|
if ((flag & (SF_MULTI_ENABLE | SF_UNI_BLOCK)) != 0) return SOCKERR_SOCKFLAG;
|
|
break;
|
|
case Sn_MR_IPRAW4:
|
|
case Sn_MR_IPRAW6:
|
|
if (flag != 0) return SOCKERR_SOCKFLAG;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
close(sn);
|
|
setSn_MR(sn, (protocol | (flag & 0xF0)));
|
|
setSn_MR2(sn, flag & 0x03);
|
|
if (!port) {
|
|
port = sock_any_port++;
|
|
if (sock_any_port == 0xFFF0) sock_any_port = SOCK_ANY_PORT_NUM;
|
|
}
|
|
setSn_PORTR(sn, port);
|
|
setSn_CR(sn, Sn_CR_OPEN);
|
|
while (getSn_CR(sn));
|
|
sock_io_mode &= ~(1 << sn);
|
|
sock_io_mode |= ((flag & (SF_IO_NONBLOCK >> 3)) << sn);
|
|
sock_is_sending &= ~(1 << sn);
|
|
sock_remained_size[sn] = 0;
|
|
sock_pack_info[sn] = PACK_COMPLETED;
|
|
while (getSn_SR(sn) == SOCK_CLOSED);
|
|
return (int8_t)sn;
|
|
}
|
|
|
|
int8_t close(uint8_t sn) {
|
|
CHECK_SOCKNUM();
|
|
setSn_CR(sn, Sn_CR_CLOSE);
|
|
while (getSn_CR(sn));
|
|
setSn_IR(sn, 0xFF);
|
|
sock_io_mode &= ~(1 << sn);
|
|
sock_is_sending &= ~(1 << sn);
|
|
sock_remained_size[sn] = 0;
|
|
sock_pack_info[sn] = PACK_NONE;
|
|
while (getSn_SR(sn) != SOCK_CLOSED);
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int8_t listen(uint8_t sn) {
|
|
CHECK_SOCKNUM();
|
|
CHECK_TCPMODE();
|
|
CHECK_SOCKINIT();
|
|
setSn_CR(sn, Sn_CR_LISTEN);
|
|
while (getSn_CR(sn));
|
|
while (getSn_SR(sn) != SOCK_LISTEN) {
|
|
close(sn);
|
|
return SOCKERR_SOCKCLOSED;
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int8_t connect(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen) {
|
|
CHECK_SOCKNUM();
|
|
CHECK_TCPMODE();
|
|
CHECK_SOCKINIT();
|
|
CHECK_IPZERO(addr, addrlen);
|
|
if (port == 0) return SOCKERR_PORTZERO;
|
|
|
|
setSn_DPORTR(sn, port);
|
|
if (addrlen == 16) {
|
|
if (getSn_MR(sn) & 0x08) {
|
|
setSn_DIP6R(sn, addr);
|
|
setSn_CR(sn, Sn_CR_CONNECT6);
|
|
} else {
|
|
return SOCKERR_SOCKMODE;
|
|
}
|
|
} else {
|
|
if (getSn_MR(sn) == Sn_MR_TCP6) return SOCKERR_SOCKMODE;
|
|
setSn_DIPR(sn, addr);
|
|
setSn_CR(sn, Sn_CR_CONNECT);
|
|
}
|
|
while (getSn_CR(sn));
|
|
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
|
while (getSn_SR(sn) != SOCK_ESTABLISHED) {
|
|
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
|
setSn_IR(sn, Sn_IR_TIMEOUT);
|
|
return SOCKERR_TIMEOUT;
|
|
}
|
|
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int8_t disconnect(uint8_t sn) {
|
|
CHECK_SOCKNUM();
|
|
CHECK_TCPMODE();
|
|
if (getSn_SR(sn) != SOCK_CLOSED) {
|
|
setSn_CR(sn, Sn_CR_DISCON);
|
|
while (getSn_CR(sn));
|
|
sock_is_sending &= ~(1 << sn);
|
|
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
|
while (getSn_SR(sn) != SOCK_CLOSED) {
|
|
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
|
close(sn);
|
|
return SOCKERR_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int32_t send(uint8_t sn, uint8_t * buf, uint16_t len) {
|
|
uint8_t tmp = 0;
|
|
uint16_t freesize = 0;
|
|
|
|
freesize = getSn_TxMAX(sn);
|
|
if (len > freesize) len = freesize;
|
|
while (1) {
|
|
freesize = (uint16_t)getSn_TX_FSR(sn);
|
|
tmp = getSn_SR(sn);
|
|
if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT)) {
|
|
if (tmp == SOCK_CLOSED) close(sn);
|
|
return SOCKERR_SOCKSTATUS;
|
|
}
|
|
if ((sock_io_mode & (1 << sn)) && (len > freesize)) return SOCK_BUSY;
|
|
if (len <= freesize) break;
|
|
}
|
|
wiz_send_data(sn, buf, len);
|
|
if (sock_is_sending & (1 << sn)) {
|
|
while (!(getSn_IR(sn) & Sn_IR_SENDOK)) {
|
|
tmp = getSn_SR(sn);
|
|
if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT)) {
|
|
if ((tmp == SOCK_CLOSED) || (getSn_IR(sn) & Sn_IR_TIMEOUT)) close(sn);
|
|
return SOCKERR_SOCKSTATUS;
|
|
}
|
|
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
|
}
|
|
setSn_IR(sn, Sn_IR_SENDOK);
|
|
}
|
|
setSn_CR(sn, Sn_CR_SEND);
|
|
while (getSn_CR(sn));
|
|
sock_is_sending |= (1 << sn);
|
|
return len;
|
|
}
|
|
|
|
int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len) {
|
|
uint8_t tmp = 0;
|
|
uint16_t recvsize = 0;
|
|
|
|
CHECK_SOCKNUM();
|
|
CHECK_SOCKMODE(Sn_MR_TCP);
|
|
CHECK_SOCKDATA();
|
|
|
|
recvsize = getSn_RxMAX(sn);
|
|
if (recvsize < len) len = recvsize;
|
|
|
|
while (1) {
|
|
recvsize = (uint16_t)getSn_RX_RSR(sn);
|
|
tmp = getSn_SR(sn);
|
|
if (tmp != SOCK_ESTABLISHED) {
|
|
if (tmp == SOCK_CLOSE_WAIT) {
|
|
if (recvsize != 0) break;
|
|
else if (getSn_TX_FSR(sn) == getSn_TxMAX(sn)) {
|
|
close(sn);
|
|
return SOCKERR_SOCKSTATUS;
|
|
}
|
|
} else {
|
|
close(sn);
|
|
return SOCKERR_SOCKSTATUS;
|
|
}
|
|
}
|
|
if (recvsize != 0) break;
|
|
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
|
};
|
|
|
|
if (recvsize < len) len = recvsize;
|
|
wiz_recv_data(sn, buf, len);
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
return (int32_t)len;
|
|
}
|
|
|
|
int32_t sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen) {
|
|
uint8_t tmp = 0;
|
|
uint8_t tcmd = Sn_CR_SEND;
|
|
uint16_t freesize = 0;
|
|
|
|
CHECK_SOCKNUM();
|
|
switch (getSn_MR(sn) & 0x0F) {
|
|
case Sn_MR_UDP:
|
|
case Sn_MR_MACRAW:
|
|
case Sn_MR_IPRAW:
|
|
case Sn_MR_IPRAW6:
|
|
break;
|
|
default:
|
|
return SOCKERR_SOCKMODE;
|
|
}
|
|
tmp = getSn_MR(sn);
|
|
if (tmp != Sn_MR_MACRAW) {
|
|
if (addrlen == 16) {
|
|
if (tmp & 0x08) {
|
|
setSn_DIP6R(sn, addr);
|
|
tcmd = Sn_CR_SEND6;
|
|
} else {
|
|
return SOCKERR_SOCKMODE;
|
|
}
|
|
} else if (addrlen == 4) {
|
|
if (tmp == Sn_MR_UDP6 || tmp == Sn_MR_IPRAW6) return SOCKERR_SOCKMODE;
|
|
setSn_DIPR(sn, addr);
|
|
tcmd = Sn_CR_SEND;
|
|
} else {
|
|
return SOCKERR_IPINVALID;
|
|
}
|
|
}
|
|
if ((tmp & 0x03) == 0x02) {
|
|
if (port) {
|
|
setSn_DPORTR(sn, port);
|
|
} else {
|
|
return SOCKERR_PORTZERO;
|
|
}
|
|
}
|
|
|
|
freesize = getSn_TxMAX(sn);
|
|
if (len > freesize) len = freesize;
|
|
while (1) {
|
|
freesize = getSn_TX_FSR(sn);
|
|
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
|
if ((sock_io_mode & (1 << sn)) && (len > freesize)) return SOCK_BUSY;
|
|
if (len <= freesize) break;
|
|
};
|
|
wiz_send_data(sn, buf, len);
|
|
setSn_CR(sn, tcmd);
|
|
while (getSn_CR(sn));
|
|
while (1) {
|
|
tmp = getSn_IR(sn);
|
|
if (tmp & Sn_IR_SENDOK) {
|
|
setSn_IR(sn, Sn_IR_SENDOK);
|
|
break;
|
|
} else if (tmp & Sn_IR_TIMEOUT) {
|
|
setSn_IR(sn, Sn_IR_TIMEOUT);
|
|
return SOCKERR_TIMEOUT;
|
|
}
|
|
}
|
|
return (int32_t)len;
|
|
}
|
|
|
|
int32_t recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen) {
|
|
uint8_t mr;
|
|
uint8_t head[8];
|
|
uint16_t pack_len = 0;
|
|
|
|
CHECK_SOCKNUM();
|
|
CHECK_SOCKDATA();
|
|
|
|
switch ((mr = getSn_MR(sn)) & 0x0F) {
|
|
case Sn_MR_UDP:
|
|
case Sn_MR_IPRAW:
|
|
case Sn_MR_IPRAW6:
|
|
case Sn_MR_MACRAW:
|
|
break;
|
|
default:
|
|
return SOCKERR_SOCKMODE;
|
|
}
|
|
|
|
if (sock_remained_size[sn] == 0) {
|
|
while (1) {
|
|
pack_len = getSn_RX_RSR(sn);
|
|
if (getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
|
|
if (pack_len != 0) {
|
|
sock_pack_info[sn] = PACK_NONE;
|
|
break;
|
|
}
|
|
if (sock_io_mode & (1 << sn)) return SOCK_BUSY;
|
|
};
|
|
}
|
|
|
|
wiz_recv_data(sn, head, 2);
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
pack_len = head[0] & 0x07;
|
|
pack_len = (pack_len << 8) + head[1];
|
|
|
|
switch (mr & 0x07) {
|
|
case Sn_MR_UDP4:
|
|
case Sn_MR_UDP6:
|
|
case Sn_MR_UDPD:
|
|
if (addr == 0) return SOCKERR_ARG;
|
|
sock_pack_info[sn] = head[0] & 0xF8;
|
|
if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16;
|
|
else *addrlen = 4;
|
|
wiz_recv_data(sn, addr, *addrlen);
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
break;
|
|
case Sn_MR_MACRAW:
|
|
if (sock_remained_size[sn] == 0) {
|
|
sock_remained_size[sn] = head[0];
|
|
sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[1] - 2;
|
|
if (sock_remained_size[sn] > 1514) {
|
|
close(sn);
|
|
return SOCKFATAL_PACKLEN;
|
|
}
|
|
sock_pack_info[sn] = PACK_FIRST;
|
|
}
|
|
if (len < sock_remained_size[sn]) pack_len = len;
|
|
else pack_len = sock_remained_size[sn];
|
|
wiz_recv_data(sn, buf, pack_len);
|
|
break;
|
|
case Sn_MR_IPRAW6:
|
|
case Sn_MR_IPRAW4:
|
|
if (sock_remained_size[sn] == 0) {
|
|
if (*addr == 0) return SOCKERR_ARG;
|
|
sock_pack_info[sn] = head[0] & 0xF8;
|
|
if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16;
|
|
else *addrlen = 4;
|
|
wiz_recv_data(sn, addr, *addrlen);
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
}
|
|
break;
|
|
default:
|
|
wiz_recv_ignore(sn, pack_len);
|
|
sock_remained_size[sn] = pack_len;
|
|
break;
|
|
}
|
|
|
|
sock_remained_size[sn] = pack_len;
|
|
sock_pack_info[sn] |= PACK_FIRST;
|
|
if ((getSn_MR(sn) & 0x03) == 0x02) {
|
|
if (port == 0) return SOCKERR_ARG;
|
|
wiz_recv_data(sn, head, 2);
|
|
*port = (((uint16_t)head[0]) << 8) + head[1];
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
}
|
|
|
|
if (len < sock_remained_size[sn]) pack_len = len;
|
|
else pack_len = sock_remained_size[sn];
|
|
wiz_recv_data(sn, buf, pack_len);
|
|
setSn_CR(sn, Sn_CR_RECV);
|
|
while (getSn_CR(sn));
|
|
|
|
sock_remained_size[sn] -= pack_len;
|
|
if (sock_remained_size[sn] != 0) sock_pack_info[sn] |= PACK_REMAINED;
|
|
else sock_pack_info[sn] |= PACK_COMPLETED;
|
|
|
|
return (int32_t)pack_len;
|
|
}
|
|
|
|
int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg) {
|
|
uint8_t tmp = 0;
|
|
CHECK_SOCKNUM();
|
|
tmp = *((uint8_t*)arg);
|
|
switch (cstype) {
|
|
case CS_SET_IOMODE:
|
|
if (tmp == SOCK_IO_NONBLOCK) sock_io_mode |= (1 << sn);
|
|
else if (tmp == SOCK_IO_BLOCK) sock_io_mode &= ~(1 << sn);
|
|
else return SOCKERR_ARG;
|
|
break;
|
|
case CS_GET_IOMODE:
|
|
*((uint8_t*)arg) = (uint8_t)((sock_io_mode >> sn) & 0x0001);
|
|
break;
|
|
case CS_GET_MAXTXBUF:
|
|
*((uint16_t*)arg) = getSn_TxMAX(sn);
|
|
break;
|
|
case CS_GET_MAXRXBUF:
|
|
*((uint16_t*)arg) = getSn_RxMAX(sn);
|
|
break;
|
|
case CS_CLR_INTERRUPT:
|
|
if (tmp > SIK_ALL) return SOCKERR_ARG;
|
|
setSn_IR(sn, tmp);
|
|
break;
|
|
case CS_GET_INTERRUPT:
|
|
*((uint8_t*)arg) = getSn_IR(sn);
|
|
break;
|
|
case CS_SET_INTMASK:
|
|
if (tmp > SIK_ALL) return SOCKERR_ARG;
|
|
setSn_IMR(sn, tmp);
|
|
break;
|
|
case CS_GET_INTMASK:
|
|
*((uint8_t*)arg) = getSn_IMR(sn);
|
|
break;
|
|
case CS_SET_PREFER:
|
|
if ((tmp & 0x03) == 0x01) return SOCKERR_ARG;
|
|
setSn_PSR(sn, tmp);
|
|
break;
|
|
case CS_GET_PREFER:
|
|
*(uint8_t*)arg = getSn_PSR(sn);
|
|
break;
|
|
default:
|
|
return SOCKERR_ARG;
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg) {
|
|
CHECK_SOCKNUM();
|
|
switch (sotype) {
|
|
case SO_TTL:
|
|
setSn_TTL(sn, *(uint8_t*)arg);
|
|
break;
|
|
case SO_TOS:
|
|
setSn_TOS(sn, *(uint8_t*)arg);
|
|
break;
|
|
case SO_MSS:
|
|
setSn_MSSR(sn, *(uint16_t*)arg);
|
|
break;
|
|
case SO_DESTIP:
|
|
if (((wiz_IPAddress *)arg)->len == 16) setSn_DIP6R(sn, ((wiz_IPAddress*)arg)->ip);
|
|
else setSn_DIPR(sn, (uint8_t*)arg);
|
|
break;
|
|
case SO_DESTPORT:
|
|
setSn_DPORTR(sn, *(uint16_t*)arg);
|
|
break;
|
|
case SO_KEEPALIVESEND:
|
|
CHECK_TCPMODE();
|
|
if (getSn_KPALVTR(sn) != 0) return SOCKERR_SOCKOPT;
|
|
setSn_CR(sn, Sn_CR_SEND_KEEP);
|
|
while (getSn_CR(sn) != 0) {
|
|
if (getSn_IR(sn) & Sn_IR_TIMEOUT) {
|
|
setSn_IR(sn, Sn_IR_TIMEOUT);
|
|
return SOCKERR_TIMEOUT;
|
|
}
|
|
}
|
|
break;
|
|
case SO_KEEPALIVEAUTO:
|
|
CHECK_TCPMODE();
|
|
setSn_KPALVTR(sn, *(uint8_t*)arg);
|
|
break;
|
|
default:
|
|
return SOCKERR_ARG;
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg) {
|
|
CHECK_SOCKNUM();
|
|
switch (sotype) {
|
|
case SO_FLAG:
|
|
*(uint8_t*)arg = (getSn_MR(sn) & 0xF0) | (getSn_MR2(sn)) | ((uint8_t)(((sock_io_mode >> sn) & 0x0001) << 3));
|
|
break;
|
|
case SO_TTL:
|
|
*(uint8_t*)arg = getSn_TTL(sn);
|
|
break;
|
|
case SO_TOS:
|
|
*(uint8_t*)arg = getSn_TOS(sn);
|
|
break;
|
|
case SO_MSS:
|
|
*(uint16_t*)arg = getSn_MSSR(sn);
|
|
break;
|
|
case SO_DESTIP:
|
|
CHECK_TCPMODE();
|
|
if (getSn_ESR(sn) & TCPSOCK_MODE) {
|
|
getSn_DIP6R(sn, ((wiz_IPAddress*)arg)->ip);
|
|
((wiz_IPAddress*)arg)->len = 16;
|
|
} else {
|
|
getSn_DIPR(sn, ((wiz_IPAddress*)arg)->ip);
|
|
((wiz_IPAddress*)arg)->len = 4;
|
|
}
|
|
break;
|
|
case SO_DESTPORT:
|
|
*(uint16_t*)arg = getSn_DPORTR(sn);
|
|
break;
|
|
case SO_KEEPALIVEAUTO:
|
|
CHECK_TCPMODE();
|
|
*(uint16_t*)arg = getSn_KPALVTR(sn);
|
|
break;
|
|
case SO_SENDBUF:
|
|
*(uint16_t*)arg = getSn_TX_FSR(sn);
|
|
break;
|
|
case SO_RECVBUF:
|
|
*(uint16_t*)arg = getSn_RX_RSR(sn);
|
|
break;
|
|
case SO_STATUS:
|
|
*(uint8_t*)arg = getSn_SR(sn);
|
|
break;
|
|
case SO_EXTSTATUS:
|
|
CHECK_TCPMODE();
|
|
*(uint8_t*)arg = getSn_ESR(sn) & 0x07;
|
|
break;
|
|
case SO_REMAINSIZE:
|
|
if (getSn_MR(sn) == SOCK_CLOSED) return SOCKERR_SOCKSTATUS;
|
|
if (getSn_MR(sn) & 0x01) *(uint16_t*)arg = getSn_RX_RSR(sn);
|
|
else *(uint16_t*)arg = sock_remained_size[sn];
|
|
break;
|
|
case SO_PACKINFO:
|
|
if (getSn_MR(sn) == SOCK_CLOSED) return SOCKERR_SOCKSTATUS;
|
|
if (getSn_MR(sn) & 0x01) return SOCKERR_SOCKMODE;
|
|
else *(uint8_t*)arg = sock_pack_info[sn];
|
|
break;
|
|
case SO_MODE:
|
|
*(uint8_t*)arg = 0x0F & getSn_MR(sn);
|
|
break;
|
|
default:
|
|
return SOCKERR_SOCKOPT;
|
|
}
|
|
return SOCK_OK;
|
|
}
|
|
|
|
int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize) {
|
|
uint32_t rx_ptr = 0;
|
|
uint16_t i = 0, sub_idx = 0;
|
|
if ((getSn_RX_RSR(sn) > 0) && (subsize > 0)) {
|
|
rx_ptr = ((uint32_t)getSn_RX_RD(sn) << 8) + WIZCHIP_RXBUF_BLOCK(sn);
|
|
sub_idx = 0;
|
|
for (i = 0; i < getSn_RX_RSR(sn); i++) {
|
|
if (WIZCHIP_READ(rx_ptr) == submsg[sub_idx]) {
|
|
sub_idx++;
|
|
if (sub_idx == subsize) return (i + 1 - sub_idx);
|
|
} else {
|
|
sub_idx = 0;
|
|
}
|
|
rx_ptr = WIZCHIP_OFFSET_INC(rx_ptr, 1);
|
|
}
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
void wizchip_reset() {
|
|
gpio_init(PIN_RST);
|
|
gpio_set_dir(PIN_RST, GPIO_OUT);
|
|
gpio_put(PIN_RST, 0);
|
|
sleep_ms(100);
|
|
gpio_put(PIN_RST, 1);
|
|
sleep_ms(100);
|
|
}
|
|
|
|
void wizchip_spi_initialize() {
|
|
wizchip_pio_init();
|
|
}
|
|
|
|
void wizchip_cris_initialize() {
|
|
critical_section_init(&g_cris_sec);
|
|
}
|
|
|
|
void wizchip_initialize() {
|
|
wizchip_pio_frame_end();
|
|
uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}};
|
|
ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize);
|
|
}
|
|
|
|
bool wizchip_check() {
|
|
return getCIDR() == 0x6300;
|
|
}
|
|
|
|
void network_initialize(wiz_NetInfo net_info) {
|
|
uint8_t syslock = SYS_NET_LOCK;
|
|
ctlwizchip(CW_SYS_UNLOCK, &syslock);
|
|
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
|
}
|