#ifndef      _W6300_H_
#define      _W6300_H_

#include <stdint.h>
#include "wizchip_conf.h"


#ifdef __cplusplus
extern "C" {
#endif


#define _W6300_SPI_READ_                  (0x00 << 5)        ///< SPI interface Read operation in Control Phase
#define _W6300_SPI_WRITE_                 (0x01 << 5)        ///< SPI interface Write operation in Control Phase

#define WIZCHIP_CREG_BLOCK                (0x00   )       ///< Common register block
#define WIZCHIP_SREG_BLOCK(N)             ((1+4*N))       ///< SOCKETn register block
#define WIZCHIP_TXBUF_BLOCK(N)            ((2+4*N))       ///< SOCKETn Tx buffer address block
#define WIZCHIP_RXBUF_BLOCK(N)            ((3+4*N))       ///< SOCKETn Rx buffer address block

#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) ///< Increase offset address

#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
#define IDM_AR0                        ((_WIZCHIP_IO_BASE_ + 0x0000))      ///< Indirect High Address Register
#define IDM_AR1                        ((_WIZCHIP_IO_BASE_ + 0x0001))      ///< Indirect Low Address Register
#define IDM_BSR                        ((_WIZCHIP_IO_BASE_ + 0x0002))      ///< Block Select Register
#define IDM_DR                         ((_WIZCHIP_IO_BASE_ + 0x0003))      ///< Indirect Data Register
#define _W6300_IO_BASE_       _WIZCHIP_IO_BASE_
#elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
#define IDM_AR0                        ((_WIZCHIP_IO_BASE_ + 0x0000))      ///< Indirect High Address Register
#define IDM_AR1                        ((_WIZCHIP_IO_BASE_ + 0x0001))      ///< Indirect Low Address Register
#define IDM_BSR                        ((_WIZCHIP_IO_BASE_ + 0x0002))      ///< Block Select Register
#define IDM_DR                         ((_WIZCHIP_IO_BASE_ + 0x0003))      ///< Indirect Data Register
#define _W6300_IO_BASE_       0x00000000
#define _W6100_IO_BASE_       0x00000000
#endif


#define _CIDR_               (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTL_                (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_CREG_BLOCK)
#define _VER_                (_W6300_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYSR_               (_W6300_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYCR0_              (_W6300_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)

#define _SYCR1_              (WIZCHIP_OFFSET_INC(_SYCR0_,1))
#define _TCNTR_              (_W6300_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)
#define _TCNTRCLR_           (_W6300_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)
#define _IR_                 (_W6300_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIR_                (_W6300_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIR_               (_W6300_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)
#define _IMR_                (_W6300_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)
#define _IRCLR_              (_W6300_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIMR_               (_W6300_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIMR_              (_W6300_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIRCLR_            (_W6300_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLPSR_              (_W6300_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLCR_               (_W6300_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYSR_              (_W6300_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYRAR_             (_W6300_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIR_             (_W6300_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDOR_             (_W6300_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYACR_             (_W6300_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIVR_            (_W6300_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYCR0_             (_W6300_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYCR1_             WIZCHIP_OFFSET_INC(_PHYCR0_,1)
#define _NET4MR_             (_W6300_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)
#define _NET6MR_             (_W6300_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR_              (_W6300_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR2_             (_W6300_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)
#define _PTMR_               (_W6300_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMNR_               (_W6300_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHAR_               (_W6300_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)
#define _PSIDR_              (_W6300_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMRUR_              (_W6300_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SHAR_               (_W6300_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)
#define _GAR_                (_W6300_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)
#define _GA4R_               (_GAR_)
#define _SUBR_               (_W6300_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUB4R_              (_SUBR_)

#define _SIPR_               (_W6300_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIP4R_              (_SIPR_)
#define _LLAR_               (_W6300_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)
#define _GUAR_               (_W6300_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUB6R_              (_W6300_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)
#define _GA6R_               (_W6300_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIP6R_            (_W6300_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIPR_             (_W6300_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIP4R_            (_SLDIPR_)
#define _SLDHAR_             (_W6300_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGIDR_            (_W6300_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGSEQR_           (_W6300_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)
#define _UIPR_               (_W6300_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
#define _UIP4R_              (_UIPR_)
#define _UPORTR_             (_W6300_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORT4R_            (_UPORTR_)
#define _UIP6R_              (_W6300_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORT6R_            (_W6300_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
#define _INTPTMR_            (_W6300_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLR_                (_W6300_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
#define _PFR_                (_W6300_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
#define _VLTR_               (_W6300_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLTR_               (_W6300_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)
#define _PAR_                (_W6300_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
#define _ICMP6BLKR_          (_W6300_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
#define _CHPLCKR_            (_W6300_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETLCKR_            (_W6300_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYLCKR_            (_W6300_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTR_                (_W6300_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)
#define _RCR_                (_W6300_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRTR_              (_W6300_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRCR_              (_W6300_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLHOPR_             (_W6300_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)

#define _Sn_MR_(N)           (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PSR_(N)          (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_CR_(N)           (_W6300_IO_BASE_ + (0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IR_(N)           (_W6300_IO_BASE_ + (0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IMR_(N)          (_W6300_IO_BASE_ + (0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IRCLR_(N)        (_W6300_IO_BASE_ + (0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))



#define _Sn_SR_(N)           (_W6300_IO_BASE_ + (0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_ESR_(N)          (_W6300_IO_BASE_ + (0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PNR_(N)          (_W6300_IO_BASE_ + (0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_NHR_(N)          (_Sn_PNR_(N))
#define _Sn_TOSR_(N)         (_W6300_IO_BASE_ + (0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TTLR_(N)         (_W6300_IO_BASE_ + (0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_HOPR_(N)         (_Sn_TTLR_(N))
#define _Sn_FRGR_(N)         (_W6300_IO_BASE_ + (0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MSSR_(N)         (_W6300_IO_BASE_ + (0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PORTR_(N)        (_W6300_IO_BASE_ + (0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DHAR_(N)         (_W6300_IO_BASE_ + (0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIPR_(N)         (_W6300_IO_BASE_ + (0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIP4R_(N)        (_Sn_DIPR_(N))
#define _Sn_DIP6R_(N)        (_W6300_IO_BASE_ + (0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DPORTR_(N)       (_W6300_IO_BASE_ + (0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MR2_(N)          (_W6300_IO_BASE_ + (0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RTR_(N)          (_W6300_IO_BASE_ + (0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RCR_(N)          (_W6300_IO_BASE_ + (0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_KPALVTR_(N)      (_W6300_IO_BASE_ + (0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_BSR_(N)       (_W6300_IO_BASE_ + (0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_FSR_(N)       (_W6300_IO_BASE_ + (0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_RD_(N)        (_W6300_IO_BASE_ + (0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_WR_(N)        (_W6300_IO_BASE_ + (0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_BSR_(N)       (_W6300_IO_BASE_ + (0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RSR_(N)       (_W6300_IO_BASE_ + (0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RD_(N)        (_W6300_IO_BASE_ + (0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_WR_(N)        (_W6300_IO_BASE_ + (0x022C << 8) + WIZCHIP_SREG_BLOCK(N))

#define SYSR_CHPL            (1 << 7)
#define SYSR_NETL            (1 << 6)
#define SYSR_PHYL            (1 << 5)

#define SYSR_IND             (1 << 5)
#define SYSR_SPI             (1 << 0)
#define SYCR0_RST            (0x00)
#define SYCR1_IEN            (1 << 7)
#define SYCR1_CLKSEL         (1 << 0)
#define SYCR1_CLKSEL_25M     1
#define SYCR1_CLKSEL_100M    0
#define IR_WOL               (1<<7)
#define IR_UNR6              (1<<4)
#define IR_IPCONF            (1<<2)
#define IR_UNR4              (1<<1)
#define IR_PTERM             (1<<0)
#define SIR_INT(N)           (1<<N)
#define SLIR_TOUT            (1<<7)
#define SLIR_ARP4            (1<<6)
#define SLIR_PING4           (1<<5)
#define SLIR_ARP6            (1<<4)
#define SLIR_PING6           (1<<3)
#define SLIR_NS              (1<<2)
#define SLIR_RS              (1<<1)
#define SLIR_RA              (1<<0)
#define PSR_AUTO             (0x00)
#define PSR_LLA              (0x02)
#define PSR_GUA              (0x03)
#define SLCR_ARP4            (1<<6)
#define SLCR_PING4           (1<<5)
#define SLCR_ARP6            (1<<4)
#define SLCR_PING6           (1<<3)
#define SLCR_NS              (1<<2)
#define SLCR_RS              (1<<1)
#define SLCR_UNA             (1<<0)
#define PHYSR_CAB            (1<<7)
#define PHYSR_CAB_OFF        (1<<7)
#define PHYSR_CAB_ON         (0<<7)
#define PHYSR_MODE           (7<<3)
#define PHYSR_MODE_AUTO      (0<<3)

#define PHYSR_MODE_100F      (4<<3)
#define PHYSR_MODE_100H      (5<<3)
#define PHYSR_MODE_10F       (6<<3)
#define PHYSR_MODE_10H       (7<<3)
#define PHYSR_DPX            (1<<2)
#define PHYSR_DPX_HALF       (1<<2)
#define PHYSR_DPX_FULL       (0<<2)
#define PHYSR_SPD            (1<<1)
#define PHYSR_SPD_10M        (1<<1)
#define PHYSR_SPD_100M       (0<<1)
#define PHYSR_LNK            (1<<0)
#define PHYSR_LNK_UP         (1<<0)
#define PHYSR_LNK_DOWN       (0<<0)
#define PHYACR_READ          (0x02)
#define PHYACR_WRITE         (0x01)
#define PHYDIVR_32           (0x00)
#define PHYDIVR_64           (0x01)
#define PHYDIVR_128          (0xFF)
#define PHYCR0_AUTO          (0x00)
#define PHYCR0_100F          (0x04)
#define PHYCR0_100H          (0x05)
#define PHYCR0_10F           (0x06)
#define PHYCR0_10H           (0x07)
#define PHYCR1_PWDN          (1<<5)
#define PHYCR1_TE            (1<<3)
#define PHYCR1_RST           (1<<0)
#define NETxMR_UNRB          (1<<3)
#define NETxMR_PARP          (1<<2)
#define NETxMR_RSTB          (1<<1)
#define NETxMR_PB            (1<<0)
#define NETMR_ANB            (1<<5)
#define NETMR_M6B            (1<<4)
#define NETMR_WOL            (1<<2)
#define NETMR_IP6B           (1<<1)
#define NETMR_IP4B           (1<<0)
#define NETMR2_DHAS          (1<<7)
#define NETMR2_DHAS_ARP      (1<<7)
#define NETMR2_DHAS_ETH      (0<<7)
#define NETMR2_PPPoE         (1<<0)
#define ICMP6BLKR_PING6      (1<<4)
#define ICMP6BLKR_MLD        (1<<3)
#define ICMP6BLKR_RA         (1<<2)
#define ICMP6BLKR_NA         (1<<1)
#define ICMP6BLKR_NS         (1<<0)
#define Sn_MR_MULTI          (1<<7)
#define Sn_MR_MF             (1<<7)
#define Sn_MR_BRDB           (1<<6)
#define Sn_MR_FPSH           (1<<6)
#define Sn_MR_ND             (1<<5)
#define Sn_MR_MC             (1<<5)
#define Sn_MR_SMB            (1<<5)
#define Sn_MR_MMB            (1<<5)
#define Sn_MR_MMB4           (Sn_MR_MMB)
#define Sn_MR_UNIB           (1<<4)
#define Sn_MR_MMB6           (1<<4)
#define Sn_MR_CLOSE          (0x00)
#define Sn_MR_TCP            (0x01)
#define Sn_MR_TCP4           (Sn_MR_TCP)
#define Sn_MR_UDP            (0x02)
#define Sn_MR_UDP4           (Sn_MR_UDP)
#define Sn_MR_IPRAW          (0x03)
#define Sn_MR_IPRAW4         (Sn_MR_IPRAW)
#define Sn_MR_MACRAW         (0x07)
#define Sn_MR_TCP6           (0x09)
#define Sn_MR_UDP6           (0x0A)
#define Sn_MR_IPRAW6         (0x0B)
#define Sn_MR_TCPD           (0x0D)
#define Sn_MR_UDPD           (0x0E)
#define Sn_CR_OPEN           (0x01)
#define Sn_CR_LISTEN         (0x02)
#define Sn_CR_CONNECT        (0x04)
#define Sn_CR_CONNECT6       (0x84)
#define Sn_CR_DISCON         (0x08)
#define Sn_CR_CLOSE          (0x10)
#define Sn_CR_SEND           (0x20)
#define Sn_CR_SEND6          (0xA0)
#define Sn_CR_SEND_KEEP      (0x22)
#define Sn_CR_RECV           (0x40)
#define Sn_IR_SENDOK         (0x10)
#define Sn_IR_TIMEOUT        (0x08)
#define Sn_IR_RECV           (0x04)
#define Sn_IR_DISCON         (0x02)
#define Sn_IR_CON            (0x01)
#define SOCK_CLOSED          (0x00)
#define SOCK_INIT            (0x13)
#define SOCK_LISTEN          (0x14)
#define SOCK_SYNSENT         (0x15)
#define SOCK_SYNRECV         (0x16)
#define SOCK_ESTABLISHED     (0x17)
#define SOCK_FIN_WAIT        (0x18)

#define SOCK_TIME_WAIT       (0x1B)
#define SOCK_CLOSE_WAIT      (0x1C)
#define SOCK_LAST_ACK        (0x1D)
#define SOCK_UDP             (0x22)
#define SOCK_IPRAW4          (0x32)
#define SOCK_IPRAW           (SOCK_IPRAW4)
#define SOCK_IPRAW6          (0x33)
#define SOCK_MACRAW          (0x42)
#define Sn_ESR_TCPM          (1<<2)
#define Sn_ESR_TCPM_IPV4     (0<<2)
#define Sn_ESR_TCPM_IPV6     (1<<2)
#define Sn_ESR_TCPOP         (1<<1)
#define Sn_ESR_TCPOP_SVR     (0<<1)
#define Sn_ESR_TCPOP_CLT     (1<<1)
#define Sn_ESR_IP6T          (1<<0)
#define Sn_ESR_IP6T_LLA      (0<<0)
#define Sn_ESR_IP6T_GUA      (1<<0)
#define Sn_MR2_DHAM          (1<<1)
#define Sn_MR2_DHAM_AUTO     (0<<1)
#define Sn_MR2_DHAM_MANUAL   (1<<1)
#define Sn_MR2_FARP          (1<<0)
#define PHYRAR_BMCR          (0x00)
#define PHYRAR_BMSR          (0x01)
#define BMCR_RST             (1<<15)
#define BMCR_LB              (1<<14)
#define BMCR_SPD             (1<<13)
#define BMCR_ANE             (1<<12)
#define BMCR_PWDN            (1<<11)
#define BMCR_ISOL            (1<<10)
#define BMCR_REAN            (1<<9)
#define BMCR_DPX             (1<<8)
#define BMCR_COLT            (1<<7)
#define BMSR_100_T4          (1<<15)
#define BMSR_100_FDX         (1<<14)
#define BMSR_100_HDX         (1<<13)
#define BMSR_10_FDX          (1<<12)
#define BMSR_10_HDX          (1<<11)
#define BMSR_MF_SUP          (1<<6)
#define BMSR_AN_COMP         (1<<5)
#define BMSR_REMOTE_FAULT    (1<<4)
#define BMSR_AN_ABILITY      (1<<3)
#define BMSR_LINK_STATUS     (1<<2)
#define BMSR_JABBER_DETECT   (1<<1)
#define BMSR_EXT_CAPA        (1<<0)


#define WIZCHIP_CRITICAL_ENTER()       WIZCHIP.CRIS._enter()
#define WIZCHIP_CRITICAL_EXIT()        WIZCHIP.CRIS._exit()

uint8_t WIZCHIP_READ(uint32_t AddrSel);
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);

#define getRTL() \
        WIZCHIP_READ(_RTL_)

#define getCIDR() \
        ((((uint16_t)WIZCHIP_READ(_CIDR_)| (((WIZCHIP_READ(_RTL_))&0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_,1)))

#define getVER() \
        ((((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_,1)))

#define getSYSR() \
        WIZCHIP_READ(_SYSR_)

#define getSYCR0() \
        WIZCHIP_READ(_SYCR0_)

#define setSYCR0(sycr0) \
        WIZCHIP_WRITE(_SYCR0_, (sycr0))

#define getSYCR1() \
        WIZCHIP_READ(_SYCR1_)

#define setSYCR1(sycr1) \
        WIZCHIP_WRITE(_SYCR1_, (sycr1))

#define getTCNTR() \
        ((((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_,1)))

#define setTCNTRCLR(tcntrclr) \
        WIZCHIP_WRITE(_TCNTRCLR_,(tcntrclr))

#define getIR() \
        WIZCHIP_READ(_IR_)

#define getSIR() \
        WIZCHIP_READ(_SIR_)

#define getSLIR() \
        WIZCHIP_READ(_SLIR_)

#define setIMR(imr) \
        WIZCHIP_WRITE(_IMR_,(imr))

#define getIMR() \
        WIZCHIP_READ(_IMR_)

#define setIRCLR(irclr) \
        WIZCHIP_WRITE(_IRCLR_,(irclr))
#define setIR(ir)                setIRCLR(ir)

#define setSIMR(simr) \
        WIZCHIP_WRITE(_SIMR_,(simr))

#define getSIMR() \
        WIZCHIP_READ(_SIMR_)

#define setSLIMR(slimr) \
        WIZCHIP_WRITE(_SLIMR_,(slimr))

#define getSLIMR() \
        WIZCHIP_READ(_SLIMR_)

#define setSLIRCLR(slirclr) \
        WIZCHIP_WRITE(_SLIRCLR_,(slirclr))
#define setSLIR(slir)            setSLIRCLR(slir)

#define setSLPSR(slpsr) \
        WIZCHIP_WRITE(_SLPSR_,(slpsr))

#define getSLPSR() \
        WIZCHIP_READ(_SLPSR_)

#define setSLCR(slcr) \
        WIZCHIP_WRITE(_SLCR_,(slcr))

#define getSLCR()      \
        WIZCHIP_READ(_SLCR_)

#define getPHYSR() \
        WIZCHIP_READ(_PHYSR_)

#define setPHYRAR(phyrar) \
        WIZCHIP_WRITE(_PHYRAR_,(phyrar))

#define getPHYRAR() \
        WIZCHIP_READ(_PHYRAR_)

#define setPHYDIR(phydir)  \
        do{                                                                       \
           WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_,1), (uint8_t)((phydir)>>8)); \
           WIZCHIP_WRITE(_PHYDIR_, (uint8_t)(phydir));                            \
        }while(0);

#define getPHYDOR() \
        ((((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_,1))) << 8) + WIZCHIP_READ(_PHYDOR_))

#define setPHYACR(phyacr) \
        WIZCHIP_WRITE(_PHYACR_,(phyacr))

#define getPHYACR() \
        WIZCHIP_READ(_PHYACR_)

#define setPHYDIVR(phydivr) \
        WIZCHIP_WRITE(_PHYDIVR_,(phydivr))

#define getPHYDIVR() \
        WIZCHIP_READ(_PHYDIVR_)

#define setPHYCR0(phycr0) \
        WIZCHIP_WRITE(_PHYCR0_,(phycr0))

#define setPHYCR1(phycr1) \
        WIZCHIP_WRITE(_PHYCR1_,(phycr1))

#define getPHYCR1() \
        WIZCHIP_READ(_PHYCR1_)

#define setNET4MR(net4mr) \
        WIZCHIP_WRITE(_NET4MR_,(net4mr))

#define setNET6MR(net6mr) \
        WIZCHIP_WRITE(_NET6MR_,(net6mr))

#define setNETMR(netmr) \
        WIZCHIP_WRITE(_NETMR_,(netmr))

#define setNETMR2(netmr2) \
        WIZCHIP_WRITE(_NETMR2_,(netmr2))

#define getNET4MR() \
        WIZCHIP_READ(_NET4MR_)

#define getNET6MR() \
        WIZCHIP_READ(_NET6MR_)

#define getNETMR() \
        WIZCHIP_READ(_NETMR_)

#define getNETMR2() \
        WIZCHIP_READ(_NETMR2_)

#define setPTMR(ptmr) \
        WIZCHIP_WRITE(_PTMR_, (ptmr))

#define getPTMR() \
        WIZCHIP_READ(_PTMR_)

#define setPMNR(pmnr) \
        WIZCHIP_WRITE(_PMNR_, (pmnr))

#define getPMNR() \
        WIZCHIP_READ(_PMNR_)

#define setPHAR(phar) \
        WIZCHIP_WRITE_BUF(_PHAR_,(phar),6)

#define getPHAR(phar) \
        WIZCHIP_READ_BUF(_PHAR_,(phar),6)

#define setPSIDR(psidr) \
        do{                                                                \
            WIZCHIP_WRITE(_PSIDR_,(uint8_t)((psidr) >> 8));                \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_,1),(uint8_t)(psidr)); \
        }while(0);

#define getPSIDR() \
        ((((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_,1)))

#define setPMRUR(pmrur) \
        do{                                                                \
            WIZCHIP_WRITE(_PMRUR_,(uint8_t)((pmrur) >> 8));                \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_,1),(uint8_t)(pmrur)); \
        }while(0);

#define getPMRUR() \
        ((((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_,1)))

#define setSHAR(shar) \
        WIZCHIP_WRITE_BUF(_SHAR_,(shar),6)

#define getSHAR(shar) \
        WIZCHIP_READ_BUF(_SHAR_,(shar),6)

#define setGAR(gar) \
        WIZCHIP_WRITE_BUF(_GAR_,(gar),4)

#define getGAR(gar) \
        WIZCHIP_READ_BUF(_GAR_,(gar),4)

#define setGA4R(ga4r)            setGAR(ga4r)
#define getGA4R(ga4r)            getGAR(ga4r)

#define setSUBR(subr) \
        WIZCHIP_WRITE_BUF(_SUBR_,(subr),4)

#define getSUBR(subr) \
        WIZCHIP_READ_BUF(_SUBR_,(subr),4)

#define setSUB4R(sub4r)          setSUBR(sub4r)
#define getSUB4R(sub4r)          getSUBR(sub4r)

#define setSIPR(sipr) \
        WIZCHIP_WRITE_BUF(_SIPR_,(sipr),4)

#define getSIPR(sipr) \
        WIZCHIP_READ_BUF(_SIPR_,(sipr),4)

#define setLLAR(llar) \
        WIZCHIP_WRITE_BUF(_LLAR_,(llar),16)

#define getLLAR(llar) \
        WIZCHIP_READ_BUF(_LLAR_,(llar),16)

#define setGUAR(guar) \
        WIZCHIP_WRITE_BUF(_GUAR_,(guar),16)

#define getGUAR(guar) \
        WIZCHIP_READ_BUF(_GUAR_,(guar),16)

#define setSUB6R(sub6r) \
        WIZCHIP_WRITE_BUF(_SUB6R_,(sub6r),16)

#define getSUB6R(sub6r) \
        WIZCHIP_READ_BUF(_SUB6R_,(sub6r),16)

#define setGA6R(ga6r) \
        WIZCHIP_WRITE_BUF(_GA6R_,(ga6r),16)

#define getGA6R(ga6r) \
        WIZCHIP_READ_BUF(_GA6R_,(ga6r),16)

#define setSLDIPR(sldipr) \
        WIZCHIP_WRITE_BUF(_SLDIPR_,(sldipr),4)
#define setSLDIP4R(sldip4r)      setSLDIPR((sldip4r))

#define getSLDIPR(sldipr) \
        WIZCHIP_READ_BUF(_SLDIPR_,(sldipr),4)
#define getSLDIP4R(sldip4r)      getSLDIPR((sldip4r))

#define setSLDIP6R(sldip6r) \
        WIZCHIP_WRITE_BUF(_SLDIP6R_, (sldip6r),16)

#define getSLDIP6R(sldip6r) \
        WIZCHIP_READ_BUF(_SLDIP6R_,(sldip6r),16)

#define getSLDHAR(sldhar) \
        WIZCHIP_READ_BUF(_SLDHAR_,(sldhar),6)

#define setPINGIDR(pingidr) \
        do{                                                                    \
            WIZCHIP_WRITE(_PINGIDR_,(uint8_t)((pingidr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_,1),(uint8_t)(pingidr)); \
        }while(0);

#define getPINGIDR() \
        (((int16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_,1)))

#define setPINGSEQR(pingseqr) \
        do{                                                                      \
            WIZCHIP_WRITE(_PINGSEQR_,(uint8_t)((pingseqr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_,1),(uint8_t)(pingseqr)); \
        }while(0);

#define getPINGSEQR() \
        (((int16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_,1)))

#define getUIPR(uipr) \
        WIZCHIP_READ_BUF(_UIPR_, (uipr), 4)

#define getUIP4R(uip4r)          getUIPR(uip4r)

#define getUPORTR() \
        ((((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_,1)))

#define getUPORT4R()             getUPORTR()

#define getUIP6R(uip6r) \
        WIZCHIP_READ_BUF(_UIP6R_,(uip6r),16)

#define getUPORT6R(uport6r) \
        ((((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_,1)))

#define setINTPTMR(intptmr) \
        do{                                                                     \
            WIZCHIP_WRITE(_INTPTMR_,(uint8_t)((intptmr) >> 8));                 \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_,1),(uint8_t)(intptmr));  \
       }while(0);

#define getINTPTMR() \
        ((((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_,1)))

#define getPLR() \
        WIZCHIP_READ(_PLR_)

#define getPFR() \
        WIZCHIP_READ(_PFR_)

#define getVLTR() \
        ( (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) +                       \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,1))) << 16) + \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,2))) << 16) + \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,3))) << 16) )

#define getPLTR() \
        ( (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) +                       \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,1))) << 16) + \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,2))) << 16) + \
          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,3))) << 16) )

#define getPAR(par) \
        WIZCHIP_READ_BUF(_PAR_, (par), 16)

#define setICMP6BLKR(icmp6blkr) \
        WIZCHIP_WRITE(_ICMP6BLKR_,(icmp6blkr))

#define getICMP6BLKR() \
        WIZCHIP_READ(_ICMP6BLKR_)

#define setCHPLCKR(chplckr) \
        WIZCHIP_WRITE(_CHPLCKR_, (chplckr))

#define getCHPLCKR() \
        ((getSYSR() & SYSR_CHPL) >> 7)

#define CHIPLOCK()      setCHPLCKR(0xFF)
#define CHIPUNLOCK()    setCHPLCKR(0xCE)

#define setNETLCKR(netlckr) \
        WIZCHIP_WRITE(_NETLCKR_, (netlckr))

#define getNETLCKR() \
        ((getSYSR() & SYSR_NETL) >> 6)

#define NETLOCK()      setNETLCKR(0xC5)
#define NETUNLOCK()    setNETLCKR(0x3A)

#define setPHYLCKR(phylckr) \
        WIZCHIP_WRITE(_PHYLCKR_,(phylckr))

#define getPHYLCKR() \
        ((getSYSR() & SYSR_PHYL) >> 5)

#define PHYLOCK()      setPHYLCKR(0xFF)
#define PHYUNLOCK()    setPHYLCKR(0x53)

#define setRTR(rtr) \
        do{                                                            \
            WIZCHIP_WRITE(_RTR_,(uint8_t)((rtr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1),(uint8_t)(rtr)); \
        }while(0);

#define getRTR() \
        ((((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))

#define setRCR(rcr) \
        WIZCHIP_WRITE(_RCR_,(rcr))

#define getRCR() \
        WIZCHIP_READ(_RCR_)

#define setSLRTR(slrtr) \
        do{                                                                \
            WIZCHIP_WRITE(_SLRTR_,(uint8_t)((slrtr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_,1),(uint8_t)(slrtr)); \
        }while(0);

#define getSLRTR() \
        ((((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_,1)))

#define setSLRCR(slrcr) \
        WIZCHIP_WRITE(_SLRCR_,(slrcr))

#define getSLRCR() \
        WIZCHIP_READ(_SLRCR_)

#define setSLHOPR(slhopr) \
        WIZCHIP_WRITE(_SLHOPR_,(slhopr))

#define getSLHOPR() \
        WIZCHIP_READ(_SLHOPR_)
/**
    @}
*/


////////////////////////////////////
// SOCKETn  register I/O function //
////////////////////////////////////
/**
    @addtogroup Socket_register_access_function_W6300
    @{
*/
#define setSn_MR(sn,mr) \
        WIZCHIP_WRITE(_Sn_MR_(sn),(mr))
#define getSn_MR(sn) \
        WIZCHIP_READ(_Sn_MR_(sn))

#define setSn_PSR(sn,psr) \
        WIZCHIP_WRITE(_Sn_PSR_(sn),(psr))
#define getSn_PSR(sn) \
        WIZCHIP_READ(_Sn_PSR_(sn))

#define setSn_CR(sn,cr) \
        WIZCHIP_WRITE(_Sn_CR_(sn),(cr))
#define getSn_CR(sn) \
        WIZCHIP_READ(_Sn_CR_(sn))

#define getSn_IR(sn) \
        WIZCHIP_READ(_Sn_IR_(sn))

#define setSn_IMR(sn,imr) \
        WIZCHIP_WRITE(_Sn_IMR_(sn),(imr))
#define getSn_IMR(sn) \
        WIZCHIP_READ(_Sn_IMR_(sn))

#define setSn_IRCLR(sn,irclr) \
        WIZCHIP_WRITE(_Sn_IRCLR_(sn),(irclr))
#define setSn_IR(sn,ir)          setSn_IRCLR(sn,(ir))

#define getSn_SR(sn) \
        WIZCHIP_READ(_Sn_SR_(sn))

#define getSn_ESR(sn) \
        WIZCHIP_READ(_Sn_ESR_(sn))

#define setSn_PNR(sn,pnr) \
        WIZCHIP_WRITE(_Sn_PNR_(sn),(pnr))
#define setSn_NHR(sn,nhr)        setSn_PNR(_Sn_PNR_(sn),(nhr))

#define getSn_PNR(sn) \
        WIZCHIP_READ(_Sn_PNR_(sn))
#define getSn_NHR(sn)            getSn_PNR(sn)

#define setSn_TOSR(sn,tosr) \
        WIZCHIP_WRITE(_Sn_TOSR_(sn),(tosr))
#define getSn_TOSR(sn) \
        WIZCHIP_READ(_Sn_TOSR_(sn))
#define getSn_TOS(sn)   getSn_TOSR(sn)    ///< For compatible ioLibrar
#define setSn_TOS(sn,tos)  setSn_TOSR(sn,tos)   ///< For compatible ioLibrar


#define setSn_TTLR(sn,ttlr) \
        WIZCHIP_WRITE(_Sn_TTLR_(sn),(ttlr))
#define getSn_TTLR(sn) \
        WIZCHIP_READ(_Sn_TTLR_(sn))
#define setSn_TTL(sn,ttl)       setSn_TTLR(sn,ttl)   ///< For compatible ioLibrary
#define getSn_TTL(sn)           getSn_TTLR(sn)   ///< For compatible ioLibrary

#define setSn_HOPR(sn,hopr)      setSn_TTLR(sn),(ttlr))
#define getSn_HOPR(sn)           getSn_TTLR(sn)

#define setSn_FRGR(sn,frgr) \
        do{                                                                      \
            WIZCHIP_WRITE(_Sn_FRGR_(sn),(uint8_t)((frgr)>>8));                   \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1),(uint8_t)(frgr));  \
        }while(0);
#define getSn_FRGR(sn,frgr) \
        ((((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1)))

#define setSn_MSSR(sn,mssr) \
        do{                                                                      \
            WIZCHIP_WRITE(_Sn_MSSR_(sn),(uint8_t)((mssr)>>8));                   \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1),(uint8_t)(mssr));  \
        }while(0);
#define getSn_MSSR(sn) \
        ((((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1)))

#define setSn_PORTR(sn,portr) \
        do{                                                                       \
            WIZCHIP_WRITE(_Sn_PORTR_(sn),(uint8_t)((portr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1),(uint8_t)(portr)); \
        }while(0);
#define getSn_PORTR(sn) \
        ((((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1)))

#define setSn_DHAR(sn,dhar) \
        WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn),(dhar),6)
#define getSn_DHAR(sn,dhar) \
        WIZCHIP_READ_BUF(_Sn_DHAR_(sn),(dhar),6)

#define setSn_DIPR(sn,dipr) \
        WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn),(dipr),4)
#define getSn_DIPR(sn,dipr) \
        WIZCHIP_READ_BUF(_Sn_DIPR_(sn),(dipr),4)

#define setSn_DIP4R(sn,dipr)      setSn_DIPR(sn,(dipr))
#define getSn_DIP4R(sn,dipr)      getSn_DIPR(sn,(dipr))

#define setSn_DIP6R(sn,dip6r) \
        WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn),(dip6r),16)
#define getSn_DIP6R(sn,dip6r) \
        WIZCHIP_READ_BUF(_Sn_DIP6R_(sn),(dip6r),16)

#define setSn_DPORTR(sn,dportr) \
        do{                                                                         \
            WIZCHIP_WRITE(_Sn_DPORTR_(sn),(uint8_t)((dportr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1),(uint8_t)(dportr)); \
        }while(0);


#define getSn_DPORTR(sn) \
        ((((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1)))

#define getSn_DPORT(sn) getSn_DPORTR(sn)
#define setSn_DPORT(sn,dportr)  setSn_DPORTR(sn,dportr)


#define setSn_MR2(sn,mr2) \
        WIZCHIP_WRITE(_Sn_MR2_(sn),(mr2))
#define getSn_MR2(sn) \
        WIZCHIP_READ(_Sn_MR2_(sn))

#define setSn_RTR(sn,rtr) \
        do{                                                                   \
            WIZCHIP_WRITE(_Sn_RTR_(sn),(uint8_t)((rtr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1),(uint8_t)(rtr)); \
        }while(0);
#define getSn_RTR(sn) \
        ((((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1)))

#define setSn_RCR(sn,rcr) \
        WIZCHIP_WRITE(_Sn_RCR_(sn),(rcr))
#define getSn_RCR(sn) \
        WIZCHIP_READ(_Sn_RCR_(sn))

#define setSn_KPALVTR(sn,kpalvtr) \
        WIZCHIP_WRITE(_Sn_KPALVTR_(sn),(kpalvtr))
#define getSn_KPALVTR(sn) \
        WIZCHIP_READ(_Sn_KPALVTR_(sn))

#define setSn_TX_BSR(sn, tmsr) \
        WIZCHIP_WRITE(_Sn_TX_BSR_(sn),(tmsr))
#define setSn_TXBUF_SIZE(sn, tmsr)      setSn_TX_BSR(sn,(tmsr))

#define getSn_TX_BSR(sn) \
        WIZCHIP_READ(_Sn_TX_BSR_(sn))
#define getSn_TXBUF_SIZE(sn)            getSn_TX_BSR(sn)

#define getSn_TxMAX(sn) \
	  (getSn_TX_BSR(sn) << 10)

uint16_t getSn_TX_FSR(uint8_t sn);

#define getSn_TX_RD(sn) \
        ((((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn),1)))

#define setSn_TX_WR(sn,txwr) \
        do{                                                                       \
            WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)((txwr)>>8));                  \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1), (uint8_t)(txwr)); \
        }while(0);
#define getSn_TX_WR(sn) \
        (((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1)))

#define setSn_RX_BSR(sn,rmsr) \
        WIZCHIP_WRITE(_Sn_RX_BSR_(sn),(rmsr))
#define setSn_RXBUF_SIZE(sn,rmsr)      setSn_RX_BSR(sn,(rmsr))

#define getSn_RX_BSR(sn) \
        WIZCHIP_READ(_Sn_RX_BSR_(sn))
#define getSn_RXBUF_SIZE(sn)           getSn_RX_BSR(sn)

#define getSn_RxMAX(sn) \
        (getSn_RX_BSR(sn) <<10)

uint16_t getSn_RX_RSR(uint8_t s);

#define setSn_RX_RD(sn,rxrd) \
        do{                                                                        \
            WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)((rxrd)>>8));                   \
            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1), (uint8_t)(rxrd)) ; \
        }while(0);

#define getSn_RX_RD(sn) \
        (((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1)))

#define getSn_RX_WR(sn) \
        (((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn),1)))
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
void wiz_recv_ignore(uint8_t sn, uint16_t len);
void wiz_delay_ms(uint32_t ms);

#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
void wiz_mdio_write(uint8_t phyregaddr, uint16_t var);
uint16_t wiz_mdio_read(uint8_t phyregaddr);
#endif

#ifdef __cplusplus
}
#endif

#endif //_W6300_H_