#include #include "port_common.h" #include "wizchip_conf.h" #include "wizchip_spi.h" #include "wizchip_qspi_pio.h" #include "pico/stdlib.h" #include "pico/binary_info.h" #include "pico/critical_section.h" #include "hardware/dma.h" static critical_section_t g_wizchip_cri_sec; wiznet_spi_config_t g_spi_config = { .clock_div_major = WIZNET_SPI_CLKDIV_MAJOR_DEFAULT, .clock_div_minor = WIZNET_SPI_CLKDIV_MINOR_DEFAULT, .clock_pin = PIO_SPI_SCK_PIN, .data_io0_pin = PIO_SPI_DATA_IO0_PIN, .data_io1_pin = PIO_SPI_DATA_IO1_PIN, .data_io2_pin = PIO_SPI_DATA_IO2_PIN, .data_io3_pin = PIO_SPI_DATA_IO3_PIN, .cs_pin = PIN_CS, .reset_pin = PIN_RST, .irq_pin = PIN_INT, }; wiznet_spi_handle_t spi_handle; void wizchip_reset() { gpio_init(PIN_RST); gpio_set_dir(PIN_RST, GPIO_OUT); gpio_put(PIN_RST, 0); sleep_ms(100); gpio_put(PIN_RST, 1); sleep_ms(100); } static void wizchip_critical_section_lock(void) { critical_section_enter_blocking(&g_wizchip_cri_sec); } static void wizchip_critical_section_unlock(void) { critical_section_exit(&g_wizchip_cri_sec); } void wizchip_spi_initialize(void) { spi_handle = wiznet_spi_pio_open(&g_spi_config); (*spi_handle)->set_active(spi_handle); } void wizchip_cris_initialize(void) { critical_section_init(&g_wizchip_cri_sec); reg_wizchip_cris_cbfunc(wizchip_critical_section_lock, wizchip_critical_section_unlock); } void wizchip_initialize(void) { (*spi_handle)->frame_end(); reg_wizchip_qspi_cbfunc((*spi_handle)->read_byte, (*spi_handle)->write_byte); reg_wizchip_cs_cbfunc((*spi_handle)->frame_start, (*spi_handle)->frame_end); uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}}; ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize); } void wizchip_check(void) { if (getCIDR() != 0x6300) { printf("W6300 ACCESS ERR: CIDR = 0x%04x\n", getCIDR()); while (1); } } void network_initialize(wiz_NetInfo net_info) { uint8_t syslock = SYS_NET_LOCK; ctlwizchip(CW_SYS_UNLOCK, &syslock); ctlnetwork(CN_SET_NETINFO, (void *)&net_info); }