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@@ -19,13 +19,7 @@
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#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
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#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
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#define IRQ_SAMPLE_DELAY_NS 100
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#define IRQ_SAMPLE_DELAY_NS 100
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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#define PIO_PROGRAM_NAME wizchip_pio_spi_single_write_read
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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#define PIO_PROGRAM_NAME wizchip_pio_spi_dual_write_read
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
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#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
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#endif
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#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
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#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
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#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
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#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
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@@ -62,57 +56,19 @@ static wiznet_spi_funcs_t *get_wiznet_spi_pio_impl(void);
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static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
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static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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pdst[0] = opcode;
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pdst[1] = (uint8_t)((addr >> 8) & 0xFF);
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pdst[2] = (uint8_t)((addr >> 0) & 0xFF);
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pdst[3] = 0;
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return 3 + 1;
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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pdst[0] = ((opcode >> 7 & 0x01) << 6) | ((opcode >> 6 & 0x01) << 4) | ((opcode >> 5 & 0x01) << 2) | ((opcode >> 4 & 0x01) << 0);
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pdst[1] = ((opcode >> 3 & 0x01) << 6) | ((opcode >> 2 & 0x01) << 4) | ((opcode >> 1 & 0x01) << 2) | ((opcode >> 0 & 0x01) << 0);
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pdst[2] = (uint8_t)((addr >> 8) & 0xFF);
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pdst[3] = (uint8_t)((addr >> 0) & 0xFF);
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pdst[4] = 0;
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return 4 + 1;
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
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pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
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pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
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pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
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pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
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pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
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pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
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pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
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pdst[4] = ((uint8_t)(addr >> 8) & 0xFF);
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pdst[4] = ((uint8_t)(addr >> 8) & 0xFF);
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pdst[5] = ((uint8_t)(addr >> 0) & 0xFF);
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pdst[5] = ((uint8_t)(addr >> 0) & 0xFF);
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pdst[6] = 0;
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pdst[6] = 0;
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return 7;
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return 6 + 1;
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#endif
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return 0;
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}
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}
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// Initialise our gpios
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// Initialise our gpios
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static void pio_spi_gpio_setup(spi_pio_state_t *state) {
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static void pio_spi_gpio_setup(spi_pio_state_t *state) {
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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gpio_init(state->spi_config->data_io0_pin);
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gpio_init(state->spi_config->data_io1_pin);
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gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
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gpio_set_dir(state->spi_config->data_io1_pin, GPIO_OUT);
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gpio_put(state->spi_config->data_io0_pin, false);
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gpio_put(state->spi_config->data_io1_pin, false);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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gpio_init(state->spi_config->data_io0_pin);
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gpio_init(state->spi_config->data_io1_pin);
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gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
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gpio_set_dir(state->spi_config->data_io1_pin, GPIO_OUT);
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gpio_put(state->spi_config->data_io0_pin, false);
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gpio_put(state->spi_config->data_io1_pin, false);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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gpio_init(state->spi_config->data_io0_pin);
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gpio_init(state->spi_config->data_io0_pin);
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gpio_init(state->spi_config->data_io1_pin);
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gpio_init(state->spi_config->data_io1_pin);
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gpio_init(state->spi_config->data_io2_pin);
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gpio_init(state->spi_config->data_io2_pin);
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@@ -125,7 +81,6 @@ static void pio_spi_gpio_setup(spi_pio_state_t *state) {
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gpio_put(state->spi_config->data_io1_pin, false);
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gpio_put(state->spi_config->data_io1_pin, false);
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gpio_put(state->spi_config->data_io2_pin, false);
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gpio_put(state->spi_config->data_io2_pin, false);
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gpio_put(state->spi_config->data_io3_pin, false);
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gpio_put(state->spi_config->data_io3_pin, false);
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#endif
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gpio_init(state->spi_config->cs_pin);
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gpio_init(state->spi_config->cs_pin);
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gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
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gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
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@@ -197,72 +152,21 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
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PADS_BANK0_GPIO0_SLEWFAST_BITS
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PADS_BANK0_GPIO0_SLEWFAST_BITS
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);
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);
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 1);
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sm_config_set_in_pins(&sm_config, state->spi_config->data_io1_pin);
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sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
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sm_config_set_in_shift(&sm_config, false, true, 8);
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sm_config_set_out_shift(&sm_config, false, true, 8);
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hw_set_bits(&state->pio->input_sync_bypass,
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(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin));
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pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
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pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
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gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
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// Set data pin to pull down and schmitt
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gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 2);
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sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
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sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
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sm_config_set_in_shift(&sm_config, false, true, 8);
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sm_config_set_out_shift(&sm_config, false, true, 8);
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hw_set_bits(&state->pio->input_sync_bypass,
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(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin));
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pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
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pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
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gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
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// Set data pin to pull down and schmitt
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gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 4);
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sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 4);
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sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
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sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
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sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 4);
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sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 4);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
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sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
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sm_config_set_in_shift(&sm_config, false, true, 8);
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sm_config_set_in_shift(&sm_config, false, true, 8);
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sm_config_set_out_shift(&sm_config, false, true, 8);
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sm_config_set_out_shift(&sm_config, false, true, 8);
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hw_set_bits(&state->pio->input_sync_bypass,
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hw_set_bits(&state->pio->input_sync_bypass,
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(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin) | (1u << state->spi_config->data_io2_pin) | (1u << state->spi_config->data_io3_pin));
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(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin) | (1u << state->spi_config->data_io2_pin) | (1u << state->spi_config->data_io3_pin));
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pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
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pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
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pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
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pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
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gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io2_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io2_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io3_pin, state->pio_func_sel);
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gpio_set_function(state->spi_config->data_io3_pin, state->pio_func_sel);
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// Set data pin to pull down and schmitt
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gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io2_pin, false, true);
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gpio_set_pulls(state->spi_config->data_io2_pin, false, true);
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@@ -271,7 +175,6 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io2_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io2_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io3_pin, true);
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gpio_set_input_hysteresis_enabled(state->spi_config->data_io3_pin, true);
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#endif
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pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
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pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
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@@ -321,18 +224,10 @@ static __noinline void ns_delay(uint32_t ns) {
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static void wiznet_spi_pio_frame_start(void) {
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static void wiznet_spi_pio_frame_start(void) {
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assert(active_state);
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assert(active_state);
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io2_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io2_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io3_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->data_io3_pin, active_state->pio_func_sel);
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#endif
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gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
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gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
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gpio_pull_down(active_state->spi_config->clock_pin);
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gpio_pull_down(active_state->spi_config->clock_pin);
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// Pull CS low
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// Pull CS low
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@@ -359,27 +254,12 @@ void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
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//pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset + PIO_SPI_OFFSET_WRITE_BITS, active_state->pio_offset + PIO_SPI_OFFSET_READ_BITS_END - 1);
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//pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset + PIO_SPI_OFFSET_WRITE_BITS, active_state->pio_offset + PIO_SPI_OFFSET_READ_BITS_END - 1);
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pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
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pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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loop_cnt = 8;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin), (1u << active_state->spi_config->data_io0_pin));// | (1u << active_state->spi_config->data_io1_pin));
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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loop_cnt = 4;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin));
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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loop_cnt = 2;
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loop_cnt = 2;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
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/* @todo: Implement to use. */
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#endif
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pio_sm_restart(active_state->pio, active_state->pio_sm);
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pio_sm_restart(active_state->pio, active_state->pio_sm);
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pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
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pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
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@@ -408,20 +288,13 @@ void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
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channel_config_set_read_increment(&in_config, false);
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channel_config_set_read_increment(&in_config, false);
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dma_channel_configure(active_state->dma_in, &in_config, rx, &active_state->pio->rxf[active_state->pio_sm], rx_length, true);
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dma_channel_configure(active_state->dma_in, &in_config, rx, &active_state->pio->rxf[active_state->pio_sm], rx_length, true);
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#if 1
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
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__compiler_memory_barrier();
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__compiler_memory_barrier();
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dma_channel_wait_for_finish_blocking(active_state->dma_out);
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dma_channel_wait_for_finish_blocking(active_state->dma_out);
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dma_channel_wait_for_finish_blocking(active_state->dma_in);
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dma_channel_wait_for_finish_blocking(active_state->dma_in);
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__compiler_memory_barrier();
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__compiler_memory_barrier();
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
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pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
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pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
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#endif
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}
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}
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void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, uint16_t tx_length) {
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void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, uint16_t tx_length) {
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@@ -434,26 +307,12 @@ void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, u
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pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
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pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
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pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
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pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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loop_cnt = 8;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin), (1u << active_state->spi_config->data_io0_pin));
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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loop_cnt = 4;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin));
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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loop_cnt = 2;
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loop_cnt = 2;
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pio_sm_set_pindirs_with_mask(active_state->pio,
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pio_sm_set_pindirs_with_mask(active_state->pio,
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active_state->pio_sm,
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active_state->pio_sm,
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
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(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
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#endif
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pio_sm_restart(active_state->pio, active_state->pio_sm);
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pio_sm_restart(active_state->pio, active_state->pio_sm);
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pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
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pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
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pio_sm_put(active_state->pio, active_state->pio_sm, tx_length * loop_cnt - 1);
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pio_sm_put(active_state->pio, active_state->pio_sm, tx_length * loop_cnt - 1);
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@@ -482,21 +341,11 @@ void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, u
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while (!(active_state->pio->fdebug & fdebug_tx_stall)) {
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while (!(active_state->pio->fdebug & fdebug_tx_stall)) {
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tight_loop_contents(); // todo timeout
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tight_loop_contents(); // todo timeout
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}
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}
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#if 1
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__compiler_memory_barrier();
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__compiler_memory_barrier();
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//pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
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#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
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pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 1, false);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
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pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 2, false);
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#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
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pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 4, false);
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pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 4, false);
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#endif
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pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
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pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
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pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
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#endif
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}
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}
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