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Strip QSPI mode options to quad-only, remove dead files

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This commit is contained in:
Ian Gulliver
2026-04-04 15:28:27 +09:00
parent 45e121bd99
commit dec8d0c68d
8 changed files with 22 additions and 274 deletions
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1
w6300/board_list.h
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@@ -1 +0,0 @@
#define W6300_EVB_PICO2 9

11
w6300/port_common.h
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@@ -1,11 +0,0 @@
#ifndef _PORT_COMMON_H_
#define _PORT_COMMON_H_
#include "pico/stdlib.h"
#include "pico/binary_info.h"
#include "pico/critical_section.h"
#include "hardware/spi.h"
#include "hardware/dma.h"
#include "hardware/clocks.h"
#endif /* _PORT_COMMON_H_ */

8
w6300/wizchip_conf.h
View File

@@ -27,13 +27,7 @@ extern "C" {
#define _PHY_IO_MODE_MII_ 0x0010
#define _PHY_IO_MODE_ _PHY_IO_MODE_MII_
#define QSPI_SINGLE_MODE (0x00 << 6)
#define QSPI_DUAL_MODE (0x01 << 6)
#define QSPI_QUAD_MODE (0x02 << 6)
#ifndef _WIZCHIP_QSPI_MODE_
#define _WIZCHIP_QSPI_MODE_ QSPI_SINGLE_MODE
#endif
#define _WIZCHIP_QSPI_MODE_ (0x02 << 6)
#define _WIZCHIP_ID_ "W6300\0"
#define _WIZCHIP_IO_MODE_ ((_WIZCHIP_IO_MODE_SPI_ & 0xff00) | (_WIZCHIP_QSPI_MODE_ & 0x00ff))

153
w6300/wizchip_qspi_pio.c
View File

@@ -19,13 +19,7 @@
#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
#define IRQ_SAMPLE_DELAY_NS 100
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
#define PIO_PROGRAM_NAME wizchip_pio_spi_single_write_read
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
#define PIO_PROGRAM_NAME wizchip_pio_spi_dual_write_read
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
#endif
#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
@@ -62,57 +56,19 @@ static wiznet_spi_funcs_t *get_wiznet_spi_pio_impl(void);
static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
pdst[0] = opcode;
pdst[1] = (uint8_t)((addr >> 8) & 0xFF);
pdst[2] = (uint8_t)((addr >> 0) & 0xFF);
pdst[3] = 0;
return 3 + 1;
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
pdst[0] = ((opcode >> 7 & 0x01) << 6) | ((opcode >> 6 & 0x01) << 4) | ((opcode >> 5 & 0x01) << 2) | ((opcode >> 4 & 0x01) << 0);
pdst[1] = ((opcode >> 3 & 0x01) << 6) | ((opcode >> 2 & 0x01) << 4) | ((opcode >> 1 & 0x01) << 2) | ((opcode >> 0 & 0x01) << 0);
pdst[2] = (uint8_t)((addr >> 8) & 0xFF);
pdst[3] = (uint8_t)((addr >> 0) & 0xFF);
pdst[4] = 0;
return 4 + 1;
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
pdst[4] = ((uint8_t)(addr >> 8) & 0xFF);
pdst[5] = ((uint8_t)(addr >> 0) & 0xFF);
pdst[6] = 0;
return 6 + 1;
#endif
return 0;
return 7;
}
// Initialise our gpios
static void pio_spi_gpio_setup(spi_pio_state_t *state) {
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
gpio_init(state->spi_config->data_io0_pin);
gpio_init(state->spi_config->data_io1_pin);
gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
gpio_set_dir(state->spi_config->data_io1_pin, GPIO_OUT);
gpio_put(state->spi_config->data_io0_pin, false);
gpio_put(state->spi_config->data_io1_pin, false);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
gpio_init(state->spi_config->data_io0_pin);
gpio_init(state->spi_config->data_io1_pin);
gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
gpio_set_dir(state->spi_config->data_io1_pin, GPIO_OUT);
gpio_put(state->spi_config->data_io0_pin, false);
gpio_put(state->spi_config->data_io1_pin, false);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
gpio_init(state->spi_config->data_io0_pin);
gpio_init(state->spi_config->data_io1_pin);
gpio_init(state->spi_config->data_io2_pin);
@@ -125,7 +81,6 @@ static void pio_spi_gpio_setup(spi_pio_state_t *state) {
gpio_put(state->spi_config->data_io1_pin, false);
gpio_put(state->spi_config->data_io2_pin, false);
gpio_put(state->spi_config->data_io3_pin, false);
#endif
gpio_init(state->spi_config->cs_pin);
gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
@@ -197,72 +152,21 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
PADS_BANK0_GPIO0_SLEWFAST_BITS
);
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 1);
sm_config_set_in_pins(&sm_config, state->spi_config->data_io1_pin);
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
sm_config_set_sideset(&sm_config, 1, false, false);
sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
sm_config_set_in_shift(&sm_config, false, true, 8);
sm_config_set_out_shift(&sm_config, false, true, 8);
hw_set_bits(&state->pio->input_sync_bypass,
(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin));
pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
// Set data pin to pull down and schmitt
gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 2);
sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 2);
sm_config_set_sideset(&sm_config, 1, false, false);
sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
sm_config_set_in_shift(&sm_config, false, true, 8);
sm_config_set_out_shift(&sm_config, false, true, 8);
hw_set_bits(&state->pio->input_sync_bypass,
(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin));
pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
// Set data pin to pull down and schmitt
gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 4);
sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 4);
sm_config_set_sideset(&sm_config, 1, false, false);
sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
sm_config_set_in_shift(&sm_config, false, true, 8);
sm_config_set_out_shift(&sm_config, false, true, 8);
hw_set_bits(&state->pio->input_sync_bypass,
(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin) | (1u << state->spi_config->data_io2_pin) | (1u << state->spi_config->data_io3_pin));
pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
gpio_set_function(state->spi_config->data_io2_pin, state->pio_func_sel);
gpio_set_function(state->spi_config->data_io3_pin, state->pio_func_sel);
// Set data pin to pull down and schmitt
gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
gpio_set_pulls(state->spi_config->data_io2_pin, false, true);
@@ -271,7 +175,6 @@ wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io2_pin, true);
gpio_set_input_hysteresis_enabled(state->spi_config->data_io3_pin, true);
#endif
pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
@@ -321,18 +224,10 @@ static __noinline void ns_delay(uint32_t ns) {
static void wiznet_spi_pio_frame_start(void) {
assert(active_state);
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
gpio_set_function(active_state->spi_config->data_io2_pin, active_state->pio_func_sel);
gpio_set_function(active_state->spi_config->data_io3_pin, active_state->pio_func_sel);
#endif
gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
gpio_pull_down(active_state->spi_config->clock_pin);
// Pull CS low
@@ -359,27 +254,12 @@ void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
//pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset + PIO_SPI_OFFSET_WRITE_BITS, active_state->pio_offset + PIO_SPI_OFFSET_READ_BITS_END - 1);
pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
loop_cnt = 8;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin), (1u << active_state->spi_config->data_io0_pin));// | (1u << active_state->spi_config->data_io1_pin));
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
loop_cnt = 4;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin),
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin));
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
loop_cnt = 2;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
/* @todo: Implement to use. */
#endif
pio_sm_restart(active_state->pio, active_state->pio_sm);
pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
@@ -408,20 +288,13 @@ void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
channel_config_set_read_increment(&in_config, false);
dma_channel_configure(active_state->dma_in, &in_config, rx, &active_state->pio->rxf[active_state->pio_sm], rx_length, true);
#if 1
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
__compiler_memory_barrier();
dma_channel_wait_for_finish_blocking(active_state->dma_out);
dma_channel_wait_for_finish_blocking(active_state->dma_in);
__compiler_memory_barrier();
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
#endif
}
void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, uint16_t tx_length) {
@@ -434,26 +307,12 @@ void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, u
pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
loop_cnt = 8;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin), (1u << active_state->spi_config->data_io0_pin));
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
loop_cnt = 4;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin),
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin));
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
loop_cnt = 2;
pio_sm_set_pindirs_with_mask(active_state->pio,
active_state->pio_sm,
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
#endif
pio_sm_restart(active_state->pio, active_state->pio_sm);
pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
pio_sm_put(active_state->pio, active_state->pio_sm, tx_length * loop_cnt - 1);
@@ -482,21 +341,11 @@ void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, u
while (!(active_state->pio->fdebug & fdebug_tx_stall)) {
tight_loop_contents(); // todo timeout
}
#if 1
__compiler_memory_barrier();
//pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
#if (_WIZCHIP_QSPI_MODE_ == QSPI_SINGLE_MODE)
pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 1, false);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_DUAL_MODE)
pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 2, false);
#elif (_WIZCHIP_QSPI_MODE_ == QSPI_QUAD_MODE)
pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 4, false);
#endif
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
#endif
}

107
w6300/wizchip_qspi_pio.pio
View File

@@ -1,89 +1,18 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Normal SPI for W55RP20
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.program wiznet_spi_write_read
.side_set 1
public write_bits:
out pins, 1 side 0
jmp x-- write_bits side 1
set pins 0 side 0
public write_end:
read_byte_delay:
set pindirs 0 side 0
read_byte:
set x 6 side 1
read_bits:
in pins, 1 side 0
jmp x-- read_bits side 1
in pins, 1 side 0
jmp y-- read_byte side 0
public read_end:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; QSPI Single for W6300
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.program wizchip_pio_spi_single_write_read
.side_set 1
public write_bits:
out pins, 1 side 0
jmp x-- write_bits side 1
set pins 0 side 0
public write_bits_end:
read_byte_delay:
set pindirs 0 side 0
read_byte:
set x 6 side 1
read_bits:
in pins, 1 side 0
jmp x-- read_bits side 1
in pins, 1 side 0
jmp y-- read_byte side 0
public read_bits_end:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; QSPI Dual for W6300
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.program wizchip_pio_spi_dual_write_read
.side_set 1
public write_bits:
out pins, 2 side 0
jmp x-- write_bits side 1
set pins 0 side 0
public write_bits_end:
read_byte_delay:
set pindirs 0 side 0
read_byte:
set x 2 side 1
read_bits:
in pins, 2 side 0
jmp x-- read_bits side 1
in pins, 2 side 0
jmp y-- read_byte side 0
public read_bits_end:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; QSPI Quad for W6300
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.program wizchip_pio_spi_quad_write_read
.side_set 1
write_bits:
out pins, 4 side 0
jmp x-- write_bits side 1
set pins 0 side 0
public write_bits_end:
read_byte_delay:
set pindirs 0 side 0
read_byte:
set x 0 side 1
read_bits:
in pins, 4 side 0
jmp x-- read_bits side 1
in pins, 4 side 0
jmp y-- read_byte side 0
public read_bits_end:
.program wizchip_pio_spi_quad_write_read
.side_set 1
write_bits:
out pins, 4 side 0
jmp x-- write_bits side 1
set pins 0 side 0
public write_bits_end:
read_byte_delay:
set pindirs 0 side 0
read_byte:
set x 0 side 1
read_bits:
in pins, 4 side 0
jmp x-- read_bits side 1
in pins, 4 side 0
jmp y-- read_byte side 0
public read_bits_end:

8
w6300/wizchip_spi.c
View File

@@ -1,13 +1,9 @@
#include <stdio.h>
#include "port_common.h"
#include "pico/stdlib.h"
#include "pico/critical_section.h"
#include "wizchip_conf.h"
#include "wizchip_spi.h"
#include "wizchip_qspi_pio.h"
#include "pico/stdlib.h"
#include "pico/binary_info.h"
#include "pico/critical_section.h"
#include "hardware/dma.h"
static critical_section_t g_wizchip_cri_sec;

2
w6300/wizchip_spi.h
View File

@@ -1,8 +1,6 @@
#ifndef _WIZCHIP_SPI_H_
#define _WIZCHIP_SPI_H_
#include "board_list.h"
#define USE_PIO
#define WIZNET_SPI_CLKDIV_MAJOR_DEFAULT 2
#define WIZNET_SPI_CLKDIV_MINOR_DEFAULT 0