C++-ize W6300 driver: remove vtable indirection, constexpr pins, pragma once
This commit is contained in:
Ian Gulliver
+5
-5
@@ -11,11 +11,11 @@ pico_sdk_init()
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add_executable(picomap
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picomap.cpp
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w6300/wizchip_spi.c
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w6300/wizchip_qspi_pio.c
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w6300/wizchip_conf.c
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w6300/w6300.c
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w6300/socket.c
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w6300/wizchip_spi.cpp
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w6300/wizchip_qspi_pio.cpp
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w6300/wizchip_conf.cpp
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w6300/w6300.cpp
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w6300/socket.cpp
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)
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target_include_directories(picomap PRIVATE
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@@ -4,10 +4,8 @@
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#include "pico/unique_id.h"
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#include "device.h"
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extern "C" {
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#include "wizchip_conf.h"
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#include "wizchip_spi.h"
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}
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static void send_bytes(const std::vector<uint8_t> &data) {
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for (auto b : data) {
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+1
-11
@@ -1,9 +1,4 @@
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#ifndef _SOCKET_H_
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#define _SOCKET_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#pragma once
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#include "wizchip_conf.h"
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#define SOCKET uint8_t
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@@ -123,8 +118,3 @@ int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr,
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#define sendto(sn, buf, len, addr, port, addrlen) sendto_W6x00(sn, buf, len, addr, port, addrlen)
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#define recvfrom(sn, buf, len, addr, port, addrlen) recvfrom_W6x00(sn, buf, len, addr, port, addrlen)
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#ifdef __cplusplus
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}
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#endif
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#endif
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-151
@@ -1,151 +0,0 @@
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#include "w6300.h"
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void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[4];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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tAD[3] = wb;
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 4, 1);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, &wb, 1);
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#endif
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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}
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uint8_t WIZCHIP_READ(uint32_t AddrSel) {
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uint8_t ret[2] = {0,};
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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ret[0] = WIZCHIP.IF.BUS._read_data(IDM_DR);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_READ_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, ret, 1);
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#endif
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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return ret[0];
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}
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void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if (_WIZCHIP_IO_MODE_ & 0xff00) & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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WIZCHIP.IF.BUS._write_data_buf(IDM_DR, pBuf, len, 0);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_WRITE_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._write_qspi(opcode, ADDR, pBuf, len);
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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#endif
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}
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void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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uint8_t opcode = 0;
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uint16_t ADDR = 0;
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WIZCHIP_CRITICAL_ENTER();
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WIZCHIP.CS._select();
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#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
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uint8_t tAD[3];
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tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
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tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
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tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
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WIZCHIP.IF.BUS._write_data_buf(IDM_AR0, tAD, 3, 1);
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WIZCHIP.IF.BUS._read_data_buf(IDM_DR, pBuf, len, 0);
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#else
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opcode = (uint8_t)((AddrSel & 0x000000FF) | (_W6300_SPI_READ_) | (_WIZCHIP_QSPI_MODE_));
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ADDR = (uint16_t)((AddrSel & 0x00ffff00) >> 8);
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WIZCHIP.IF.QSPI._read_qspi(opcode, ADDR, pBuf, len);
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WIZCHIP.CS._deselect();
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WIZCHIP_CRITICAL_EXIT();
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#endif
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}
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uint16_t getSn_TX_FSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_TX_FSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_FSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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uint16_t getSn_RX_RSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_RX_RSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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uint16_t ptr = getSn_TX_WR(sn);
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uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
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WIZCHIP_WRITE_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_TX_WR(sn, ptr);
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}
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void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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if (len == 0) return;
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uint16_t ptr = getSn_RX_RD(sn);
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uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
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WIZCHIP_READ_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_RX_RD(sn, ptr);
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}
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void wiz_recv_ignore(uint8_t sn, uint16_t len) {
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setSn_RX_RD(sn, getSn_RX_RD(sn) + len);
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}
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void wiz_delay_ms(uint32_t milliseconds) {
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for (uint32_t i = 0; i < milliseconds; i++) {
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setTCNTRCLR(0xff);
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while (getTCNTR() < 0x0a) {}
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}
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}
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#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
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void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
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setPHYRAR(phyregaddr);
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setPHYDIR(var);
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setPHYACR(PHYACR_WRITE);
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while (getPHYACR());
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}
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uint16_t wiz_mdio_read(uint8_t phyregaddr) {
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setPHYRAR(phyregaddr);
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setPHYACR(PHYACR_READ);
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while (getPHYACR());
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return getPHYDOR();
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}
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#endif
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+108
@@ -0,0 +1,108 @@
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#include "w6300.h"
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#include "wizchip_qspi_pio.h"
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static uint8_t make_opcode(uint32_t addr, uint8_t rw) {
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return static_cast<uint8_t>((addr & 0xFF) | rw | _WIZCHIP_QSPI_MODE_);
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}
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static uint16_t make_addr(uint32_t addr) {
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return static_cast<uint16_t>((addr & 0x00FFFF00) >> 8);
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}
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void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
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WIZCHIP_CRITICAL_ENTER();
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wizchip_pio_frame_start();
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wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), &wb, 1);
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wizchip_pio_frame_end();
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WIZCHIP_CRITICAL_EXIT();
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}
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uint8_t WIZCHIP_READ(uint32_t AddrSel) {
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uint8_t ret[2] = {0};
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WIZCHIP_CRITICAL_ENTER();
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wizchip_pio_frame_start();
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wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), ret, 1);
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wizchip_pio_frame_end();
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WIZCHIP_CRITICAL_EXIT();
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return ret[0];
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}
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void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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WIZCHIP_CRITICAL_ENTER();
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wizchip_pio_frame_start();
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wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), pBuf, len);
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wizchip_pio_frame_end();
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WIZCHIP_CRITICAL_EXIT();
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}
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void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) {
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WIZCHIP_CRITICAL_ENTER();
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wizchip_pio_frame_start();
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wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), pBuf, len);
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wizchip_pio_frame_end();
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WIZCHIP_CRITICAL_EXIT();
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}
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uint16_t getSn_TX_FSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_TX_FSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_FSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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uint16_t getSn_RX_RSR(uint8_t sn) {
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uint16_t prev_val = -1, val = 0;
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do {
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prev_val = val;
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val = WIZCHIP_READ(_Sn_RX_RSR_(sn));
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val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RSR_(sn), 1));
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} while (val != prev_val);
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return val;
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}
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void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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uint16_t ptr = getSn_TX_WR(sn);
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uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn);
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WIZCHIP_WRITE_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_TX_WR(sn, ptr);
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}
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void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
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if (len == 0) return;
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uint16_t ptr = getSn_RX_RD(sn);
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uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn);
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WIZCHIP_READ_BUF(addrsel, wizdata, len);
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ptr += len;
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setSn_RX_RD(sn, ptr);
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}
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void wiz_recv_ignore(uint8_t sn, uint16_t len) {
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setSn_RX_RD(sn, getSn_RX_RD(sn) + len);
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}
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void wiz_delay_ms(uint32_t milliseconds) {
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for (uint32_t i = 0; i < milliseconds; i++) {
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setTCNTRCLR(0xff);
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while (getTCNTR() < 0x0a) {}
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}
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}
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#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
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void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
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setPHYRAR(phyregaddr);
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setPHYDIR(var);
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setPHYACR(PHYACR_WRITE);
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while (getPHYACR());
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}
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uint16_t wiz_mdio_read(uint8_t phyregaddr) {
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setPHYRAR(phyregaddr);
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setPHYACR(PHYACR_READ);
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while (getPHYACR());
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return getPHYDOR();
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}
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#endif
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+108
-135
@@ -1,153 +1,129 @@
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#ifndef _W6300_H_
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#define _W6300_H_
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#include <stdint.h>
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#pragma once
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#include <cstdint>
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#include "wizchip_conf.h"
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constexpr uint8_t W6300_SPI_READ = (0x00 << 5);
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constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5);
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#ifdef __cplusplus
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extern "C" {
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#endif
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constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00;
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constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; }
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constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; }
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constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; }
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#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8))
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#define _W6300_SPI_READ_ (0x00 << 5) ///< SPI interface Read operation in Control Phase
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#define _W6300_SPI_WRITE_ (0x01 << 5) ///< SPI interface Write operation in Control Phase
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#define WIZCHIP_CREG_BLOCK (0x00 ) ///< Common register block
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#define WIZCHIP_SREG_BLOCK(N) ((1+4*N)) ///< SOCKETn register block
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#define WIZCHIP_TXBUF_BLOCK(N) ((2+4*N)) ///< SOCKETn Tx buffer address block
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#define WIZCHIP_RXBUF_BLOCK(N) ((3+4*N)) ///< SOCKETn Rx buffer address block
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#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) ///< Increase offset address
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#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
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#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
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#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
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#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
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#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
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#define _W6300_IO_BASE_ _WIZCHIP_IO_BASE_
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#elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
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#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
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#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
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#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
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#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
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#define _W6300_IO_BASE_ 0x00000000
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#define _W6100_IO_BASE_ 0x00000000
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#endif
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#define _CIDR_ (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)
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#define _RTL_ (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_CREG_BLOCK)
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#define _VER_ (_W6300_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)
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#define _SYSR_ (_W6300_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)
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#define _SYCR0_ (_W6300_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)
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#define _CIDR_ ((0x0000 << 8) + WIZCHIP_CREG_BLOCK)
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#define _RTL_ ((0x0004 << 8) + WIZCHIP_CREG_BLOCK)
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#define _VER_ ((0x0002 << 8) + WIZCHIP_CREG_BLOCK)
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#define _SYSR_ ((0x2000 << 8) + WIZCHIP_CREG_BLOCK)
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#define _SYCR0_ ((0x2004 << 8) + WIZCHIP_CREG_BLOCK)
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#define _SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1))
|
||||
#define _TCNTR_ (_W6300_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _TCNTRCLR_ (_W6300_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IR_ (_W6300_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIR_ (_W6300_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIR_ (_W6300_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IMR_ (_W6300_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IRCLR_ (_W6300_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIMR_ (_W6300_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIMR_ (_W6300_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIRCLR_ (_W6300_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLPSR_ (_W6300_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLCR_ (_W6300_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYSR_ (_W6300_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYRAR_ (_W6300_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIR_ (_W6300_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDOR_ (_W6300_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYACR_ (_W6300_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIVR_ (_W6300_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYCR0_ (_W6300_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _TCNTR_ ((0x2016 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _TCNTRCLR_ ((0x2020 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IR_ ((0x2100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIR_ ((0x2101 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIR_ ((0x2102 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IMR_ ((0x2104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _IRCLR_ ((0x2108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIMR_ ((0x2114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIMR_ ((0x2124 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLIRCLR_ ((0x2128 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLPSR_ ((0x212C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLCR_ ((0x2130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYSR_ ((0x3000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYRAR_ ((0x3008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIR_ ((0x300C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDOR_ ((0x3010 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYACR_ ((0x3014 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYDIVR_ ((0x3018 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYCR0_ ((0x301C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1)
|
||||
#define _NET4MR_ (_W6300_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NET6MR_ (_W6300_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR_ (_W6300_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR2_ (_W6300_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PTMR_ (_W6300_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMNR_ (_W6300_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHAR_ (_W6300_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PSIDR_ (_W6300_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMRUR_ (_W6300_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SHAR_ (_W6300_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GAR_ (_W6300_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NET4MR_ ((0x4000 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NET6MR_ ((0x4004 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR_ ((0x4008 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETMR2_ ((0x4009 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PTMR_ ((0x4100 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMNR_ ((0x4104 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHAR_ ((0x4108 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PSIDR_ ((0x4110 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PMRUR_ ((0x4114 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SHAR_ ((0x4120 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GAR_ ((0x4130 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GA4R_ (_GAR_)
|
||||
#define _SUBR_ (_W6300_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUBR_ ((0x4134 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUB4R_ (_SUBR_)
|
||||
|
||||
#define _SIPR_ (_W6300_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIPR_ ((0x4138 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SIP4R_ (_SIPR_)
|
||||
#define _LLAR_ (_W6300_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GUAR_ (_W6300_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUB6R_ (_W6300_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GA6R_ (_W6300_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIP6R_ (_W6300_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIPR_ (_W6300_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _LLAR_ ((0x4140 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GUAR_ ((0x4150 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SUB6R_ ((0x4160 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _GA6R_ ((0x4170 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIP6R_ ((0x4180 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIPR_ ((0x418C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDIP4R_ (_SLDIPR_)
|
||||
#define _SLDHAR_ (_W6300_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGIDR_ (_W6300_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGSEQR_ (_W6300_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIPR_ (_W6300_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLDHAR_ ((0x4190 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGIDR_ ((0x4198 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PINGSEQR_ ((0x419C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIPR_ ((0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIP4R_ (_UIPR_)
|
||||
#define _UPORTR_ (_W6300_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORTR_ ((0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORT4R_ (_UPORTR_)
|
||||
#define _UIP6R_ (_W6300_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORT6R_ (_W6300_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _INTPTMR_ (_W6300_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLR_ (_W6300_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PFR_ (_W6300_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _VLTR_ (_W6300_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLTR_ (_W6300_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PAR_ (_W6300_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _ICMP6BLKR_ (_W6300_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _CHPLCKR_ (_W6300_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETLCKR_ (_W6300_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYLCKR_ (_W6300_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RTR_ (_W6300_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RCR_ (_W6300_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRTR_ (_W6300_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRCR_ (_W6300_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLHOPR_ (_W6300_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UIP6R_ ((0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _UPORT6R_ ((0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _INTPTMR_ ((0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLR_ ((0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PFR_ ((0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _VLTR_ ((0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PLTR_ ((0x41DC << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PAR_ ((0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _ICMP6BLKR_ ((0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _CHPLCKR_ ((0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _NETLCKR_ ((0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _PHYLCKR_ ((0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RTR_ ((0x4200 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _RCR_ ((0x4204 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRTR_ ((0x4208 << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLRCR_ ((0x420C << 8) + WIZCHIP_CREG_BLOCK)
|
||||
#define _SLHOPR_ ((0x420F << 8) + WIZCHIP_CREG_BLOCK)
|
||||
|
||||
#define _Sn_MR_(N) (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PSR_(N) (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_CR_(N) (_W6300_IO_BASE_ + (0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IR_(N) (_W6300_IO_BASE_ + (0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IMR_(N) (_W6300_IO_BASE_ + (0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IRCLR_(N) (_W6300_IO_BASE_ + (0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MR_(N) ((0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PSR_(N) ((0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_CR_(N) ((0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IR_(N) ((0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IMR_(N) ((0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_IRCLR_(N) ((0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
|
||||
|
||||
|
||||
#define _Sn_SR_(N) (_W6300_IO_BASE_ + (0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_ESR_(N) (_W6300_IO_BASE_ + (0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PNR_(N) (_W6300_IO_BASE_ + (0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_SR_(N) ((0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_ESR_(N) ((0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PNR_(N) ((0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_NHR_(N) (_Sn_PNR_(N))
|
||||
#define _Sn_TOSR_(N) (_W6300_IO_BASE_ + (0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TTLR_(N) (_W6300_IO_BASE_ + (0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TOSR_(N) ((0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TTLR_(N) ((0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_HOPR_(N) (_Sn_TTLR_(N))
|
||||
#define _Sn_FRGR_(N) (_W6300_IO_BASE_ + (0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MSSR_(N) (_W6300_IO_BASE_ + (0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PORTR_(N) (_W6300_IO_BASE_ + (0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DHAR_(N) (_W6300_IO_BASE_ + (0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIPR_(N) (_W6300_IO_BASE_ + (0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_FRGR_(N) ((0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MSSR_(N) ((0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_PORTR_(N) ((0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DHAR_(N) ((0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIPR_(N) ((0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIP4R_(N) (_Sn_DIPR_(N))
|
||||
#define _Sn_DIP6R_(N) (_W6300_IO_BASE_ + (0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DPORTR_(N) (_W6300_IO_BASE_ + (0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MR2_(N) (_W6300_IO_BASE_ + (0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RTR_(N) (_W6300_IO_BASE_ + (0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RCR_(N) (_W6300_IO_BASE_ + (0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_KPALVTR_(N) (_W6300_IO_BASE_ + (0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_BSR_(N) (_W6300_IO_BASE_ + (0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_FSR_(N) (_W6300_IO_BASE_ + (0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_RD_(N) (_W6300_IO_BASE_ + (0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_WR_(N) (_W6300_IO_BASE_ + (0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_BSR_(N) (_W6300_IO_BASE_ + (0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RSR_(N) (_W6300_IO_BASE_ + (0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RD_(N) (_W6300_IO_BASE_ + (0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_WR_(N) (_W6300_IO_BASE_ + (0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DIP6R_(N) ((0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_DPORTR_(N) ((0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_MR2_(N) ((0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RTR_(N) ((0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RCR_(N) ((0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_KPALVTR_(N) ((0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_BSR_(N) ((0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_FSR_(N) ((0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_RD_(N) ((0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_TX_WR_(N) ((0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_BSR_(N) ((0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RSR_(N) ((0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_RD_(N) ((0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
#define _Sn_RX_WR_(N) ((0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
|
||||
|
||||
#define SYSR_CHPL (1 << 7)
|
||||
#define SYSR_NETL (1 << 6)
|
||||
@@ -327,8 +303,10 @@ extern "C" {
|
||||
#define BMSR_EXT_CAPA (1<<0)
|
||||
|
||||
|
||||
#define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
|
||||
#define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
|
||||
void wizchip_cris_enter();
|
||||
void wizchip_cris_exit();
|
||||
#define WIZCHIP_CRITICAL_ENTER() wizchip_cris_enter()
|
||||
#define WIZCHIP_CRITICAL_EXIT() wizchip_cris_exit()
|
||||
|
||||
uint8_t WIZCHIP_READ(uint32_t AddrSel);
|
||||
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
|
||||
@@ -922,8 +900,3 @@ void wiz_mdio_write(uint8_t phyregaddr, uint16_t var);
|
||||
uint16_t wiz_mdio_read(uint8_t phyregaddr);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //_W6300_H_
|
||||
@@ -1,594 +0,0 @@
|
||||
#include <stddef.h>
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
void wizchip_cris_enter(void) {}
|
||||
void wizchip_cris_exit(void) {}
|
||||
void wizchip_cs_select(void) {}
|
||||
void wizchip_cs_deselect(void) {}
|
||||
|
||||
iodata_t wizchip_bus_readdata(uint32_t AddrSel) {
|
||||
return *((volatile iodata_t *)((ptrdiff_t)AddrSel));
|
||||
}
|
||||
|
||||
void wizchip_bus_writedata(uint32_t AddrSel, iodata_t wb) {
|
||||
*((volatile iodata_t *)((ptrdiff_t)AddrSel)) = wb;
|
||||
}
|
||||
|
||||
void wizchip_bus_read_buf(uint32_t AddrSel, iodata_t* buf, int16_t len, uint8_t addrinc) {
|
||||
if (addrinc) addrinc = sizeof(iodata_t);
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
*buf++ = WIZCHIP.IF.BUS._read_data(AddrSel);
|
||||
AddrSel += (uint32_t)addrinc;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_bus_write_buf(uint32_t AddrSel, iodata_t* buf, int16_t len, uint8_t addrinc) {
|
||||
if (addrinc) addrinc = sizeof(iodata_t);
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
WIZCHIP.IF.BUS._write_data(AddrSel, *buf++);
|
||||
AddrSel += (uint32_t)addrinc;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t wizchip_spi_readbyte(void) { return 0; }
|
||||
void wizchip_spi_writebyte(uint8_t wb) {}
|
||||
|
||||
void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {
|
||||
for (uint16_t i = 0; i < len; i++) *pBuf++ = WIZCHIP.IF.SPI._read_byte();
|
||||
}
|
||||
|
||||
void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {
|
||||
for (uint16_t i = 0; i < len; i++) WIZCHIP.IF.SPI._write_byte(*pBuf++);
|
||||
}
|
||||
|
||||
void wizchip_qspi_read(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len) {}
|
||||
void wizchip_qspi_write(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len) {}
|
||||
|
||||
_WIZCHIP WIZCHIP = {
|
||||
_WIZCHIP_IO_MODE_,
|
||||
_WIZCHIP_ID_,
|
||||
{ wizchip_cris_enter, wizchip_cris_exit },
|
||||
{ wizchip_cs_select, wizchip_cs_deselect },
|
||||
{ { wizchip_bus_readdata, wizchip_bus_writedata } }
|
||||
};
|
||||
|
||||
static uint8_t _DNS_[4];
|
||||
static uint8_t _DNS6_[16];
|
||||
static ipconf_mode _IPMODE_;
|
||||
|
||||
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void)) {
|
||||
if (!cris_en || !cris_ex) {
|
||||
WIZCHIP.CRIS._enter = wizchip_cris_enter;
|
||||
WIZCHIP.CRIS._exit = wizchip_cris_exit;
|
||||
} else {
|
||||
WIZCHIP.CRIS._enter = cris_en;
|
||||
WIZCHIP.CRIS._exit = cris_ex;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void)) {
|
||||
if (!cs_sel || !cs_desel) {
|
||||
WIZCHIP.CS._select = wizchip_cs_select;
|
||||
WIZCHIP.CS._deselect = wizchip_cs_deselect;
|
||||
} else {
|
||||
WIZCHIP.CS._select = cs_sel;
|
||||
WIZCHIP.CS._deselect = cs_desel;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_bus_cbfunc(iodata_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
|
||||
if (!bus_rb || !bus_wb) {
|
||||
WIZCHIP.IF.BUS._read_data = wizchip_bus_readdata;
|
||||
WIZCHIP.IF.BUS._write_data = wizchip_bus_writedata;
|
||||
} else {
|
||||
WIZCHIP.IF.BUS._read_data = bus_rb;
|
||||
WIZCHIP.IF.BUS._write_data = bus_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
|
||||
if (!spi_rb || !spi_wb) {
|
||||
WIZCHIP.IF.SPI._read_byte = wizchip_spi_readbyte;
|
||||
WIZCHIP.IF.SPI._write_byte = wizchip_spi_writebyte;
|
||||
} else {
|
||||
WIZCHIP.IF.SPI._read_byte = spi_rb;
|
||||
WIZCHIP.IF.SPI._write_byte = spi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
|
||||
if (!spi_rb || !spi_wb) {
|
||||
WIZCHIP.IF.SPI._read_burst = wizchip_spi_readburst;
|
||||
WIZCHIP.IF.SPI._write_burst = wizchip_spi_writeburst;
|
||||
} else {
|
||||
WIZCHIP.IF.SPI._read_burst = spi_rb;
|
||||
WIZCHIP.IF.SPI._write_burst = spi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
void reg_wizchip_qspi_cbfunc(void (*qspi_rb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len),
|
||||
void (*qspi_wb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len)) {
|
||||
while (!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_QSPI_));
|
||||
if (!qspi_rb || !qspi_wb) {
|
||||
WIZCHIP.IF.QSPI._read_qspi = wizchip_qspi_read;
|
||||
WIZCHIP.IF.QSPI._write_qspi = wizchip_qspi_write;
|
||||
} else {
|
||||
WIZCHIP.IF.QSPI._read_qspi = qspi_rb;
|
||||
WIZCHIP.IF.QSPI._write_qspi = qspi_wb;
|
||||
}
|
||||
}
|
||||
|
||||
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg) {
|
||||
uint8_t tmp = *(uint8_t*)arg;
|
||||
uint8_t* ptmp[2] = {0, 0};
|
||||
switch (cwtype) {
|
||||
case CW_SYS_LOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYLOCK();
|
||||
break;
|
||||
case CW_SYS_UNLOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPUNLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETUNLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYUNLOCK();
|
||||
break;
|
||||
case CW_GET_SYSLOCK:
|
||||
*(uint8_t*)arg = getSYSR() >> 5;
|
||||
break;
|
||||
case CW_RESET_WIZCHIP:
|
||||
wizchip_sw_reset();
|
||||
break;
|
||||
case CW_INIT_WIZCHIP:
|
||||
if (arg != 0) {
|
||||
ptmp[0] = (uint8_t*)arg;
|
||||
ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
|
||||
}
|
||||
return wizchip_init(ptmp[0], ptmp[1]);
|
||||
case CW_CLR_INTERRUPT:
|
||||
wizchip_clrinterrupt(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTERRUPT:
|
||||
*((intr_kind*)arg) = wizchip_getinterrupt();
|
||||
break;
|
||||
case CW_SET_INTRMASK:
|
||||
wizchip_setinterruptmask(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTRMASK:
|
||||
*((intr_kind*)arg) = wizchip_getinterruptmask();
|
||||
break;
|
||||
case CW_SET_INTRTIME:
|
||||
setINTPTMR(*(uint16_t*)arg);
|
||||
break;
|
||||
case CW_GET_INTRTIME:
|
||||
*(uint16_t*)arg = getINTPTMR();
|
||||
break;
|
||||
case CW_GET_ID:
|
||||
((uint8_t*)arg)[0] = WIZCHIP.id[0];
|
||||
((uint8_t*)arg)[1] = WIZCHIP.id[1];
|
||||
((uint8_t*)arg)[2] = WIZCHIP.id[2];
|
||||
((uint8_t*)arg)[3] = WIZCHIP.id[3];
|
||||
((uint8_t*)arg)[4] = WIZCHIP.id[4];
|
||||
((uint8_t*)arg)[5] = WIZCHIP.id[5];
|
||||
((uint8_t*)arg)[6] = 0;
|
||||
break;
|
||||
case CW_GET_VER:
|
||||
*(uint16_t*)arg = getVER();
|
||||
break;
|
||||
case CW_RESET_PHY:
|
||||
wizphy_reset();
|
||||
break;
|
||||
case CW_SET_PHYCONF:
|
||||
wizphy_setphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYCONF:
|
||||
wizphy_getphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYSTATUS:
|
||||
break;
|
||||
case CW_SET_PHYPOWMODE:
|
||||
wizphy_setphypmode(*(uint8_t*)arg);
|
||||
break;
|
||||
case CW_GET_PHYPOWMODE:
|
||||
tmp = wizphy_getphypmode();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
case CW_GET_PHYLINK:
|
||||
tmp = wizphy_getphylink();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg) {
|
||||
switch (cntype) {
|
||||
case CN_SET_NETINFO:
|
||||
wizchip_setnetinfo((wiz_NetInfo*)arg);
|
||||
break;
|
||||
case CN_GET_NETINFO:
|
||||
wizchip_getnetinfo((wiz_NetInfo*)arg);
|
||||
break;
|
||||
case CN_SET_NETMODE:
|
||||
wizchip_setnetmode(*(netmode_type*)arg);
|
||||
break;
|
||||
case CN_GET_NETMODE:
|
||||
*(netmode_type*)arg = wizchip_getnetmode();
|
||||
break;
|
||||
case CN_SET_TIMEOUT:
|
||||
wizchip_settimeout((wiz_NetTimeout*)arg);
|
||||
break;
|
||||
case CN_GET_TIMEOUT:
|
||||
wizchip_gettimeout((wiz_NetTimeout*)arg);
|
||||
break;
|
||||
case CN_SET_PREFER:
|
||||
setSLPSR(*(uint8_t*)arg);
|
||||
break;
|
||||
case CN_GET_PREFER:
|
||||
*(uint8_t*)arg = getSLPSR();
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg) {
|
||||
switch (cnstype) {
|
||||
case CNS_ARP:
|
||||
return wizchip_arp((wiz_ARP*)arg);
|
||||
case CNS_PING:
|
||||
return wizchip_ping((wiz_PING*)arg);
|
||||
case CNS_DAD:
|
||||
return wizchip_dad((uint8_t*)arg);
|
||||
case CNS_SLAAC:
|
||||
return wizchip_slaac((wiz_Prefix*)arg);
|
||||
case CNS_UNSOL_NA:
|
||||
return wizchip_unsolicited();
|
||||
case CNS_GET_PREFIX:
|
||||
return wizchip_getprefix((wiz_Prefix*)arg);
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_sw_reset(void) {
|
||||
uint8_t gw[4], sn[4], sip[4];
|
||||
uint8_t mac[6];
|
||||
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
||||
uint8_t islock = getSYSR();
|
||||
|
||||
CHIPUNLOCK();
|
||||
getSHAR(mac);
|
||||
getGAR(gw); getSUBR(sn); getSIPR(sip);
|
||||
getGA6R(gw6); getSUB6R(sn6); getLLAR(lla); getGUAR(gua);
|
||||
setSYCR0(SYCR0_RST);
|
||||
getSYCR0();
|
||||
|
||||
NETUNLOCK();
|
||||
setSHAR(mac);
|
||||
setGAR(gw); setSUBR(sn); setSIPR(sip);
|
||||
setGA6R(gw6); setSUB6R(sn6); setLLAR(lla); setGUAR(gua);
|
||||
|
||||
if (islock & SYSR_CHPL) CHIPLOCK();
|
||||
if (islock & SYSR_NETL) NETLOCK();
|
||||
}
|
||||
|
||||
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize) {
|
||||
int8_t i;
|
||||
int8_t tmp = 0;
|
||||
wizchip_sw_reset();
|
||||
|
||||
if (txsize) {
|
||||
tmp = 0;
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
tmp += txsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
setSn_TXBUF_SIZE(i, txsize[i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (rxsize) {
|
||||
tmp = 0;
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
tmp += rxsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
setSn_RXBUF_SIZE(i, rxsize[i]);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wizchip_clrinterrupt(intr_kind intr) {
|
||||
uint8_t ir = (uint8_t)intr;
|
||||
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
||||
uint8_t slir = (uint8_t)((uint32_t)intr >> 16);
|
||||
setIRCLR(ir);
|
||||
for (int i = 0; i < _WIZCHIP_SOCK_NUM_; i++) {
|
||||
if (sir & (1 << i)) setSn_IRCLR(i, 0xFF);
|
||||
}
|
||||
setSLIRCLR(slir);
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterrupt(void) {
|
||||
uint8_t ir = getIR();
|
||||
uint8_t sir = getSIR();
|
||||
uint32_t ret = sir;
|
||||
ret = (ret << 8) + ir;
|
||||
ret = (((uint32_t)getSLIR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
void wizchip_setinterruptmask(intr_kind intr) {
|
||||
uint8_t imr = (uint8_t)intr;
|
||||
uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
|
||||
uint8_t slimr = (uint8_t)((uint32_t)intr >> 16);
|
||||
setIMR(imr);
|
||||
setSIMR(simr);
|
||||
setSLIMR(slimr);
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterruptmask(void) {
|
||||
uint8_t imr = getIMR();
|
||||
uint8_t simr = getSIMR();
|
||||
uint32_t ret = simr;
|
||||
ret = (ret << 8) + imr;
|
||||
ret = (((uint32_t)getSLIMR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
int8_t wizphy_getphylink(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
return (getPHYSR() & PHYSR_LNK);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
if (wiz_mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON;
|
||||
return PHY_LINK_OFF;
|
||||
#endif
|
||||
}
|
||||
|
||||
int8_t wizphy_getphypmode(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
if (getPHYCR1() & PHYCR1_PWDN) return PHY_POWER_DOWN;
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
if (wiz_mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN;
|
||||
#endif
|
||||
return PHY_POWER_NORM;
|
||||
}
|
||||
|
||||
void wizphy_reset(void) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYCR1() | PHYCR1_RST;
|
||||
PHYUNLOCK();
|
||||
setPHYCR1(tmp);
|
||||
PHYLOCK();
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
wiz_mdio_write(PHYRAR_BMCR, wiz_mdio_read(PHYRAR_BMCR) | BMCR_RST);
|
||||
while (wiz_mdio_read(PHYRAR_BMCR) & BMCR_RST);
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_setphyconf(wiz_PhyConf* phyconf) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = 0;
|
||||
if (phyconf->mode == PHY_MODE_TE) {
|
||||
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
||||
tmp = PHYCR0_AUTO;
|
||||
} else {
|
||||
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
||||
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
||||
tmp = PHYCR0_AUTO;
|
||||
} else {
|
||||
tmp |= 0x04;
|
||||
if (phyconf->speed == PHY_SPEED_10) tmp |= 0x02;
|
||||
if (phyconf->duplex == PHY_DUPLEX_HALF) tmp |= 0x01;
|
||||
}
|
||||
}
|
||||
setPHYCR0(tmp);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (phyconf->mode == PHY_MODE_TE) {
|
||||
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
||||
setPHYCR0(PHYCR0_AUTO);
|
||||
} else {
|
||||
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
||||
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
||||
tmp |= BMCR_ANE;
|
||||
} else {
|
||||
tmp &= ~(BMCR_ANE | BMCR_DPX | BMCR_SPD);
|
||||
if (phyconf->duplex == PHY_DUPLEX_FULL) tmp |= BMCR_DPX;
|
||||
if (phyconf->speed == PHY_SPEED_100) tmp |= BMCR_SPD;
|
||||
}
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_getphyconf(wiz_PhyConf* phyconf) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYSR();
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
||||
phyconf->speed = (tmp & (1 << 4)) ? PHY_SPEED_10 : PHY_SPEED_100;
|
||||
phyconf->duplex = (tmp & (1 << 3)) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & BMCR_ANE) ? PHY_MODE_AUTONEGO : PHY_MODE_MANUAL);
|
||||
phyconf->duplex = (tmp & BMCR_DPX) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
|
||||
phyconf->speed = (tmp & BMCR_SPD) ? PHY_SPEED_100 : PHY_SPEED_10;
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizphy_getphystat(wiz_PhyConf* phyconf) {
|
||||
uint8_t tmp = getPHYSR();
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
||||
phyconf->speed = (tmp & PHYSR_SPD) ? PHY_SPEED_10 : PHY_SPEED_100;
|
||||
phyconf->duplex = (tmp & PHYSR_DPX) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
||||
}
|
||||
|
||||
void wizphy_setphypmode(uint8_t pmode) {
|
||||
#if (_PHY_IO_MODE_ == _PHY_IO_MODE_PHYCR_)
|
||||
uint8_t tmp = getPHYCR1();
|
||||
if (pmode == PHY_POWER_DOWN) tmp |= PHYCR1_PWDN;
|
||||
else tmp &= ~PHYCR1_PWDN;
|
||||
setPHYCR1(tmp);
|
||||
#elif (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (pmode == PHY_POWER_DOWN) tmp |= BMCR_PWDN;
|
||||
else tmp &= ~BMCR_PWDN;
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
#endif
|
||||
}
|
||||
|
||||
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo) {
|
||||
setSHAR(pnetinfo->mac);
|
||||
setGAR(pnetinfo->gw);
|
||||
setSUBR(pnetinfo->sn);
|
||||
setSIPR(pnetinfo->ip);
|
||||
setGA6R(pnetinfo->gw6);
|
||||
setSUB6R(pnetinfo->sn6);
|
||||
setLLAR(pnetinfo->lla);
|
||||
setGUAR(pnetinfo->gua);
|
||||
for (uint8_t i = 0; i < 4; i++) _DNS_[i] = pnetinfo->dns[i];
|
||||
for (uint8_t i = 0; i < 16; i++) _DNS6_[i] = pnetinfo->dns6[i];
|
||||
_IPMODE_ = pnetinfo->ipmode;
|
||||
}
|
||||
|
||||
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo) {
|
||||
getSHAR(pnetinfo->mac);
|
||||
getGAR(pnetinfo->gw);
|
||||
getSUBR(pnetinfo->sn);
|
||||
getSIPR(pnetinfo->ip);
|
||||
getGA6R(pnetinfo->gw6);
|
||||
getSUB6R(pnetinfo->sn6);
|
||||
getLLAR(pnetinfo->lla);
|
||||
getGUAR(pnetinfo->gua);
|
||||
for (uint8_t i = 0; i < 4; i++) pnetinfo->dns[i] = _DNS_[i];
|
||||
for (uint8_t i = 0; i < 16; i++) pnetinfo->dns6[i] = _DNS6_[i];
|
||||
pnetinfo->ipmode = _IPMODE_;
|
||||
}
|
||||
|
||||
void wizchip_setnetmode(netmode_type netmode) {
|
||||
uint32_t tmp = (uint32_t)netmode;
|
||||
setNETMR((uint8_t)tmp);
|
||||
setNETMR2((uint8_t)(tmp >> 8));
|
||||
setNET4MR((uint8_t)(tmp >> 16));
|
||||
setNET6MR((uint8_t)(tmp >> 24));
|
||||
}
|
||||
|
||||
netmode_type wizchip_getnetmode(void) {
|
||||
uint32_t ret = getNETMR();
|
||||
ret = (ret << 8) + getNETMR2();
|
||||
ret = (ret << 16) + getNET4MR();
|
||||
ret = (ret << 24) + getNET6MR();
|
||||
return (netmode_type)ret;
|
||||
}
|
||||
|
||||
void wizchip_settimeout(wiz_NetTimeout* nettime) {
|
||||
setRCR(nettime->s_retry_cnt);
|
||||
setRTR(nettime->s_time_100us);
|
||||
setSLRCR(nettime->sl_retry_cnt);
|
||||
setSLRTR(nettime->sl_time_100us);
|
||||
}
|
||||
|
||||
void wizchip_gettimeout(wiz_NetTimeout* nettime) {
|
||||
nettime->s_retry_cnt = getRCR();
|
||||
nettime->s_time_100us = getRTR();
|
||||
nettime->sl_retry_cnt = getSLRCR();
|
||||
nettime->sl_time_100us = getSLRTR();
|
||||
}
|
||||
|
||||
int8_t wizchip_arp(wiz_ARP* arp) {
|
||||
uint8_t tmp;
|
||||
if (arp->destinfo.len == 16) {
|
||||
setSLDIP6R(arp->destinfo.ip);
|
||||
setSLCR(SLCR_ARP6);
|
||||
} else {
|
||||
setSLDIP4R(arp->destinfo.ip);
|
||||
setSLCR(SLCR_ARP4);
|
||||
}
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_ARP4 | SLIR_ARP6)) {
|
||||
getSLDHAR(arp->dha);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_ping(wiz_PING* ping) {
|
||||
uint8_t tmp;
|
||||
setPINGIDR(ping->id);
|
||||
setPINGSEQR(ping->seq);
|
||||
if (ping->destinfo.len == 16) {
|
||||
setSLDIP6R(ping->destinfo.ip);
|
||||
setSLCR(SLCR_PING6);
|
||||
} else {
|
||||
setSLDIP4R(ping->destinfo.ip);
|
||||
setSLCR(SLCR_PING4);
|
||||
}
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_PING4 | SLIR_PING6)) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_dad(uint8_t* ipv6) {
|
||||
uint8_t tmp;
|
||||
setSLDIP6R(ipv6);
|
||||
setSLCR(SLCR_NS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_slaac(wiz_Prefix* prefix) {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_RS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_RS) {
|
||||
prefix->len = getPLR();
|
||||
prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR();
|
||||
prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_unsolicited(void) {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_UNA);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_getprefix(wiz_Prefix* prefix) {
|
||||
if (getSLIR() & SLIR_RA) {
|
||||
prefix->len = getPLR();
|
||||
prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR();
|
||||
prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
setSLIRCLR(SLIR_RA);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
@@ -0,0 +1,347 @@
|
||||
#include <cstring>
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
static uint8_t dns_[4];
|
||||
static uint8_t dns6_[16];
|
||||
static ipconf_mode ipmode_;
|
||||
|
||||
static constexpr char WIZCHIP_ID[] = "W6300";
|
||||
|
||||
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg) {
|
||||
uint8_t tmp = *(uint8_t*)arg;
|
||||
uint8_t* ptmp[2] = {0, 0};
|
||||
switch (cwtype) {
|
||||
case CW_SYS_LOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYLOCK();
|
||||
break;
|
||||
case CW_SYS_UNLOCK:
|
||||
if (tmp & SYS_CHIP_LOCK) CHIPUNLOCK();
|
||||
if (tmp & SYS_NET_LOCK) NETUNLOCK();
|
||||
if (tmp & SYS_PHY_LOCK) PHYUNLOCK();
|
||||
break;
|
||||
case CW_GET_SYSLOCK:
|
||||
*(uint8_t*)arg = getSYSR() >> 5;
|
||||
break;
|
||||
case CW_RESET_WIZCHIP:
|
||||
wizchip_sw_reset();
|
||||
break;
|
||||
case CW_INIT_WIZCHIP:
|
||||
if (arg) {
|
||||
ptmp[0] = (uint8_t*)arg;
|
||||
ptmp[1] = ptmp[0] + WIZCHIP_SOCK_NUM;
|
||||
}
|
||||
return wizchip_init(ptmp[0], ptmp[1]);
|
||||
case CW_CLR_INTERRUPT:
|
||||
wizchip_clrinterrupt(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTERRUPT:
|
||||
*((intr_kind*)arg) = wizchip_getinterrupt();
|
||||
break;
|
||||
case CW_SET_INTRMASK:
|
||||
wizchip_setinterruptmask(*((intr_kind*)arg));
|
||||
break;
|
||||
case CW_GET_INTRMASK:
|
||||
*((intr_kind*)arg) = wizchip_getinterruptmask();
|
||||
break;
|
||||
case CW_SET_INTRTIME:
|
||||
setINTPTMR(*(uint16_t*)arg);
|
||||
break;
|
||||
case CW_GET_INTRTIME:
|
||||
*(uint16_t*)arg = getINTPTMR();
|
||||
break;
|
||||
case CW_GET_ID:
|
||||
memcpy(arg, WIZCHIP_ID, sizeof(WIZCHIP_ID));
|
||||
break;
|
||||
case CW_GET_VER:
|
||||
*(uint16_t*)arg = getVER();
|
||||
break;
|
||||
case CW_RESET_PHY:
|
||||
wizphy_reset();
|
||||
break;
|
||||
case CW_SET_PHYCONF:
|
||||
wizphy_setphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYCONF:
|
||||
wizphy_getphyconf((wiz_PhyConf*)arg);
|
||||
break;
|
||||
case CW_GET_PHYSTATUS:
|
||||
break;
|
||||
case CW_SET_PHYPOWMODE:
|
||||
wizphy_setphypmode(*(uint8_t*)arg);
|
||||
break;
|
||||
case CW_GET_PHYPOWMODE:
|
||||
tmp = wizphy_getphypmode();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
case CW_GET_PHYLINK:
|
||||
tmp = wizphy_getphylink();
|
||||
if ((int8_t)tmp == -1) return -1;
|
||||
*(uint8_t*)arg = tmp;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg) {
|
||||
switch (cntype) {
|
||||
case CN_SET_NETINFO: wizchip_setnetinfo((wiz_NetInfo*)arg); break;
|
||||
case CN_GET_NETINFO: wizchip_getnetinfo((wiz_NetInfo*)arg); break;
|
||||
case CN_SET_NETMODE: wizchip_setnetmode(*(netmode_type*)arg); break;
|
||||
case CN_GET_NETMODE: *(netmode_type*)arg = wizchip_getnetmode(); break;
|
||||
case CN_SET_TIMEOUT: wizchip_settimeout((wiz_NetTimeout*)arg); break;
|
||||
case CN_GET_TIMEOUT: wizchip_gettimeout((wiz_NetTimeout*)arg); break;
|
||||
case CN_SET_PREFER: setSLPSR(*(uint8_t*)arg); break;
|
||||
case CN_GET_PREFER: *(uint8_t*)arg = getSLPSR(); break;
|
||||
default: return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg) {
|
||||
switch (cnstype) {
|
||||
case CNS_ARP: return wizchip_arp((wiz_ARP*)arg);
|
||||
case CNS_PING: return wizchip_ping((wiz_PING*)arg);
|
||||
case CNS_DAD: return wizchip_dad((uint8_t*)arg);
|
||||
case CNS_SLAAC: return wizchip_slaac((wiz_Prefix*)arg);
|
||||
case CNS_UNSOL_NA: return wizchip_unsolicited();
|
||||
case CNS_GET_PREFIX: return wizchip_getprefix((wiz_Prefix*)arg);
|
||||
default: return -1;
|
||||
}
|
||||
}
|
||||
|
||||
void wizchip_sw_reset() {
|
||||
uint8_t gw[4], sn[4], sip[4], mac[6];
|
||||
uint8_t gw6[16], sn6[16], lla[16], gua[16];
|
||||
uint8_t islock = getSYSR();
|
||||
|
||||
CHIPUNLOCK();
|
||||
getSHAR(mac); getGAR(gw); getSUBR(sn); getSIPR(sip);
|
||||
getGA6R(gw6); getSUB6R(sn6); getLLAR(lla); getGUAR(gua);
|
||||
setSYCR0(SYCR0_RST);
|
||||
getSYCR0();
|
||||
|
||||
NETUNLOCK();
|
||||
setSHAR(mac); setGAR(gw); setSUBR(sn); setSIPR(sip);
|
||||
setGA6R(gw6); setSUB6R(sn6); setLLAR(lla); setGUAR(gua);
|
||||
|
||||
if (islock & SYSR_CHPL) CHIPLOCK();
|
||||
if (islock & SYSR_NETL) NETLOCK();
|
||||
}
|
||||
|
||||
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize) {
|
||||
wizchip_sw_reset();
|
||||
if (txsize) {
|
||||
int8_t tmp = 0;
|
||||
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) {
|
||||
tmp += txsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) setSn_TXBUF_SIZE(i, txsize[i]);
|
||||
}
|
||||
if (rxsize) {
|
||||
int8_t tmp = 0;
|
||||
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) {
|
||||
tmp += rxsize[i];
|
||||
if (tmp > 32) return -1;
|
||||
}
|
||||
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++) setSn_RXBUF_SIZE(i, rxsize[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wizchip_clrinterrupt(intr_kind intr) {
|
||||
setIRCLR((uint8_t)intr);
|
||||
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
|
||||
for (int i = 0; i < WIZCHIP_SOCK_NUM; i++)
|
||||
if (sir & (1 << i)) setSn_IRCLR(i, 0xFF);
|
||||
setSLIRCLR((uint8_t)((uint32_t)intr >> 16));
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterrupt() {
|
||||
uint32_t ret = getSIR();
|
||||
ret = (ret << 8) + getIR();
|
||||
ret = (((uint32_t)getSLIR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
void wizchip_setinterruptmask(intr_kind intr) {
|
||||
setIMR((uint8_t)intr);
|
||||
setSIMR((uint8_t)((uint16_t)intr >> 8));
|
||||
setSLIMR((uint8_t)((uint32_t)intr >> 16));
|
||||
}
|
||||
|
||||
intr_kind wizchip_getinterruptmask() {
|
||||
uint32_t ret = getSIMR();
|
||||
ret = (ret << 8) + getIMR();
|
||||
ret = (((uint32_t)getSLIMR()) << 16) | ret;
|
||||
return (intr_kind)ret;
|
||||
}
|
||||
|
||||
int8_t wizphy_getphylink() {
|
||||
if (wiz_mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON;
|
||||
return PHY_LINK_OFF;
|
||||
}
|
||||
|
||||
int8_t wizphy_getphypmode() {
|
||||
if (wiz_mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN;
|
||||
return PHY_POWER_NORM;
|
||||
}
|
||||
|
||||
void wizphy_reset() {
|
||||
wiz_mdio_write(PHYRAR_BMCR, wiz_mdio_read(PHYRAR_BMCR) | BMCR_RST);
|
||||
while (wiz_mdio_read(PHYRAR_BMCR) & BMCR_RST);
|
||||
}
|
||||
|
||||
void wizphy_setphyconf(wiz_PhyConf* phyconf) {
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (phyconf->mode == PHY_MODE_TE) {
|
||||
setPHYCR1(getPHYCR1() | PHYCR1_TE);
|
||||
setPHYCR0(PHYCR0_AUTO);
|
||||
} else {
|
||||
setPHYCR1(getPHYCR1() & ~PHYCR1_TE);
|
||||
if (phyconf->mode == PHY_MODE_AUTONEGO) {
|
||||
tmp |= BMCR_ANE;
|
||||
} else {
|
||||
tmp &= ~(BMCR_ANE | BMCR_DPX | BMCR_SPD);
|
||||
if (phyconf->duplex == PHY_DUPLEX_FULL) tmp |= BMCR_DPX;
|
||||
if (phyconf->speed == PHY_SPEED_100) tmp |= BMCR_SPD;
|
||||
}
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
void wizphy_getphyconf(wiz_PhyConf* phyconf) {
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & BMCR_ANE) ? PHY_MODE_AUTONEGO : PHY_MODE_MANUAL);
|
||||
phyconf->duplex = (tmp & BMCR_DPX) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
|
||||
phyconf->speed = (tmp & BMCR_SPD) ? PHY_SPEED_100 : PHY_SPEED_10;
|
||||
}
|
||||
|
||||
void wizphy_getphystat(wiz_PhyConf* phyconf) {
|
||||
uint8_t tmp = getPHYSR();
|
||||
phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & (1 << 5)) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO);
|
||||
phyconf->speed = (tmp & PHYSR_SPD) ? PHY_SPEED_10 : PHY_SPEED_100;
|
||||
phyconf->duplex = (tmp & PHYSR_DPX) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL;
|
||||
}
|
||||
|
||||
void wizphy_setphypmode(uint8_t pmode) {
|
||||
uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR);
|
||||
if (pmode == PHY_POWER_DOWN) tmp |= BMCR_PWDN;
|
||||
else tmp &= ~BMCR_PWDN;
|
||||
wiz_mdio_write(PHYRAR_BMCR, tmp);
|
||||
}
|
||||
|
||||
void wizchip_setnetinfo(wiz_NetInfo* p) {
|
||||
setSHAR(p->mac); setGAR(p->gw); setSUBR(p->sn); setSIPR(p->ip);
|
||||
setGA6R(p->gw6); setSUB6R(p->sn6); setLLAR(p->lla); setGUAR(p->gua);
|
||||
memcpy(dns_, p->dns, 4);
|
||||
memcpy(dns6_, p->dns6, 16);
|
||||
ipmode_ = p->ipmode;
|
||||
}
|
||||
|
||||
void wizchip_getnetinfo(wiz_NetInfo* p) {
|
||||
getSHAR(p->mac); getGAR(p->gw); getSUBR(p->sn); getSIPR(p->ip);
|
||||
getGA6R(p->gw6); getSUB6R(p->sn6); getLLAR(p->lla); getGUAR(p->gua);
|
||||
memcpy(p->dns, dns_, 4);
|
||||
memcpy(p->dns6, dns6_, 16);
|
||||
p->ipmode = ipmode_;
|
||||
}
|
||||
|
||||
void wizchip_setnetmode(netmode_type netmode) {
|
||||
uint32_t tmp = (uint32_t)netmode;
|
||||
setNETMR((uint8_t)tmp);
|
||||
setNETMR2((uint8_t)(tmp >> 8));
|
||||
setNET4MR((uint8_t)(tmp >> 16));
|
||||
setNET6MR((uint8_t)(tmp >> 24));
|
||||
}
|
||||
|
||||
netmode_type wizchip_getnetmode() {
|
||||
uint32_t ret = getNETMR();
|
||||
ret = (ret << 8) + getNETMR2();
|
||||
ret = (ret << 16) + getNET4MR();
|
||||
ret = (ret << 24) + getNET6MR();
|
||||
return (netmode_type)ret;
|
||||
}
|
||||
|
||||
void wizchip_settimeout(wiz_NetTimeout* t) {
|
||||
setRCR(t->s_retry_cnt); setRTR(t->s_time_100us);
|
||||
setSLRCR(t->sl_retry_cnt); setSLRTR(t->sl_time_100us);
|
||||
}
|
||||
|
||||
void wizchip_gettimeout(wiz_NetTimeout* t) {
|
||||
t->s_retry_cnt = getRCR(); t->s_time_100us = getRTR();
|
||||
t->sl_retry_cnt = getSLRCR(); t->sl_time_100us = getSLRTR();
|
||||
}
|
||||
|
||||
int8_t wizchip_arp(wiz_ARP* arp) {
|
||||
uint8_t tmp;
|
||||
if (arp->destinfo.len == 16) { setSLDIP6R(arp->destinfo.ip); setSLCR(SLCR_ARP6); }
|
||||
else { setSLDIP4R(arp->destinfo.ip); setSLCR(SLCR_ARP4); }
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_ARP4 | SLIR_ARP6)) { getSLDHAR(arp->dha); return 0; }
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_ping(wiz_PING* ping) {
|
||||
uint8_t tmp;
|
||||
setPINGIDR(ping->id); setPINGSEQR(ping->seq);
|
||||
if (ping->destinfo.len == 16) { setSLDIP6R(ping->destinfo.ip); setSLCR(SLCR_PING6); }
|
||||
else { setSLDIP4R(ping->destinfo.ip); setSLCR(SLCR_PING4); }
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & (SLIR_PING4 | SLIR_PING6)) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_dad(uint8_t* ipv6) {
|
||||
uint8_t tmp;
|
||||
setSLDIP6R(ipv6); setSLCR(SLCR_NS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_slaac(wiz_Prefix* prefix) {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_RS);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_RS) {
|
||||
prefix->len = getPLR(); prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR(); prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_unsolicited() {
|
||||
uint8_t tmp;
|
||||
setSLCR(SLCR_UNA);
|
||||
while (getSLCR());
|
||||
while ((tmp = getSLIR()) == 0x00);
|
||||
setSLIRCLR(~SLIR_RA);
|
||||
if (tmp & SLIR_TOUT) return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int8_t wizchip_getprefix(wiz_Prefix* prefix) {
|
||||
if (getSLIR() & SLIR_RA) {
|
||||
prefix->len = getPLR(); prefix->flag = getPFR();
|
||||
prefix->valid_lifetime = getVLTR(); prefix->preferred_lifetime = getPLTR();
|
||||
getPAR(prefix->prefix);
|
||||
setSLIRCLR(SLIR_RA);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
+99
-241
@@ -1,294 +1,158 @@
|
||||
#ifndef _WIZCHIP_CONF_H_
|
||||
#define _WIZCHIP_CONF_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
|
||||
#define W6300 6300
|
||||
|
||||
#ifndef _WIZCHIP_
|
||||
#define _WIZCHIP_ W6300
|
||||
#endif
|
||||
|
||||
#define _WIZCHIP_IO_MODE_NONE_ 0x0000
|
||||
#define _WIZCHIP_IO_MODE_BUS_ 0x0100
|
||||
#define _WIZCHIP_IO_MODE_SPI_ 0x0200
|
||||
#define _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1)
|
||||
#define _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2)
|
||||
#define _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1)
|
||||
#define _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2)
|
||||
#define _WIZCHIP_IO_MODE_SPI_5500_ (_WIZCHIP_IO_MODE_SPI_ + 3)
|
||||
#define _WIZCHIP_IO_MODE_SPI_QSPI_ (_WIZCHIP_IO_MODE_SPI_ + 4)
|
||||
|
||||
#define _PHY_IO_MODE_PHYCR_ 0x0000
|
||||
#define _PHY_IO_MODE_MII_ 0x0010
|
||||
#define _PHY_IO_MODE_ _PHY_IO_MODE_MII_
|
||||
|
||||
#define _WIZCHIP_QSPI_MODE_ (0x02 << 6)
|
||||
#define _WIZCHIP_QSPI_MODE_ (0x02 << 6)
|
||||
|
||||
#define _WIZCHIP_ID_ "W6300\0"
|
||||
#define _WIZCHIP_IO_MODE_ ((_WIZCHIP_IO_MODE_SPI_ & 0xff00) | (_WIZCHIP_QSPI_MODE_ & 0x00ff))
|
||||
using iodata_t = uint8_t;
|
||||
using datasize_t = int16_t;
|
||||
|
||||
typedef uint8_t iodata_t;
|
||||
typedef int16_t datasize_t;
|
||||
#include "w6300.h"
|
||||
|
||||
#ifndef _WIZCHIP_IO_BASE_
|
||||
#define _WIZCHIP_IO_BASE_ 0x00000000
|
||||
#endif
|
||||
constexpr int WIZCHIP_SOCK_NUM = 8;
|
||||
#define _WIZCHIP_SOCK_NUM_ WIZCHIP_SOCK_NUM
|
||||
|
||||
#define _WIZCHIP_SOCK_NUM_ 8
|
||||
enum ctlwizchip_type {
|
||||
CW_SYS_LOCK, CW_SYS_UNLOCK, CW_GET_SYSLOCK,
|
||||
CW_RESET_WIZCHIP, CW_INIT_WIZCHIP,
|
||||
CW_GET_INTERRUPT, CW_CLR_INTERRUPT, CW_SET_INTRMASK, CW_GET_INTRMASK,
|
||||
CW_SET_INTRTIME, CW_GET_INTRTIME, CW_SET_IEN, CW_GET_IEN,
|
||||
CW_GET_ID, CW_GET_VER, CW_SET_SYSCLK, CW_GET_SYSCLK,
|
||||
CW_RESET_PHY, CW_SET_PHYCONF, CW_GET_PHYCONF, CW_GET_PHYSTATUS,
|
||||
CW_SET_PHYPOWMODE, CW_GET_PHYPOWMODE, CW_GET_PHYLINK
|
||||
};
|
||||
|
||||
typedef struct __WIZCHIP {
|
||||
uint16_t if_mode;
|
||||
uint8_t id[8];
|
||||
struct _CRIS {
|
||||
void (*_enter)(void);
|
||||
void (*_exit)(void);
|
||||
} CRIS;
|
||||
struct _CS {
|
||||
void (*_select)(void);
|
||||
void (*_deselect)(void);
|
||||
} CS;
|
||||
union _IF {
|
||||
struct {
|
||||
iodata_t (*_read_data)(uint32_t AddrSel);
|
||||
void (*_write_data)(uint32_t AddrSel, iodata_t wb);
|
||||
void (*_read_data_buf)(uint32_t AddrSel, iodata_t* pBuf, int16_t len, uint8_t addrinc);
|
||||
void (*_write_data_buf)(uint32_t AddrSel, iodata_t* pBuf, int16_t len, uint8_t addrinc);
|
||||
} BUS;
|
||||
struct {
|
||||
uint8_t (*_read_byte)(void);
|
||||
void (*_write_byte)(uint8_t wb);
|
||||
void (*_read_burst)(uint8_t* pBuf, uint16_t len);
|
||||
void (*_write_burst)(uint8_t* pBuf, uint16_t len);
|
||||
} SPI;
|
||||
struct {
|
||||
void (*_read_qspi)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
void (*_write_qspi)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
} QSPI;
|
||||
} IF;
|
||||
} _WIZCHIP;
|
||||
enum ctlnetwork_type {
|
||||
CN_SET_NETINFO, CN_GET_NETINFO, CN_SET_NETMODE, CN_GET_NETMODE,
|
||||
CN_SET_TIMEOUT, CN_GET_TIMEOUT, CN_SET_PREFER, CN_GET_PREFER,
|
||||
};
|
||||
|
||||
extern _WIZCHIP WIZCHIP;
|
||||
enum ctlnetservice_type {
|
||||
CNS_ARP, CNS_PING, CNS_DAD, CNS_SLAAC, CNS_UNSOL_NA, CNS_GET_PREFIX
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
CW_SYS_LOCK,
|
||||
CW_SYS_UNLOCK,
|
||||
CW_GET_SYSLOCK,
|
||||
CW_RESET_WIZCHIP,
|
||||
CW_INIT_WIZCHIP,
|
||||
CW_GET_INTERRUPT,
|
||||
CW_CLR_INTERRUPT,
|
||||
CW_SET_INTRMASK,
|
||||
CW_GET_INTRMASK,
|
||||
CW_SET_INTRTIME,
|
||||
CW_GET_INTRTIME,
|
||||
CW_SET_IEN,
|
||||
CW_GET_IEN,
|
||||
CW_GET_ID,
|
||||
CW_GET_VER,
|
||||
CW_SET_SYSCLK,
|
||||
CW_GET_SYSCLK,
|
||||
CW_RESET_PHY,
|
||||
CW_SET_PHYCONF,
|
||||
CW_GET_PHYCONF,
|
||||
CW_GET_PHYSTATUS,
|
||||
CW_SET_PHYPOWMODE,
|
||||
CW_GET_PHYPOWMODE,
|
||||
CW_GET_PHYLINK
|
||||
} ctlwizchip_type;
|
||||
enum intr_kind : uint32_t {
|
||||
IK_PPPOE_TERMINATED = (1 << 0), IK_DEST_UNREACH = (1 << 1), IK_IP_CONFLICT = (1 << 2),
|
||||
IK_DEST_UNREACH6 = (1 << 4), IK_WOL = (1 << 7), IK_NET_ALL = 0x97,
|
||||
IK_SOCK_0 = (1 << 8), IK_SOCK_1 = (1 << 9), IK_SOCK_2 = (1 << 10), IK_SOCK_3 = (1 << 11),
|
||||
IK_SOCK_4 = (1 << 12), IK_SOCK_5 = (1 << 13), IK_SOCK_6 = (1 << 14), IK_SOCK_7 = (1 << 15),
|
||||
IK_SOCK_ALL = (0xFF << 8),
|
||||
IK_SOCKL_TOUT = (1 << 16), IK_SOCKL_ARP4 = (1 << 17), IK_SOCKL_PING4 = (1 << 18),
|
||||
IK_SOCKL_ARP6 = (1 << 19), IK_SOCKL_PING6 = (1 << 20), IK_SOCKL_NS = (1 << 21),
|
||||
IK_SOCKL_RS = (1 << 22), IK_SOCKL_RA = (1 << 23), IK_SOCKL_ALL = (0xFF << 16),
|
||||
IK_INT_ALL = 0x00FFFF97
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
CN_SET_NETINFO,
|
||||
CN_GET_NETINFO,
|
||||
CN_SET_NETMODE,
|
||||
CN_GET_NETMODE,
|
||||
CN_SET_TIMEOUT,
|
||||
CN_GET_TIMEOUT,
|
||||
CN_SET_PREFER,
|
||||
CN_GET_PREFER,
|
||||
} ctlnetwork_type;
|
||||
constexpr uint8_t SYS_CHIP_LOCK = (1 << 2);
|
||||
constexpr uint8_t SYS_NET_LOCK = (1 << 1);
|
||||
constexpr uint8_t SYS_PHY_LOCK = (1 << 0);
|
||||
|
||||
typedef enum {
|
||||
CNS_ARP,
|
||||
CNS_PING,
|
||||
CNS_DAD,
|
||||
CNS_SLAAC,
|
||||
CNS_UNSOL_NA,
|
||||
CNS_GET_PREFIX
|
||||
} ctlnetservice_type;
|
||||
constexpr uint8_t PHY_MODE_MANUAL = 0;
|
||||
constexpr uint8_t PHY_MODE_AUTONEGO = 1;
|
||||
constexpr uint8_t PHY_MODE_TE = 2;
|
||||
constexpr uint8_t PHY_CONFBY_HW = 0;
|
||||
constexpr uint8_t PHY_CONFBY_SW = 1;
|
||||
constexpr uint8_t PHY_SPEED_10 = 0;
|
||||
constexpr uint8_t PHY_SPEED_100 = 1;
|
||||
constexpr uint8_t PHY_DUPLEX_HALF = 0;
|
||||
constexpr uint8_t PHY_DUPLEX_FULL = 1;
|
||||
constexpr uint8_t PHY_LINK_OFF = 0;
|
||||
constexpr uint8_t PHY_LINK_ON = 1;
|
||||
constexpr uint8_t PHY_POWER_NORM = 0;
|
||||
constexpr uint8_t PHY_POWER_DOWN = 1;
|
||||
|
||||
typedef enum {
|
||||
IK_PPPOE_TERMINATED = (1 << 0),
|
||||
IK_DEST_UNREACH = (1 << 1),
|
||||
IK_IP_CONFLICT = (1 << 2),
|
||||
IK_DEST_UNREACH6 = (1 << 4),
|
||||
IK_WOL = (1 << 7),
|
||||
IK_NET_ALL = (0x97),
|
||||
IK_SOCK_0 = (1 << 8),
|
||||
IK_SOCK_1 = (1 << 9),
|
||||
IK_SOCK_2 = (1 << 10),
|
||||
IK_SOCK_3 = (1 << 11),
|
||||
IK_SOCK_4 = (1 << 12),
|
||||
IK_SOCK_5 = (1 << 13),
|
||||
IK_SOCK_6 = (1 << 14),
|
||||
IK_SOCK_7 = (1 << 15),
|
||||
IK_SOCK_ALL = (0xFF << 8),
|
||||
IK_SOCKL_TOUT = (1 << 16),
|
||||
IK_SOCKL_ARP4 = (1 << 17),
|
||||
IK_SOCKL_PING4 = (1 << 18),
|
||||
IK_SOCKL_ARP6 = (1 << 19),
|
||||
IK_SOCKL_PING6 = (1 << 20),
|
||||
IK_SOCKL_NS = (1 << 21),
|
||||
IK_SOCKL_RS = (1 << 22),
|
||||
IK_SOCKL_RA = (1 << 23),
|
||||
IK_SOCKL_ALL = (0xFF << 16),
|
||||
IK_INT_ALL = (0x00FFFF97)
|
||||
} intr_kind;
|
||||
|
||||
#define SYS_CHIP_LOCK (1<<2)
|
||||
#define SYS_NET_LOCK (1<<1)
|
||||
#define SYS_PHY_LOCK (1<<0)
|
||||
|
||||
#define SYSCLK_100MHZ 0
|
||||
#define SYSCLK_25MHZ 1
|
||||
|
||||
#define PHY_MODE_MANUAL 0
|
||||
#define PHY_MODE_AUTONEGO 1
|
||||
#define PHY_MODE_TE 2
|
||||
|
||||
#define IPV6_ADDR_AUTO 0x00
|
||||
#define IPV6_ADDR_LLA 0x02
|
||||
#define IPV6_ADDR_GUA 0x03
|
||||
|
||||
#define PHY_CONFBY_HW 0
|
||||
#define PHY_CONFBY_SW 1
|
||||
#define PHY_SPEED_10 0
|
||||
#define PHY_SPEED_100 1
|
||||
#define PHY_DUPLEX_HALF 0
|
||||
#define PHY_DUPLEX_FULL 1
|
||||
#define PHY_LINK_OFF 0
|
||||
#define PHY_LINK_ON 1
|
||||
#define PHY_POWER_NORM 0
|
||||
#define PHY_POWER_DOWN 1
|
||||
|
||||
typedef struct wiz_PhyConf_t {
|
||||
struct wiz_PhyConf {
|
||||
uint8_t by;
|
||||
uint8_t mode;
|
||||
uint8_t speed;
|
||||
uint8_t duplex;
|
||||
} wiz_PhyConf;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NETINFO_NONE = 0x00,
|
||||
NETINFO_STATIC_V4 = 0x01,
|
||||
NETINFO_STATIC_V6 = 0x02,
|
||||
NETINFO_STATIC_ALL = 0x03,
|
||||
NETINFO_SLAAC_V6 = 0x04,
|
||||
NETINFO_DHCP_V4 = 0x10,
|
||||
NETINFO_DHCP_V6 = 0x20,
|
||||
NETINFO_DHCP_ALL = 0x30
|
||||
} ipconf_mode;
|
||||
enum ipconf_mode : uint8_t {
|
||||
NETINFO_NONE = 0x00, NETINFO_STATIC_V4 = 0x01, NETINFO_STATIC_V6 = 0x02,
|
||||
NETINFO_STATIC_ALL = 0x03, NETINFO_SLAAC_V6 = 0x04,
|
||||
NETINFO_DHCP_V4 = 0x10, NETINFO_DHCP_V6 = 0x20, NETINFO_DHCP_ALL = 0x30
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NETINFO_STATIC = 1,
|
||||
NETINFO_DHCP
|
||||
} dhcp_mode;
|
||||
enum dhcp_mode : uint8_t { NETINFO_STATIC = 1, NETINFO_DHCP };
|
||||
|
||||
typedef struct wiz_NetInfo_t {
|
||||
uint8_t mac[6];
|
||||
uint8_t ip[4];
|
||||
uint8_t sn[4];
|
||||
uint8_t gw[4];
|
||||
uint8_t lla[16];
|
||||
uint8_t gua[16];
|
||||
uint8_t sn6[16];
|
||||
uint8_t gw6[16];
|
||||
uint8_t dns[4];
|
||||
uint8_t dns6[16];
|
||||
struct wiz_NetInfo {
|
||||
uint8_t mac[6];
|
||||
uint8_t ip[4];
|
||||
uint8_t sn[4];
|
||||
uint8_t gw[4];
|
||||
uint8_t lla[16];
|
||||
uint8_t gua[16];
|
||||
uint8_t sn6[16];
|
||||
uint8_t gw6[16];
|
||||
uint8_t dns[4];
|
||||
uint8_t dns6[16];
|
||||
ipconf_mode ipmode;
|
||||
dhcp_mode dhcp;
|
||||
} wiz_NetInfo;
|
||||
dhcp_mode dhcp;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NM_IPB_V4 = (1 << 0),
|
||||
NM_IPB_V6 = (1 << 1),
|
||||
NM_WOL = (1 << 2),
|
||||
NM_PB6_MULTI = (1 << 4),
|
||||
NM_PB6_ALLNODE = (1 << 5),
|
||||
NM_MR_MASK = (0x37),
|
||||
NM_PPPoE = (1 << 8),
|
||||
NM_DHA_SELECT = (1 << 15),
|
||||
NM_MR2_MASK = (0x09 << 8),
|
||||
NM_PB4_ALL = (1 << 16),
|
||||
NM_TRSTB_V4 = (1 << 17),
|
||||
NM_PARP_V4 = (1 << 18),
|
||||
NM_UNRB_V4 = (1 << 19),
|
||||
NM_NET4_MASK = (0x0F << 16),
|
||||
NM_PB6_ALL = (1 << 24),
|
||||
NM_TRSTB_V6 = (1 << 25),
|
||||
NM_PARP_V6 = (1 << 26),
|
||||
NM_UNRB_V6 = (1 << 27),
|
||||
NM_NET6_MASK = (0x0F << 24),
|
||||
NM_MASK_ALL = (0x0F0F0937)
|
||||
} netmode_type;
|
||||
enum netmode_type : uint32_t {
|
||||
NM_IPB_V4 = (1 << 0), NM_IPB_V6 = (1 << 1), NM_WOL = (1 << 2),
|
||||
NM_PB6_MULTI = (1 << 4), NM_PB6_ALLNODE = (1 << 5), NM_MR_MASK = 0x37,
|
||||
NM_PPPoE = (1 << 8), NM_DHA_SELECT = (1 << 15), NM_MR2_MASK = (0x09 << 8),
|
||||
NM_PB4_ALL = (1 << 16), NM_TRSTB_V4 = (1 << 17), NM_PARP_V4 = (1 << 18),
|
||||
NM_UNRB_V4 = (1 << 19), NM_NET4_MASK = (0x0F << 16),
|
||||
NM_PB6_ALL = (1 << 24), NM_TRSTB_V6 = (1 << 25), NM_PARP_V6 = (1 << 26),
|
||||
NM_UNRB_V6 = (1 << 27), NM_NET6_MASK = (0x0F << 24),
|
||||
NM_MASK_ALL = 0x0F0F0937
|
||||
};
|
||||
|
||||
typedef struct wiz_NetTimeout_t {
|
||||
struct wiz_NetTimeout {
|
||||
uint8_t s_retry_cnt;
|
||||
uint16_t s_time_100us;
|
||||
uint8_t sl_retry_cnt;
|
||||
uint16_t sl_time_100us;
|
||||
} wiz_NetTimeout;
|
||||
};
|
||||
|
||||
typedef struct wiz_IPAddress_t {
|
||||
struct wiz_IPAddress {
|
||||
uint8_t ip[16];
|
||||
uint8_t len;
|
||||
} wiz_IPAddress;
|
||||
};
|
||||
|
||||
typedef struct wiz_Prefix_t {
|
||||
struct wiz_Prefix {
|
||||
uint8_t len;
|
||||
uint8_t flag;
|
||||
uint32_t valid_lifetime;
|
||||
uint32_t preferred_lifetime;
|
||||
uint8_t prefix[16];
|
||||
} wiz_Prefix;
|
||||
};
|
||||
|
||||
typedef struct wiz_ARP_t {
|
||||
struct wiz_ARP {
|
||||
wiz_IPAddress destinfo;
|
||||
uint8_t dha[6];
|
||||
} wiz_ARP;
|
||||
};
|
||||
|
||||
typedef struct wiz_PING_t {
|
||||
struct wiz_PING {
|
||||
uint16_t id;
|
||||
uint16_t seq;
|
||||
wiz_IPAddress destinfo;
|
||||
} wiz_PING;
|
||||
|
||||
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void));
|
||||
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void));
|
||||
void reg_wizchip_bus_cbfunc(iodata_t (*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb));
|
||||
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb));
|
||||
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len));
|
||||
void reg_wizchip_qspi_cbfunc(void (*qspi_rb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len), void (*qspi_wb)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len));
|
||||
};
|
||||
|
||||
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg);
|
||||
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg);
|
||||
int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg);
|
||||
|
||||
void wizchip_sw_reset(void);
|
||||
void wizchip_sw_reset();
|
||||
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize);
|
||||
void wizchip_clrinterrupt(intr_kind intr);
|
||||
intr_kind wizchip_getinterrupt(void);
|
||||
intr_kind wizchip_getinterrupt();
|
||||
void wizchip_setinterruptmask(intr_kind intr);
|
||||
intr_kind wizchip_getinterruptmask(void);
|
||||
intr_kind wizchip_getinterruptmask();
|
||||
|
||||
int8_t wizphy_getphylink(void);
|
||||
int8_t wizphy_getphypmode(void);
|
||||
void wizphy_reset(void);
|
||||
int8_t wizphy_getphylink();
|
||||
int8_t wizphy_getphypmode();
|
||||
void wizphy_reset();
|
||||
void wizphy_setphyconf(wiz_PhyConf* phyconf);
|
||||
void wizphy_getphyconf(wiz_PhyConf* phyconf);
|
||||
void wizphy_getphystat(wiz_PhyConf* phyconf);
|
||||
@@ -297,7 +161,7 @@ void wizphy_setphypmode(uint8_t pmode);
|
||||
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo);
|
||||
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo);
|
||||
void wizchip_setnetmode(netmode_type netmode);
|
||||
netmode_type wizchip_getnetmode(void);
|
||||
netmode_type wizchip_getnetmode();
|
||||
void wizchip_settimeout(wiz_NetTimeout* nettime);
|
||||
void wizchip_gettimeout(wiz_NetTimeout* nettime);
|
||||
|
||||
@@ -305,11 +169,5 @@ int8_t wizchip_arp(wiz_ARP* arp);
|
||||
int8_t wizchip_ping(wiz_PING* ping);
|
||||
int8_t wizchip_dad(uint8_t* ipv6);
|
||||
int8_t wizchip_slaac(wiz_Prefix* prefix);
|
||||
int8_t wizchip_unsolicited(void);
|
||||
int8_t wizchip_unsolicited();
|
||||
int8_t wizchip_getprefix(wiz_Prefix* prefix);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,383 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/error.h"
|
||||
|
||||
#include "hardware/dma.h"
|
||||
#include "hardware/clocks.h"
|
||||
|
||||
#include "wizchip_conf.h"
|
||||
#include "wizchip_qspi_pio.h"
|
||||
|
||||
#include "wizchip_qspi_pio.pio.h"
|
||||
|
||||
#ifndef PIO_SPI_PREFERRED_PIO
|
||||
#define PIO_SPI_PREFERRED_PIO 1
|
||||
#endif
|
||||
|
||||
#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
|
||||
#define IRQ_SAMPLE_DELAY_NS 100
|
||||
|
||||
#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
|
||||
|
||||
#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
|
||||
#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
|
||||
#define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits)
|
||||
#define PIO_OFFSET_WRITE_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits_end)
|
||||
#define PIO_OFFSET_READ_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_read_bits_end)
|
||||
|
||||
#ifndef PICO_WIZNET_SPI_PIO_INSTANCE_COUNT
|
||||
#define PICO_WIZNET_SPI_PIO_INSTANCE_COUNT 1
|
||||
#endif
|
||||
|
||||
#define SPI_HEADER_LEN 3
|
||||
|
||||
typedef struct spi_pio_state {
|
||||
wiznet_spi_funcs_t *funcs;
|
||||
const wiznet_spi_config_t *spi_config;
|
||||
pio_hw_t *pio;
|
||||
uint8_t pio_func_sel;
|
||||
int8_t pio_offset;
|
||||
int8_t pio_sm;
|
||||
int8_t dma_out;
|
||||
int8_t dma_in;
|
||||
uint8_t spi_header[SPI_HEADER_LEN];
|
||||
uint8_t spi_header_count;
|
||||
} spi_pio_state_t;
|
||||
|
||||
|
||||
|
||||
static spi_pio_state_t spi_pio_state[PICO_WIZNET_SPI_PIO_INSTANCE_COUNT];
|
||||
static spi_pio_state_t *active_state;
|
||||
|
||||
static void wiznet_spi_pio_close(wiznet_spi_handle_t funcs);
|
||||
static wiznet_spi_funcs_t *get_wiznet_spi_pio_impl(void);
|
||||
|
||||
|
||||
static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
|
||||
pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
|
||||
pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
|
||||
pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
|
||||
pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
|
||||
pdst[4] = ((uint8_t)(addr >> 8) & 0xFF);
|
||||
pdst[5] = ((uint8_t)(addr >> 0) & 0xFF);
|
||||
pdst[6] = 0;
|
||||
return 7;
|
||||
}
|
||||
|
||||
// Initialise our gpios
|
||||
static void pio_spi_gpio_setup(spi_pio_state_t *state) {
|
||||
|
||||
gpio_init(state->spi_config->data_io0_pin);
|
||||
gpio_init(state->spi_config->data_io1_pin);
|
||||
gpio_init(state->spi_config->data_io2_pin);
|
||||
gpio_init(state->spi_config->data_io3_pin);
|
||||
gpio_set_dir(state->spi_config->data_io0_pin, GPIO_OUT);
|
||||
gpio_set_dir(state->spi_config->data_io1_pin, GPIO_OUT);
|
||||
gpio_set_dir(state->spi_config->data_io2_pin, GPIO_OUT);
|
||||
gpio_set_dir(state->spi_config->data_io3_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->data_io0_pin, false);
|
||||
gpio_put(state->spi_config->data_io1_pin, false);
|
||||
gpio_put(state->spi_config->data_io2_pin, false);
|
||||
gpio_put(state->spi_config->data_io3_pin, false);
|
||||
|
||||
gpio_init(state->spi_config->cs_pin);
|
||||
gpio_set_dir(state->spi_config->cs_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->cs_pin, true);
|
||||
|
||||
gpio_init(state->spi_config->irq_pin);
|
||||
gpio_set_dir(state->spi_config->irq_pin, GPIO_IN);
|
||||
gpio_set_pulls(state->spi_config->irq_pin, false, false);
|
||||
|
||||
}
|
||||
|
||||
wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config) {
|
||||
|
||||
spi_pio_state_t *state;
|
||||
for (int i = 0; i < count_of(spi_pio_state); i++) {
|
||||
if (!spi_pio_state[i].funcs) {
|
||||
state = &spi_pio_state[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
assert(state);
|
||||
if (!state) {
|
||||
return NULL;
|
||||
}
|
||||
state->spi_config = spi_config;
|
||||
state->funcs = get_wiznet_spi_pio_impl();
|
||||
|
||||
pio_spi_gpio_setup(state);
|
||||
|
||||
pio_hw_t *pios[2] = {pio0, pio1};
|
||||
uint pio_index = PIO_SPI_PREFERRED_PIO;
|
||||
|
||||
if (!pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC)) {
|
||||
pio_index ^= 1;
|
||||
if (!pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC)) {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
state->pio = pios[pio_index];
|
||||
state->dma_in = -1;
|
||||
state->dma_out = -1;
|
||||
|
||||
static_assert(GPIO_FUNC_PIO1 == GPIO_FUNC_PIO0 + 1, "");
|
||||
state->pio_func_sel = GPIO_FUNC_PIO0 + pio_index;
|
||||
state->pio_sm = (int8_t)pio_claim_unused_sm(state->pio, false);
|
||||
if (state->pio_sm < 0) {
|
||||
wiznet_spi_pio_close(&state->funcs);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
state->pio_offset = pio_add_program(state->pio, &PIO_PROGRAM_FUNC);
|
||||
|
||||
uint64_t f_sys = clock_get_hz(clk_sys); // Hz
|
||||
printf("[PIO QSPI CLOCK SPEED : %.2f MHz] (sys=%.2f MHz)\r\n\r\n",
|
||||
(double)f_sys / (2.0 * (state->spi_config->clock_div_major +
|
||||
state->spi_config->clock_div_minor / 256.0)) / 1e6,
|
||||
f_sys / 1e6);
|
||||
|
||||
pio_sm_config sm_config = PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC(state->pio_offset);
|
||||
|
||||
sm_config_set_clkdiv_int_frac(&sm_config, state->spi_config->clock_div_major, state->spi_config->clock_div_minor);
|
||||
hw_write_masked(&pads_bank0_hw->io[state->spi_config->clock_pin],
|
||||
(uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
|
||||
PADS_BANK0_GPIO0_DRIVE_BITS
|
||||
);
|
||||
hw_write_masked(&pads_bank0_hw->io[state->spi_config->clock_pin],
|
||||
(uint)1 << PADS_BANK0_GPIO0_SLEWFAST_LSB,
|
||||
PADS_BANK0_GPIO0_SLEWFAST_BITS
|
||||
);
|
||||
|
||||
sm_config_set_out_pins(&sm_config, state->spi_config->data_io0_pin, 4);
|
||||
sm_config_set_in_pins(&sm_config, state->spi_config->data_io0_pin);
|
||||
sm_config_set_set_pins(&sm_config, state->spi_config->data_io0_pin, 4);
|
||||
sm_config_set_sideset(&sm_config, 1, false, false);
|
||||
sm_config_set_sideset_pins(&sm_config, state->spi_config->clock_pin);
|
||||
sm_config_set_in_shift(&sm_config, false, true, 8);
|
||||
sm_config_set_out_shift(&sm_config, false, true, 8);
|
||||
hw_set_bits(&state->pio->input_sync_bypass,
|
||||
(1u << state->spi_config->data_io0_pin) | (1u << state->spi_config->data_io1_pin) | (1u << state->spi_config->data_io2_pin) | (1u << state->spi_config->data_io3_pin));
|
||||
pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
|
||||
pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->spi_config->clock_pin, 1, true);
|
||||
gpio_set_function(state->spi_config->data_io0_pin, state->pio_func_sel);
|
||||
gpio_set_function(state->spi_config->data_io1_pin, state->pio_func_sel);
|
||||
gpio_set_function(state->spi_config->data_io2_pin, state->pio_func_sel);
|
||||
gpio_set_function(state->spi_config->data_io3_pin, state->pio_func_sel);
|
||||
gpio_set_pulls(state->spi_config->data_io0_pin, false, true);
|
||||
gpio_set_pulls(state->spi_config->data_io1_pin, false, true);
|
||||
gpio_set_pulls(state->spi_config->data_io2_pin, false, true);
|
||||
gpio_set_pulls(state->spi_config->data_io3_pin, false, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io0_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io1_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io2_pin, true);
|
||||
gpio_set_input_hysteresis_enabled(state->spi_config->data_io3_pin, true);
|
||||
|
||||
pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
|
||||
|
||||
state->dma_out = (int8_t)dma_claim_unused_channel(false); // todo: Should be able to use one dma channel?
|
||||
state->dma_in = (int8_t)dma_claim_unused_channel(false);
|
||||
if (state->dma_out < 0 || state->dma_in < 0) {
|
||||
wiznet_spi_pio_close(&state->funcs);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return &state->funcs;
|
||||
|
||||
}
|
||||
|
||||
static void wiznet_spi_pio_close(wiznet_spi_handle_t handle) {
|
||||
|
||||
spi_pio_state_t *state = (spi_pio_state_t *)handle;
|
||||
if (state) {
|
||||
if (state->pio_sm >= 0) {
|
||||
if (state->pio_offset != -1) {
|
||||
pio_remove_program(state->pio, &PIO_PROGRAM_FUNC, state->pio_offset);
|
||||
}
|
||||
|
||||
pio_sm_unclaim(state->pio, state->pio_sm);
|
||||
}
|
||||
if (state->dma_out >= 0) {
|
||||
dma_channel_unclaim(state->dma_out);
|
||||
state->dma_out = -1;
|
||||
}
|
||||
if (state->dma_in >= 0) {
|
||||
dma_channel_unclaim(state->dma_in);
|
||||
state->dma_in = -1;
|
||||
}
|
||||
state->funcs = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void cs_set(spi_pio_state_t *state, bool value) {
|
||||
gpio_put(state->spi_config->cs_pin, value);
|
||||
}
|
||||
|
||||
static __noinline void ns_delay(uint32_t ns) {
|
||||
// cycles = ns * clk_sys_hz / 1,000,000,000
|
||||
uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u);
|
||||
busy_wait_at_least_cycles(cycles);
|
||||
}
|
||||
|
||||
static void wiznet_spi_pio_frame_start(void) {
|
||||
assert(active_state);
|
||||
gpio_set_function(active_state->spi_config->data_io0_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io1_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io2_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->data_io3_pin, active_state->pio_func_sel);
|
||||
gpio_set_function(active_state->spi_config->clock_pin, active_state->pio_func_sel);
|
||||
gpio_pull_down(active_state->spi_config->clock_pin);
|
||||
// Pull CS low
|
||||
cs_set(active_state, false);
|
||||
}
|
||||
|
||||
static void wiznet_spi_pio_frame_end(void) {
|
||||
assert(active_state);
|
||||
// from this point a positive edge will cause an IRQ to be pending
|
||||
cs_set(active_state, true);
|
||||
// we need to wait a bit in case the irq line is incorrectly high
|
||||
#ifdef IRQ_SAMPLE_DELAY_NS
|
||||
ns_delay(IRQ_SAMPLE_DELAY_NS);
|
||||
#endif
|
||||
}
|
||||
|
||||
void wiznet_spi_pio_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, uint16_t rx_length) {
|
||||
uint8_t command_buf[8] = {0,};
|
||||
uint16_t command_len = mk_cmd_buf(command_buf, op_code, AddrSel);
|
||||
uint32_t loop_cnt = 0;
|
||||
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
|
||||
pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + PIO_OFFSET_READ_BITS_END - 1);
|
||||
//pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset + PIO_SPI_OFFSET_WRITE_BITS, active_state->pio_offset + PIO_SPI_OFFSET_READ_BITS_END - 1);
|
||||
pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
|
||||
|
||||
loop_cnt = 2;
|
||||
pio_sm_set_pindirs_with_mask(active_state->pio,
|
||||
active_state->pio_sm,
|
||||
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
|
||||
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
|
||||
|
||||
pio_sm_restart(active_state->pio, active_state->pio_sm);
|
||||
pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
|
||||
|
||||
pio_sm_put(active_state->pio, active_state->pio_sm, command_len * loop_cnt - 1);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_x, 32));
|
||||
|
||||
pio_sm_put(active_state->pio, active_state->pio_sm, rx_length - 1);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_y, 32));
|
||||
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_jmp(active_state->pio_offset));
|
||||
|
||||
dma_channel_abort(active_state->dma_out);
|
||||
dma_channel_abort(active_state->dma_in);
|
||||
|
||||
dma_channel_config out_config = dma_channel_get_default_config(active_state->dma_out);
|
||||
channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&out_config, true);
|
||||
channel_config_set_dreq(&out_config, pio_get_dreq(active_state->pio, active_state->pio_sm, true));
|
||||
dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], command_buf, command_len, true);
|
||||
|
||||
dma_channel_config in_config = dma_channel_get_default_config(active_state->dma_in);
|
||||
channel_config_set_transfer_data_size(&in_config, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&in_config, true);
|
||||
channel_config_set_dreq(&in_config, pio_get_dreq(active_state->pio, active_state->pio_sm, false));
|
||||
channel_config_set_write_increment(&in_config, true);
|
||||
channel_config_set_read_increment(&in_config, false);
|
||||
dma_channel_configure(active_state->dma_in, &in_config, rx, &active_state->pio->rxf[active_state->pio_sm], rx_length, true);
|
||||
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
|
||||
__compiler_memory_barrier();
|
||||
dma_channel_wait_for_finish_blocking(active_state->dma_out);
|
||||
dma_channel_wait_for_finish_blocking(active_state->dma_in);
|
||||
__compiler_memory_barrier();
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
|
||||
}
|
||||
|
||||
void wiznet_spi_pio_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, uint16_t tx_length) {
|
||||
uint8_t command_buf[8] = {0,};
|
||||
uint16_t command_len = mk_cmd_buf(command_buf, op_code, AddrSel);
|
||||
uint32_t loop_cnt = 0;
|
||||
tx_length = tx_length + command_len;
|
||||
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
|
||||
pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
|
||||
pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
|
||||
|
||||
loop_cnt = 2;
|
||||
pio_sm_set_pindirs_with_mask(active_state->pio,
|
||||
active_state->pio_sm,
|
||||
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin),
|
||||
(1u << active_state->spi_config->data_io0_pin) | (1u << active_state->spi_config->data_io1_pin) | (1u << active_state->spi_config->data_io2_pin) | (1u << active_state->spi_config->data_io3_pin));
|
||||
|
||||
pio_sm_restart(active_state->pio, active_state->pio_sm);
|
||||
pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
|
||||
pio_sm_put(active_state->pio, active_state->pio_sm, tx_length * loop_cnt - 1);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_x, 32));
|
||||
pio_sm_put(active_state->pio, active_state->pio_sm, 0);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_y, 32));
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_jmp(active_state->pio_offset));
|
||||
dma_channel_abort(active_state->dma_out);
|
||||
|
||||
|
||||
dma_channel_config out_config = dma_channel_get_default_config(active_state->dma_out);
|
||||
channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&out_config, true);
|
||||
channel_config_set_dreq(&out_config, pio_get_dreq(active_state->pio, active_state->pio_sm, true));
|
||||
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
|
||||
|
||||
dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], command_buf, command_len, true);
|
||||
dma_channel_wait_for_finish_blocking(active_state->dma_out);
|
||||
dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], tx, tx_length - command_len, true);
|
||||
dma_channel_wait_for_finish_blocking(active_state->dma_out);
|
||||
|
||||
const uint32_t fdebug_tx_stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + active_state->pio_sm);
|
||||
active_state->pio->fdebug = fdebug_tx_stall;
|
||||
// pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
|
||||
while (!(active_state->pio->fdebug & fdebug_tx_stall)) {
|
||||
tight_loop_contents(); // todo timeout
|
||||
}
|
||||
|
||||
__compiler_memory_barrier();
|
||||
pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->spi_config->data_io0_pin, 4, false);
|
||||
pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
|
||||
pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
|
||||
}
|
||||
|
||||
|
||||
static void wiznet_spi_pio_set_active(wiznet_spi_handle_t handle) {
|
||||
active_state = (spi_pio_state_t *)handle;
|
||||
}
|
||||
|
||||
static void wiznet_spi_pio_set_inactive(void) {
|
||||
active_state = NULL;
|
||||
}
|
||||
|
||||
static void wizchip_spi_pio_reset(wiznet_spi_handle_t handle) {
|
||||
|
||||
spi_pio_state_t *state = (spi_pio_state_t *)handle;
|
||||
gpio_set_dir(state->spi_config->reset_pin, GPIO_OUT);
|
||||
gpio_put(state->spi_config->reset_pin, 0);
|
||||
sleep_ms(100);
|
||||
gpio_put(state->spi_config->reset_pin, 1);
|
||||
sleep_ms(100);
|
||||
|
||||
}
|
||||
|
||||
static wiznet_spi_funcs_t *get_wiznet_spi_pio_impl(void) {
|
||||
static wiznet_spi_funcs_t funcs = {
|
||||
.close = wiznet_spi_pio_close,
|
||||
.set_active = wiznet_spi_pio_set_active,
|
||||
.set_inactive = wiznet_spi_pio_set_inactive,
|
||||
.frame_start = wiznet_spi_pio_frame_start,
|
||||
.frame_end = wiznet_spi_pio_frame_end,
|
||||
.read_byte = wiznet_spi_pio_read_byte,
|
||||
.write_byte = wiznet_spi_pio_write_byte,
|
||||
.reset = wizchip_spi_pio_reset,
|
||||
};
|
||||
return &funcs;
|
||||
}
|
||||
@@ -0,0 +1,221 @@
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <initializer_list>
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/error.h"
|
||||
#include "hardware/dma.h"
|
||||
#include "hardware/clocks.h"
|
||||
#include "wizchip_spi.h"
|
||||
#include "wizchip_qspi_pio.h"
|
||||
#include "wizchip_qspi_pio.pio.h"
|
||||
|
||||
#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read
|
||||
#define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program)
|
||||
#define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config)
|
||||
#define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits)
|
||||
#define PIO_OFFSET_WRITE_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits_end)
|
||||
#define PIO_OFFSET_READ_BITS_END __CONCAT(PIO_PROGRAM_NAME, _offset_read_bits_end)
|
||||
|
||||
static constexpr uint32_t PADS_DRIVE = PADS_BANK0_GPIO0_DRIVE_VALUE_12MA;
|
||||
static constexpr uint32_t IRQ_DELAY_NS = 100;
|
||||
static constexpr uint32_t QSPI_LOOP_CNT = 2;
|
||||
|
||||
static struct {
|
||||
pio_hw_t *pio;
|
||||
uint8_t pio_func_sel;
|
||||
int8_t pio_offset;
|
||||
int8_t pio_sm;
|
||||
int8_t dma_out;
|
||||
int8_t dma_in;
|
||||
} state;
|
||||
|
||||
static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
|
||||
pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
|
||||
pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
|
||||
pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
|
||||
pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
|
||||
pdst[4] = (uint8_t)(addr >> 8);
|
||||
pdst[5] = (uint8_t)(addr);
|
||||
pdst[6] = 0;
|
||||
return 7;
|
||||
}
|
||||
|
||||
static uint32_t data_pin_mask() {
|
||||
return (1u << PIO_SPI_DATA_IO0_PIN) | (1u << PIO_SPI_DATA_IO1_PIN) |
|
||||
(1u << PIO_SPI_DATA_IO2_PIN) | (1u << PIO_SPI_DATA_IO3_PIN);
|
||||
}
|
||||
|
||||
static __noinline void ns_delay(uint32_t ns) {
|
||||
uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u);
|
||||
busy_wait_at_least_cycles(cycles);
|
||||
}
|
||||
|
||||
void wizchip_pio_init() {
|
||||
for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) {
|
||||
gpio_init(pin);
|
||||
gpio_set_dir(pin, GPIO_OUT);
|
||||
gpio_put(pin, false);
|
||||
}
|
||||
gpio_init(PIN_CS);
|
||||
gpio_set_dir(PIN_CS, GPIO_OUT);
|
||||
gpio_put(PIN_CS, true);
|
||||
gpio_init(PIN_INT);
|
||||
gpio_set_dir(PIN_INT, GPIO_IN);
|
||||
gpio_set_pulls(PIN_INT, false, false);
|
||||
|
||||
pio_hw_t *pios[2] = {pio0, pio1};
|
||||
uint pio_index = 1;
|
||||
if (!pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC)) {
|
||||
pio_index ^= 1;
|
||||
assert(pio_can_add_program(pios[pio_index], &PIO_PROGRAM_FUNC));
|
||||
}
|
||||
|
||||
state.pio = pios[pio_index];
|
||||
state.dma_in = -1;
|
||||
state.dma_out = -1;
|
||||
|
||||
static_assert(GPIO_FUNC_PIO1 == GPIO_FUNC_PIO0 + 1);
|
||||
state.pio_func_sel = GPIO_FUNC_PIO0 + pio_index;
|
||||
state.pio_sm = (int8_t)pio_claim_unused_sm(state.pio, true);
|
||||
state.pio_offset = pio_add_program(state.pio, &PIO_PROGRAM_FUNC);
|
||||
|
||||
pio_sm_config sm_config = PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC(state.pio_offset);
|
||||
sm_config_set_clkdiv_int_frac(&sm_config, WIZNET_SPI_CLKDIV_MAJOR_DEFAULT, WIZNET_SPI_CLKDIV_MINOR_DEFAULT);
|
||||
|
||||
hw_write_masked(&pads_bank0_hw->io[PIO_SPI_SCK_PIN],
|
||||
(uint)PADS_DRIVE << PADS_BANK0_GPIO0_DRIVE_LSB,
|
||||
PADS_BANK0_GPIO0_DRIVE_BITS);
|
||||
hw_write_masked(&pads_bank0_hw->io[PIO_SPI_SCK_PIN],
|
||||
1u << PADS_BANK0_GPIO0_SLEWFAST_LSB,
|
||||
PADS_BANK0_GPIO0_SLEWFAST_BITS);
|
||||
|
||||
sm_config_set_out_pins(&sm_config, PIO_SPI_DATA_IO0_PIN, 4);
|
||||
sm_config_set_in_pins(&sm_config, PIO_SPI_DATA_IO0_PIN);
|
||||
sm_config_set_set_pins(&sm_config, PIO_SPI_DATA_IO0_PIN, 4);
|
||||
sm_config_set_sideset(&sm_config, 1, false, false);
|
||||
sm_config_set_sideset_pins(&sm_config, PIO_SPI_SCK_PIN);
|
||||
sm_config_set_in_shift(&sm_config, false, true, 8);
|
||||
sm_config_set_out_shift(&sm_config, false, true, 8);
|
||||
hw_set_bits(&state.pio->input_sync_bypass, data_pin_mask());
|
||||
pio_sm_set_config(state.pio, state.pio_sm, &sm_config);
|
||||
pio_sm_set_consecutive_pindirs(state.pio, state.pio_sm, PIO_SPI_SCK_PIN, 1, true);
|
||||
|
||||
for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) {
|
||||
gpio_set_function(pin, (gpio_function_t)state.pio_func_sel);
|
||||
gpio_set_pulls(pin, false, true);
|
||||
gpio_set_input_hysteresis_enabled(pin, true);
|
||||
}
|
||||
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_set(pio_pins, 1));
|
||||
|
||||
state.dma_out = (int8_t)dma_claim_unused_channel(true);
|
||||
state.dma_in = (int8_t)dma_claim_unused_channel(true);
|
||||
}
|
||||
|
||||
void wizchip_pio_close() {
|
||||
if (state.pio_sm >= 0) {
|
||||
if (state.pio_offset != -1) {
|
||||
pio_remove_program(state.pio, &PIO_PROGRAM_FUNC, state.pio_offset);
|
||||
}
|
||||
pio_sm_unclaim(state.pio, state.pio_sm);
|
||||
}
|
||||
if (state.dma_out >= 0) dma_channel_unclaim(state.dma_out);
|
||||
if (state.dma_in >= 0) dma_channel_unclaim(state.dma_in);
|
||||
}
|
||||
|
||||
void wizchip_pio_frame_start() {
|
||||
for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN})
|
||||
gpio_set_function(pin, (gpio_function_t)state.pio_func_sel);
|
||||
gpio_set_function(PIO_SPI_SCK_PIN, (gpio_function_t)state.pio_func_sel);
|
||||
gpio_pull_down(PIO_SPI_SCK_PIN);
|
||||
gpio_put(PIN_CS, false);
|
||||
}
|
||||
|
||||
void wizchip_pio_frame_end() {
|
||||
gpio_put(PIN_CS, true);
|
||||
ns_delay(IRQ_DELAY_NS);
|
||||
}
|
||||
|
||||
void wizchip_pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) {
|
||||
uint8_t cmd[8] = {};
|
||||
uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr);
|
||||
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, false);
|
||||
pio_sm_set_wrap(state.pio, state.pio_sm, state.pio_offset, state.pio_offset + PIO_OFFSET_READ_BITS_END - 1);
|
||||
pio_sm_clear_fifos(state.pio, state.pio_sm);
|
||||
pio_sm_set_pindirs_with_mask(state.pio, state.pio_sm, data_pin_mask(), data_pin_mask());
|
||||
pio_sm_restart(state.pio, state.pio_sm);
|
||||
pio_sm_clkdiv_restart(state.pio, state.pio_sm);
|
||||
|
||||
pio_sm_put(state.pio, state.pio_sm, cmd_len * QSPI_LOOP_CNT - 1);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_x, 32));
|
||||
pio_sm_put(state.pio, state.pio_sm, len - 1);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_y, 32));
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_jmp(state.pio_offset));
|
||||
|
||||
dma_channel_abort(state.dma_out);
|
||||
dma_channel_abort(state.dma_in);
|
||||
|
||||
dma_channel_config out_cfg = dma_channel_get_default_config(state.dma_out);
|
||||
channel_config_set_transfer_data_size(&out_cfg, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&out_cfg, true);
|
||||
channel_config_set_dreq(&out_cfg, pio_get_dreq(state.pio, state.pio_sm, true));
|
||||
dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], cmd, cmd_len, true);
|
||||
|
||||
dma_channel_config in_cfg = dma_channel_get_default_config(state.dma_in);
|
||||
channel_config_set_transfer_data_size(&in_cfg, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&in_cfg, true);
|
||||
channel_config_set_dreq(&in_cfg, pio_get_dreq(state.pio, state.pio_sm, false));
|
||||
channel_config_set_write_increment(&in_cfg, true);
|
||||
channel_config_set_read_increment(&in_cfg, false);
|
||||
dma_channel_configure(state.dma_in, &in_cfg, buf, &state.pio->rxf[state.pio_sm], len, true);
|
||||
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, true);
|
||||
__compiler_memory_barrier();
|
||||
dma_channel_wait_for_finish_blocking(state.dma_out);
|
||||
dma_channel_wait_for_finish_blocking(state.dma_in);
|
||||
__compiler_memory_barrier();
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, false);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_mov(pio_pins, pio_null));
|
||||
}
|
||||
|
||||
void wizchip_pio_write(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) {
|
||||
uint8_t cmd[8] = {};
|
||||
uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr);
|
||||
uint16_t total = len + cmd_len;
|
||||
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, false);
|
||||
pio_sm_set_wrap(state.pio, state.pio_sm, state.pio_offset, state.pio_offset + PIO_OFFSET_WRITE_BITS_END - 1);
|
||||
pio_sm_clear_fifos(state.pio, state.pio_sm);
|
||||
pio_sm_set_pindirs_with_mask(state.pio, state.pio_sm, data_pin_mask(), data_pin_mask());
|
||||
pio_sm_restart(state.pio, state.pio_sm);
|
||||
pio_sm_clkdiv_restart(state.pio, state.pio_sm);
|
||||
|
||||
pio_sm_put(state.pio, state.pio_sm, total * QSPI_LOOP_CNT - 1);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_x, 32));
|
||||
pio_sm_put(state.pio, state.pio_sm, 0);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_out(pio_y, 32));
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_jmp(state.pio_offset));
|
||||
|
||||
dma_channel_abort(state.dma_out);
|
||||
|
||||
dma_channel_config out_cfg = dma_channel_get_default_config(state.dma_out);
|
||||
channel_config_set_transfer_data_size(&out_cfg, DMA_SIZE_8);
|
||||
channel_config_set_bswap(&out_cfg, true);
|
||||
channel_config_set_dreq(&out_cfg, pio_get_dreq(state.pio, state.pio_sm, true));
|
||||
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, true);
|
||||
dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], cmd, cmd_len, true);
|
||||
dma_channel_wait_for_finish_blocking(state.dma_out);
|
||||
dma_channel_configure(state.dma_out, &out_cfg, &state.pio->txf[state.pio_sm], buf, len, true);
|
||||
dma_channel_wait_for_finish_blocking(state.dma_out);
|
||||
|
||||
const uint32_t stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + state.pio_sm);
|
||||
state.pio->fdebug = stall;
|
||||
while (!(state.pio->fdebug & stall)) tight_loop_contents();
|
||||
|
||||
__compiler_memory_barrier();
|
||||
pio_sm_set_consecutive_pindirs(state.pio, state.pio_sm, PIO_SPI_DATA_IO0_PIN, 4, false);
|
||||
pio_sm_exec(state.pio, state.pio_sm, pio_encode_mov(pio_pins, pio_null));
|
||||
pio_sm_set_enabled(state.pio, state.pio_sm, false);
|
||||
}
|
||||
@@ -1,43 +1,10 @@
|
||||
#ifndef _WIZNET_SPI_FUNCS_H_
|
||||
#define _WIZNET_SPI_FUNCS_H_
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
|
||||
#include <stdint.h>
|
||||
void wizchip_pio_init();
|
||||
void wizchip_pio_close();
|
||||
|
||||
typedef struct wiznet_spi_funcs** wiznet_spi_handle_t;
|
||||
|
||||
typedef struct wiznet_spi_config {
|
||||
uint16_t clock_div_major;
|
||||
uint8_t clock_div_minor;
|
||||
uint8_t clock_pin;
|
||||
uint8_t data_io0_pin;
|
||||
uint8_t data_io1_pin;
|
||||
uint8_t data_io2_pin;
|
||||
uint8_t data_io3_pin;
|
||||
uint8_t cs_pin;
|
||||
uint8_t reset_pin;
|
||||
uint8_t irq_pin;
|
||||
} wiznet_spi_config_t;
|
||||
|
||||
typedef struct wiznet_spi_funcs {
|
||||
void (*close)(wiznet_spi_handle_t funcs);
|
||||
void (*set_active)(wiznet_spi_handle_t funcs);
|
||||
void (*set_inactive)(void);
|
||||
void (*frame_start)(void);
|
||||
void (*frame_end)(void);
|
||||
void (*read_byte)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
void (*write_byte)(uint8_t opcode, uint16_t addr, uint8_t* pBuf, uint16_t len);
|
||||
void (*read_buffer)(uint8_t *pBuf, uint16_t len);
|
||||
void (*write_buffer)(uint8_t *pBuf, uint16_t len);
|
||||
void (*reset)(wiznet_spi_handle_t funcs);
|
||||
} wiznet_spi_funcs_t;
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef _WIZNET_SPI_PIO_H_
|
||||
#define _WIZNET_SPI_PIO_H_
|
||||
|
||||
#include "wizchip_spi.h"
|
||||
|
||||
wiznet_spi_handle_t wiznet_spi_pio_open(const wiznet_spi_config_t *spi_config);
|
||||
|
||||
#endif
|
||||
void wizchip_pio_frame_start();
|
||||
void wizchip_pio_frame_end();
|
||||
void wizchip_pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len);
|
||||
void wizchip_pio_write(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len);
|
||||
|
||||
@@ -1,72 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "wizchip_conf.h"
|
||||
#include "wizchip_spi.h"
|
||||
#include "wizchip_qspi_pio.h"
|
||||
|
||||
static critical_section_t g_wizchip_cri_sec;
|
||||
|
||||
wiznet_spi_config_t g_spi_config = {
|
||||
.clock_div_major = WIZNET_SPI_CLKDIV_MAJOR_DEFAULT,
|
||||
.clock_div_minor = WIZNET_SPI_CLKDIV_MINOR_DEFAULT,
|
||||
.clock_pin = PIO_SPI_SCK_PIN,
|
||||
.data_io0_pin = PIO_SPI_DATA_IO0_PIN,
|
||||
.data_io1_pin = PIO_SPI_DATA_IO1_PIN,
|
||||
.data_io2_pin = PIO_SPI_DATA_IO2_PIN,
|
||||
.data_io3_pin = PIO_SPI_DATA_IO3_PIN,
|
||||
.cs_pin = PIN_CS,
|
||||
.reset_pin = PIN_RST,
|
||||
.irq_pin = PIN_INT,
|
||||
};
|
||||
|
||||
wiznet_spi_handle_t spi_handle;
|
||||
|
||||
void wizchip_reset() {
|
||||
gpio_init(PIN_RST);
|
||||
gpio_set_dir(PIN_RST, GPIO_OUT);
|
||||
gpio_put(PIN_RST, 0);
|
||||
sleep_ms(100);
|
||||
gpio_put(PIN_RST, 1);
|
||||
sleep_ms(100);
|
||||
}
|
||||
|
||||
static void wizchip_critical_section_lock(void) {
|
||||
critical_section_enter_blocking(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
static void wizchip_critical_section_unlock(void) {
|
||||
critical_section_exit(&g_wizchip_cri_sec);
|
||||
}
|
||||
|
||||
void wizchip_spi_initialize(void) {
|
||||
spi_handle = wiznet_spi_pio_open(&g_spi_config);
|
||||
(*spi_handle)->set_active(spi_handle);
|
||||
}
|
||||
|
||||
void wizchip_cris_initialize(void) {
|
||||
critical_section_init(&g_wizchip_cri_sec);
|
||||
reg_wizchip_cris_cbfunc(wizchip_critical_section_lock, wizchip_critical_section_unlock);
|
||||
}
|
||||
|
||||
void wizchip_initialize(void) {
|
||||
(*spi_handle)->frame_end();
|
||||
reg_wizchip_qspi_cbfunc((*spi_handle)->read_byte, (*spi_handle)->write_byte);
|
||||
reg_wizchip_cs_cbfunc((*spi_handle)->frame_start, (*spi_handle)->frame_end);
|
||||
|
||||
uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}};
|
||||
ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize);
|
||||
}
|
||||
|
||||
void wizchip_check(void) {
|
||||
if (getCIDR() != 0x6300) {
|
||||
printf("W6300 ACCESS ERR: CIDR = 0x%04x\n", getCIDR());
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
void network_initialize(wiz_NetInfo net_info) {
|
||||
uint8_t syslock = SYS_NET_LOCK;
|
||||
ctlwizchip(CW_SYS_UNLOCK, &syslock);
|
||||
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#include <cstdio>
|
||||
#include "pico/stdlib.h"
|
||||
#include "pico/critical_section.h"
|
||||
#include "wizchip_conf.h"
|
||||
#include "wizchip_spi.h"
|
||||
#include "wizchip_qspi_pio.h"
|
||||
|
||||
static critical_section_t g_cris_sec;
|
||||
|
||||
void wizchip_cris_enter() {
|
||||
critical_section_enter_blocking(&g_cris_sec);
|
||||
}
|
||||
|
||||
void wizchip_cris_exit() {
|
||||
critical_section_exit(&g_cris_sec);
|
||||
}
|
||||
|
||||
void wizchip_reset() {
|
||||
gpio_init(PIN_RST);
|
||||
gpio_set_dir(PIN_RST, GPIO_OUT);
|
||||
gpio_put(PIN_RST, 0);
|
||||
sleep_ms(100);
|
||||
gpio_put(PIN_RST, 1);
|
||||
sleep_ms(100);
|
||||
}
|
||||
|
||||
void wizchip_spi_initialize() {
|
||||
wizchip_pio_init();
|
||||
}
|
||||
|
||||
void wizchip_cris_initialize() {
|
||||
critical_section_init(&g_cris_sec);
|
||||
}
|
||||
|
||||
void wizchip_initialize() {
|
||||
wizchip_pio_frame_end();
|
||||
uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}};
|
||||
ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize);
|
||||
}
|
||||
|
||||
void wizchip_check() {
|
||||
if (getCIDR() != 0x6300) {
|
||||
printf("W6300 ACCESS ERR: CIDR = 0x%04x\n", getCIDR());
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
void network_initialize(wiz_NetInfo net_info) {
|
||||
uint8_t syslock = SYS_NET_LOCK;
|
||||
ctlwizchip(CW_SYS_UNLOCK, &syslock);
|
||||
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
|
||||
}
|
||||
+18
-20
@@ -1,24 +1,22 @@
|
||||
#ifndef _WIZCHIP_SPI_H_
|
||||
#define _WIZCHIP_SPI_H_
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include "wizchip_conf.h"
|
||||
|
||||
#define USE_PIO
|
||||
#define WIZNET_SPI_CLKDIV_MAJOR_DEFAULT 2
|
||||
#define WIZNET_SPI_CLKDIV_MINOR_DEFAULT 0
|
||||
constexpr uint8_t PIN_INT = 15;
|
||||
constexpr uint8_t PIN_CS = 16;
|
||||
constexpr uint8_t PIO_SPI_SCK_PIN = 17;
|
||||
constexpr uint8_t PIO_SPI_DATA_IO0_PIN = 18;
|
||||
constexpr uint8_t PIO_SPI_DATA_IO1_PIN = 19;
|
||||
constexpr uint8_t PIO_SPI_DATA_IO2_PIN = 20;
|
||||
constexpr uint8_t PIO_SPI_DATA_IO3_PIN = 21;
|
||||
constexpr uint8_t PIN_RST = 22;
|
||||
|
||||
#define PIN_INT 15
|
||||
#define PIN_CS 16
|
||||
#define PIO_SPI_SCK_PIN 17
|
||||
#define PIO_SPI_DATA_IO0_PIN 18
|
||||
#define PIO_SPI_DATA_IO1_PIN 19
|
||||
#define PIO_SPI_DATA_IO2_PIN 20
|
||||
#define PIO_SPI_DATA_IO3_PIN 21
|
||||
#define PIN_RST 22
|
||||
constexpr uint16_t WIZNET_SPI_CLKDIV_MAJOR_DEFAULT = 2;
|
||||
constexpr uint8_t WIZNET_SPI_CLKDIV_MINOR_DEFAULT = 0;
|
||||
|
||||
void wizchip_spi_initialize(void);
|
||||
void wizchip_cris_initialize(void);
|
||||
void wizchip_reset(void);
|
||||
void wizchip_initialize(void);
|
||||
void wizchip_check(void);
|
||||
void wizchip_spi_initialize();
|
||||
void wizchip_cris_initialize();
|
||||
void wizchip_reset();
|
||||
void wizchip_initialize();
|
||||
void wizchip_check();
|
||||
void network_initialize(wiz_NetInfo net_info);
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user