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C++-ize W6300 driver: remove vtable indirection, constexpr pins, pragma once

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This commit is contained in:
Ian Gulliver
2026-04-04 16:22:37 +09:00
parent dec8d0c68d
commit 92e00476da
16 changed files with 967 additions and 1655 deletions
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243
w6300/w6300.h
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@@ -1,153 +1,129 @@
#ifndef _W6300_H_
#define _W6300_H_
#include <stdint.h>
#pragma once
#include <cstdint>
#include "wizchip_conf.h"
constexpr uint8_t W6300_SPI_READ = (0x00 << 5);
constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5);
#ifdef __cplusplus
extern "C" {
#endif
constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00;
constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; }
constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; }
constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; }
#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8))
#define _W6300_SPI_READ_ (0x00 << 5) ///< SPI interface Read operation in Control Phase
#define _W6300_SPI_WRITE_ (0x01 << 5) ///< SPI interface Write operation in Control Phase
#define WIZCHIP_CREG_BLOCK (0x00 ) ///< Common register block
#define WIZCHIP_SREG_BLOCK(N) ((1+4*N)) ///< SOCKETn register block
#define WIZCHIP_TXBUF_BLOCK(N) ((2+4*N)) ///< SOCKETn Tx buffer address block
#define WIZCHIP_RXBUF_BLOCK(N) ((3+4*N)) ///< SOCKETn Rx buffer address block
#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) ///< Increase offset address
#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
#define _W6300_IO_BASE_ _WIZCHIP_IO_BASE_
#elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
#define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) ///< Indirect High Address Register
#define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) ///< Indirect Low Address Register
#define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) ///< Block Select Register
#define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) ///< Indirect Data Register
#define _W6300_IO_BASE_ 0x00000000
#define _W6100_IO_BASE_ 0x00000000
#endif
#define _CIDR_ (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTL_ (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_CREG_BLOCK)
#define _VER_ (_W6300_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYSR_ (_W6300_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYCR0_ (_W6300_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)
#define _CIDR_ ((0x0000 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTL_ ((0x0004 << 8) + WIZCHIP_CREG_BLOCK)
#define _VER_ ((0x0002 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYSR_ ((0x2000 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYCR0_ ((0x2004 << 8) + WIZCHIP_CREG_BLOCK)
#define _SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1))
#define _TCNTR_ (_W6300_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)
#define _TCNTRCLR_ (_W6300_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)
#define _IR_ (_W6300_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIR_ (_W6300_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIR_ (_W6300_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)
#define _IMR_ (_W6300_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)
#define _IRCLR_ (_W6300_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIMR_ (_W6300_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIMR_ (_W6300_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIRCLR_ (_W6300_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLPSR_ (_W6300_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLCR_ (_W6300_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYSR_ (_W6300_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYRAR_ (_W6300_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIR_ (_W6300_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDOR_ (_W6300_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYACR_ (_W6300_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIVR_ (_W6300_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYCR0_ (_W6300_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)
#define _TCNTR_ ((0x2016 << 8) + WIZCHIP_CREG_BLOCK)
#define _TCNTRCLR_ ((0x2020 << 8) + WIZCHIP_CREG_BLOCK)
#define _IR_ ((0x2100 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIR_ ((0x2101 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIR_ ((0x2102 << 8) + WIZCHIP_CREG_BLOCK)
#define _IMR_ ((0x2104 << 8) + WIZCHIP_CREG_BLOCK)
#define _IRCLR_ ((0x2108 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIMR_ ((0x2114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIMR_ ((0x2124 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLIRCLR_ ((0x2128 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLPSR_ ((0x212C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLCR_ ((0x2130 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYSR_ ((0x3000 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYRAR_ ((0x3008 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIR_ ((0x300C << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDOR_ ((0x3010 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYACR_ ((0x3014 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYDIVR_ ((0x3018 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYCR0_ ((0x301C << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1)
#define _NET4MR_ (_W6300_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)
#define _NET6MR_ (_W6300_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR_ (_W6300_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR2_ (_W6300_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)
#define _PTMR_ (_W6300_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMNR_ (_W6300_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHAR_ (_W6300_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)
#define _PSIDR_ (_W6300_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMRUR_ (_W6300_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SHAR_ (_W6300_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)
#define _GAR_ (_W6300_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)
#define _NET4MR_ ((0x4000 << 8) + WIZCHIP_CREG_BLOCK)
#define _NET6MR_ ((0x4004 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR_ ((0x4008 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETMR2_ ((0x4009 << 8) + WIZCHIP_CREG_BLOCK)
#define _PTMR_ ((0x4100 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMNR_ ((0x4104 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHAR_ ((0x4108 << 8) + WIZCHIP_CREG_BLOCK)
#define _PSIDR_ ((0x4110 << 8) + WIZCHIP_CREG_BLOCK)
#define _PMRUR_ ((0x4114 << 8) + WIZCHIP_CREG_BLOCK)
#define _SHAR_ ((0x4120 << 8) + WIZCHIP_CREG_BLOCK)
#define _GAR_ ((0x4130 << 8) + WIZCHIP_CREG_BLOCK)
#define _GA4R_ (_GAR_)
#define _SUBR_ (_W6300_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUBR_ ((0x4134 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUB4R_ (_SUBR_)
#define _SIPR_ (_W6300_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIPR_ ((0x4138 << 8) + WIZCHIP_CREG_BLOCK)
#define _SIP4R_ (_SIPR_)
#define _LLAR_ (_W6300_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)
#define _GUAR_ (_W6300_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUB6R_ (_W6300_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)
#define _GA6R_ (_W6300_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIP6R_ (_W6300_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIPR_ (_W6300_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)
#define _LLAR_ ((0x4140 << 8) + WIZCHIP_CREG_BLOCK)
#define _GUAR_ ((0x4150 << 8) + WIZCHIP_CREG_BLOCK)
#define _SUB6R_ ((0x4160 << 8) + WIZCHIP_CREG_BLOCK)
#define _GA6R_ ((0x4170 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIP6R_ ((0x4180 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIPR_ ((0x418C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDIP4R_ (_SLDIPR_)
#define _SLDHAR_ (_W6300_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGIDR_ (_W6300_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGSEQR_ (_W6300_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)
#define _UIPR_ (_W6300_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLDHAR_ ((0x4190 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGIDR_ ((0x4198 << 8) + WIZCHIP_CREG_BLOCK)
#define _PINGSEQR_ ((0x419C << 8) + WIZCHIP_CREG_BLOCK)
#define _UIPR_ ((0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
#define _UIP4R_ (_UIPR_)
#define _UPORTR_ (_W6300_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORTR_ ((0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORT4R_ (_UPORTR_)
#define _UIP6R_ (_W6300_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORT6R_ (_W6300_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
#define _INTPTMR_ (_W6300_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLR_ (_W6300_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
#define _PFR_ (_W6300_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
#define _VLTR_ (_W6300_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLTR_ (_W6300_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)
#define _PAR_ (_W6300_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
#define _ICMP6BLKR_ (_W6300_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
#define _CHPLCKR_ (_W6300_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETLCKR_ (_W6300_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYLCKR_ (_W6300_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTR_ (_W6300_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)
#define _RCR_ (_W6300_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRTR_ (_W6300_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRCR_ (_W6300_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLHOPR_ (_W6300_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)
#define _UIP6R_ ((0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
#define _UPORT6R_ ((0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
#define _INTPTMR_ ((0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLR_ ((0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
#define _PFR_ ((0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
#define _VLTR_ ((0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
#define _PLTR_ ((0x41DC << 8) + WIZCHIP_CREG_BLOCK)
#define _PAR_ ((0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
#define _ICMP6BLKR_ ((0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
#define _CHPLCKR_ ((0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
#define _NETLCKR_ ((0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
#define _PHYLCKR_ ((0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
#define _RTR_ ((0x4200 << 8) + WIZCHIP_CREG_BLOCK)
#define _RCR_ ((0x4204 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRTR_ ((0x4208 << 8) + WIZCHIP_CREG_BLOCK)
#define _SLRCR_ ((0x420C << 8) + WIZCHIP_CREG_BLOCK)
#define _SLHOPR_ ((0x420F << 8) + WIZCHIP_CREG_BLOCK)
#define _Sn_MR_(N) (_W6300_IO_BASE_ + (0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PSR_(N) (_W6300_IO_BASE_ + (0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_CR_(N) (_W6300_IO_BASE_ + (0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IR_(N) (_W6300_IO_BASE_ + (0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IMR_(N) (_W6300_IO_BASE_ + (0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IRCLR_(N) (_W6300_IO_BASE_ + (0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MR_(N) ((0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PSR_(N) ((0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_CR_(N) ((0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IR_(N) ((0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IMR_(N) ((0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_IRCLR_(N) ((0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_SR_(N) (_W6300_IO_BASE_ + (0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_ESR_(N) (_W6300_IO_BASE_ + (0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PNR_(N) (_W6300_IO_BASE_ + (0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_SR_(N) ((0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_ESR_(N) ((0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PNR_(N) ((0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_NHR_(N) (_Sn_PNR_(N))
#define _Sn_TOSR_(N) (_W6300_IO_BASE_ + (0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TTLR_(N) (_W6300_IO_BASE_ + (0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TOSR_(N) ((0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TTLR_(N) ((0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_HOPR_(N) (_Sn_TTLR_(N))
#define _Sn_FRGR_(N) (_W6300_IO_BASE_ + (0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MSSR_(N) (_W6300_IO_BASE_ + (0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PORTR_(N) (_W6300_IO_BASE_ + (0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DHAR_(N) (_W6300_IO_BASE_ + (0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIPR_(N) (_W6300_IO_BASE_ + (0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_FRGR_(N) ((0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MSSR_(N) ((0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_PORTR_(N) ((0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DHAR_(N) ((0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIPR_(N) ((0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIP4R_(N) (_Sn_DIPR_(N))
#define _Sn_DIP6R_(N) (_W6300_IO_BASE_ + (0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DPORTR_(N) (_W6300_IO_BASE_ + (0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MR2_(N) (_W6300_IO_BASE_ + (0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RTR_(N) (_W6300_IO_BASE_ + (0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RCR_(N) (_W6300_IO_BASE_ + (0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_KPALVTR_(N) (_W6300_IO_BASE_ + (0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_BSR_(N) (_W6300_IO_BASE_ + (0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_FSR_(N) (_W6300_IO_BASE_ + (0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_RD_(N) (_W6300_IO_BASE_ + (0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_WR_(N) (_W6300_IO_BASE_ + (0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_BSR_(N) (_W6300_IO_BASE_ + (0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RSR_(N) (_W6300_IO_BASE_ + (0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RD_(N) (_W6300_IO_BASE_ + (0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_WR_(N) (_W6300_IO_BASE_ + (0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DIP6R_(N) ((0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_DPORTR_(N) ((0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_MR2_(N) ((0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RTR_(N) ((0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RCR_(N) ((0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_KPALVTR_(N) ((0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_BSR_(N) ((0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_FSR_(N) ((0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_RD_(N) ((0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_TX_WR_(N) ((0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_BSR_(N) ((0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RSR_(N) ((0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_RD_(N) ((0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
#define _Sn_RX_WR_(N) ((0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
#define SYSR_CHPL (1 << 7)
#define SYSR_NETL (1 << 6)
@@ -327,8 +303,10 @@ extern "C" {
#define BMSR_EXT_CAPA (1<<0)
#define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
#define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
void wizchip_cris_enter();
void wizchip_cris_exit();
#define WIZCHIP_CRITICAL_ENTER() wizchip_cris_enter()
#define WIZCHIP_CRITICAL_EXIT() wizchip_cris_exit()
uint8_t WIZCHIP_READ(uint32_t AddrSel);
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
@@ -922,8 +900,3 @@ void wiz_mdio_write(uint8_t phyregaddr, uint16_t var);
uint16_t wiz_mdio_read(uint8_t phyregaddr);
#endif
#ifdef __cplusplus
}
#endif
#endif //_W6300_H_