From 732ea4250d22a67f68e4775c823bc78c836e360b Mon Sep 17 00:00:00 2001 From: Ian Gulliver Date: Sun, 5 Apr 2026 09:09:10 +0900 Subject: [PATCH] Rename all internal wiz/WIZCHIP symbols to clean names --- w6300/qspi.pio | 2 +- w6300/w6300.cpp | 724 ++++++++++++++++++++++++------------------------ 2 files changed, 362 insertions(+), 364 deletions(-) diff --git a/w6300/qspi.pio b/w6300/qspi.pio index 1031390..fac05ee 100644 --- a/w6300/qspi.pio +++ b/w6300/qspi.pio @@ -1,4 +1,4 @@ -.program wizchip_pio_spi_quad_write_read +.program qspi .side_set 1 write_bits: diff --git a/w6300/w6300.cpp b/w6300/w6300.cpp index 274f482..14776ef 100644 --- a/w6300/w6300.cpp +++ b/w6300/w6300.cpp @@ -12,7 +12,7 @@ namespace w6300 { namespace { -#define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read +#define PIO_PROGRAM_NAME qspi #define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program) #define PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(PIO_PROGRAM_NAME, _program_get_default_config) #define PIO_OFFSET_WRITE_BITS __CONCAT(PIO_PROGRAM_NAME, _offset_write_bits) @@ -28,8 +28,8 @@ constexpr uint8_t PIO_SPI_DATA_IO2_PIN = 20; constexpr uint8_t PIO_SPI_DATA_IO3_PIN = 21; constexpr uint8_t PIN_RST = 22; -constexpr uint16_t WIZNET_SPI_CLKDIV_MAJOR_DEFAULT = 2; -constexpr uint8_t WIZNET_SPI_CLKDIV_MINOR_DEFAULT = 0; +constexpr uint16_t SPI_CLKDIV_MAJOR = 2; +constexpr uint8_t SPI_CLKDIV_MINOR = 0; constexpr uint32_t PADS_DRIVE = PADS_BANK0_GPIO0_DRIVE_VALUE_12MA; constexpr uint32_t IRQ_DELAY_NS = 100; @@ -65,7 +65,7 @@ __noinline void ns_delay(uint32_t ns) { busy_wait_at_least_cycles(cycles); } -void wizchip_pio_init() { +void pio_init() { for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) { gpio_init(pin); gpio_set_dir(pin, GPIO_OUT); @@ -95,7 +95,7 @@ void wizchip_pio_init() { state.pio_offset = pio_add_program(state.pio, &PIO_PROGRAM_FUNC); pio_sm_config sm_config = PIO_PROGRAM_GET_DEFAULT_CONFIG_FUNC(state.pio_offset); - sm_config_set_clkdiv_int_frac(&sm_config, WIZNET_SPI_CLKDIV_MAJOR_DEFAULT, WIZNET_SPI_CLKDIV_MINOR_DEFAULT); + sm_config_set_clkdiv_int_frac(&sm_config, SPI_CLKDIV_MAJOR, SPI_CLKDIV_MINOR); hw_write_masked(&pads_bank0_hw->io[PIO_SPI_SCK_PIN], (uint)PADS_DRIVE << PADS_BANK0_GPIO0_DRIVE_LSB, @@ -128,7 +128,7 @@ void wizchip_pio_init() { } -void wizchip_pio_frame_start() { +void pio_frame_start() { for (auto pin : {PIO_SPI_DATA_IO0_PIN, PIO_SPI_DATA_IO1_PIN, PIO_SPI_DATA_IO2_PIN, PIO_SPI_DATA_IO3_PIN}) gpio_set_function(pin, (gpio_function_t)state.pio_func_sel); gpio_set_function(PIO_SPI_SCK_PIN, (gpio_function_t)state.pio_func_sel); @@ -136,12 +136,12 @@ void wizchip_pio_frame_start() { gpio_put(PIN_CS, false); } -void wizchip_pio_frame_end() { +void pio_frame_end() { gpio_put(PIN_CS, true); ns_delay(IRQ_DELAY_NS); } -void wizchip_pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) { +void pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) { uint8_t cmd[8] = {}; uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr); @@ -184,7 +184,7 @@ void wizchip_pio_read(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) pio_sm_exec(state.pio, state.pio_sm, pio_encode_mov(pio_pins, pio_null)); } -void wizchip_pio_write(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) { +void pio_write(uint8_t opcode, uint16_t addr, uint8_t* buf, uint16_t len) { uint8_t cmd[8] = {}; uint16_t cmd_len = mk_cmd_buf(cmd, opcode, addr); uint16_t total = len + cmd_len; @@ -280,123 +280,123 @@ enum sockint_kind { SIK_CONNECTED = 1, SIK_DISCONNECTED = 2, SIK_RECEIVED = 4, S constexpr uint8_t TCPSOCK_MODE = static_cast(tcp_sock_info::mode); -constexpr uint8_t W6300_SPI_READ = (0x00 << 5); -constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5); +constexpr uint8_t SPI_READ = (0x00 << 5); +constexpr uint8_t SPI_WRITE = (0x01 << 5); -constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00; -constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; } -constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; } -constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; } +constexpr uint32_t CREG_BLOCK = 0x00; +constexpr uint32_t SREG_BLOCK(uint8_t n) { return 1 + 4 * n; } +constexpr uint32_t TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; } +constexpr uint32_t RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; } -constexpr uint32_t WIZCHIP_OFFSET_INC(uint32_t addr, uint32_t n) { return addr + (n << 8); } +constexpr uint32_t offset_inc(uint32_t addr, uint32_t n) { return addr + (n << 8); } -constexpr uint32_t _CIDR_ = (0x0000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RTL_ = (0x0004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _VER_ = (0x0002 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYSR_ = (0x2000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYCR0_ = (0x2004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYCR1_ = WIZCHIP_OFFSET_INC(_SYCR0_, 1); -constexpr uint32_t _TCNTR_ = (0x2016 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _TCNTRCLR_ = (0x2020 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IR_ = (0x2100 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SIR_ = (0x2101 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIR_ = (0x2102 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IMR_ = (0x2104 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IRCLR_ = (0x2108 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SIMR_ = (0x2114 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIMR_ = (0x2124 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIRCLR_ = (0x2128 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLPSR_ = (0x212C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLCR_ = (0x2130 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYSR_ = (0x3000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYRAR_ = (0x3008 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDIR_ = (0x300C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDOR_ = (0x3010 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYACR_ = (0x3014 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDIVR_ = (0x3018 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYCR0_ = (0x301C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYCR1_ = WIZCHIP_OFFSET_INC(_PHYCR0_, 1); -constexpr uint32_t _NET4MR_ = (0x4000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NET6MR_ = (0x4004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETMR_ = (0x4008 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETMR2_ = (0x4009 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PTMR_ = (0x4100 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PMNR_ = (0x4104 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHAR_ = (0x4108 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PSIDR_ = (0x4110 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PMRUR_ = (0x4114 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SHAR_ = (0x4120 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GAR_ = (0x4130 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _CIDR_ = (0x0000 << 8) + CREG_BLOCK; +constexpr uint32_t _RTL_ = (0x0004 << 8) + CREG_BLOCK; +constexpr uint32_t _VER_ = (0x0002 << 8) + CREG_BLOCK; +constexpr uint32_t _SYSR_ = (0x2000 << 8) + CREG_BLOCK; +constexpr uint32_t _SYCR0_ = (0x2004 << 8) + CREG_BLOCK; +constexpr uint32_t _SYCR1_ = offset_inc(_SYCR0_, 1); +constexpr uint32_t _TCNTR_ = (0x2016 << 8) + CREG_BLOCK; +constexpr uint32_t _TCNTRCLR_ = (0x2020 << 8) + CREG_BLOCK; +constexpr uint32_t _IR_ = (0x2100 << 8) + CREG_BLOCK; +constexpr uint32_t _SIR_ = (0x2101 << 8) + CREG_BLOCK; +constexpr uint32_t _SLIR_ = (0x2102 << 8) + CREG_BLOCK; +constexpr uint32_t _IMR_ = (0x2104 << 8) + CREG_BLOCK; +constexpr uint32_t _IRCLR_ = (0x2108 << 8) + CREG_BLOCK; +constexpr uint32_t _SIMR_ = (0x2114 << 8) + CREG_BLOCK; +constexpr uint32_t _SLIMR_ = (0x2124 << 8) + CREG_BLOCK; +constexpr uint32_t _SLIRCLR_ = (0x2128 << 8) + CREG_BLOCK; +constexpr uint32_t _SLPSR_ = (0x212C << 8) + CREG_BLOCK; +constexpr uint32_t _SLCR_ = (0x2130 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYSR_ = (0x3000 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYRAR_ = (0x3008 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYDIR_ = (0x300C << 8) + CREG_BLOCK; +constexpr uint32_t _PHYDOR_ = (0x3010 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYACR_ = (0x3014 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYDIVR_ = (0x3018 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYCR0_ = (0x301C << 8) + CREG_BLOCK; +constexpr uint32_t _PHYCR1_ = offset_inc(_PHYCR0_, 1); +constexpr uint32_t _NET4MR_ = (0x4000 << 8) + CREG_BLOCK; +constexpr uint32_t _NET6MR_ = (0x4004 << 8) + CREG_BLOCK; +constexpr uint32_t _NETMR_ = (0x4008 << 8) + CREG_BLOCK; +constexpr uint32_t _NETMR2_ = (0x4009 << 8) + CREG_BLOCK; +constexpr uint32_t _PTMR_ = (0x4100 << 8) + CREG_BLOCK; +constexpr uint32_t _PMNR_ = (0x4104 << 8) + CREG_BLOCK; +constexpr uint32_t _PHAR_ = (0x4108 << 8) + CREG_BLOCK; +constexpr uint32_t _PSIDR_ = (0x4110 << 8) + CREG_BLOCK; +constexpr uint32_t _PMRUR_ = (0x4114 << 8) + CREG_BLOCK; +constexpr uint32_t _SHAR_ = (0x4120 << 8) + CREG_BLOCK; +constexpr uint32_t _GAR_ = (0x4130 << 8) + CREG_BLOCK; constexpr uint32_t _GA4R_ = _GAR_; -constexpr uint32_t _SUBR_ = (0x4134 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SUBR_ = (0x4134 << 8) + CREG_BLOCK; constexpr uint32_t _SUB4R_ = _SUBR_; -constexpr uint32_t _SIPR_ = (0x4138 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SIPR_ = (0x4138 << 8) + CREG_BLOCK; constexpr uint32_t _SIP4R_ = _SIPR_; -constexpr uint32_t _LLAR_ = (0x4140 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GUAR_ = (0x4150 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SUB6R_ = (0x4160 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GA6R_ = (0x4170 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLDIP6R_ = (0x4180 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLDIPR_ = (0x418C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _LLAR_ = (0x4140 << 8) + CREG_BLOCK; +constexpr uint32_t _GUAR_ = (0x4150 << 8) + CREG_BLOCK; +constexpr uint32_t _SUB6R_ = (0x4160 << 8) + CREG_BLOCK; +constexpr uint32_t _GA6R_ = (0x4170 << 8) + CREG_BLOCK; +constexpr uint32_t _SLDIP6R_ = (0x4180 << 8) + CREG_BLOCK; +constexpr uint32_t _SLDIPR_ = (0x418C << 8) + CREG_BLOCK; constexpr uint32_t _SLDIP4R_ = _SLDIPR_; -constexpr uint32_t _SLDHAR_ = (0x4190 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PINGIDR_ = (0x4198 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PINGSEQR_ = (0x419C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UIPR_ = (0x41A0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLDHAR_ = (0x4190 << 8) + CREG_BLOCK; +constexpr uint32_t _PINGIDR_ = (0x4198 << 8) + CREG_BLOCK; +constexpr uint32_t _PINGSEQR_ = (0x419C << 8) + CREG_BLOCK; +constexpr uint32_t _UIPR_ = (0x41A0 << 8) + CREG_BLOCK; constexpr uint32_t _UIP4R_ = _UIPR_; -constexpr uint32_t _UPORTR_ = (0x41A4 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UPORTR_ = (0x41A4 << 8) + CREG_BLOCK; constexpr uint32_t _UPORT4R_ = _UPORTR_; -constexpr uint32_t _UIP6R_ = (0x41B0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UPORT6R_ = (0x41C0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _INTPTMR_ = (0x41C5 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PLR_ = (0x41D0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PFR_ = (0x41D4 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _VLTR_ = (0x41D8 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PLTR_ = (0x41DC << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PAR_ = (0x41E0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _CHPLCKR_ = (0x41F4 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETLCKR_ = (0x41F5 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYLCKR_ = (0x41F6 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RTR_ = (0x4200 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RCR_ = (0x4204 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLRTR_ = (0x4208 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLRCR_ = (0x420C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLHOPR_ = (0x420F << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UIP6R_ = (0x41B0 << 8) + CREG_BLOCK; +constexpr uint32_t _UPORT6R_ = (0x41C0 << 8) + CREG_BLOCK; +constexpr uint32_t _INTPTMR_ = (0x41C5 << 8) + CREG_BLOCK; +constexpr uint32_t _PLR_ = (0x41D0 << 8) + CREG_BLOCK; +constexpr uint32_t _PFR_ = (0x41D4 << 8) + CREG_BLOCK; +constexpr uint32_t _VLTR_ = (0x41D8 << 8) + CREG_BLOCK; +constexpr uint32_t _PLTR_ = (0x41DC << 8) + CREG_BLOCK; +constexpr uint32_t _PAR_ = (0x41E0 << 8) + CREG_BLOCK; +constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + CREG_BLOCK; +constexpr uint32_t _CHPLCKR_ = (0x41F4 << 8) + CREG_BLOCK; +constexpr uint32_t _NETLCKR_ = (0x41F5 << 8) + CREG_BLOCK; +constexpr uint32_t _PHYLCKR_ = (0x41F6 << 8) + CREG_BLOCK; +constexpr uint32_t _RTR_ = (0x4200 << 8) + CREG_BLOCK; +constexpr uint32_t _RCR_ = (0x4204 << 8) + CREG_BLOCK; +constexpr uint32_t _SLRTR_ = (0x4208 << 8) + CREG_BLOCK; +constexpr uint32_t _SLRCR_ = (0x420C << 8) + CREG_BLOCK; +constexpr uint32_t _SLHOPR_ = (0x420F << 8) + CREG_BLOCK; -constexpr uint32_t _Sn_MR_(uint8_t n) { return (0x0000 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PSR_(uint8_t n) { return (0x0004 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_CR_(uint8_t n) { return (0x0010 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IR_(uint8_t n) { return (0x0020 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IMR_(uint8_t n) { return (0x0024 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IRCLR_(uint8_t n) { return (0x0028 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_SR_(uint8_t n) { return (0x0030 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_ESR_(uint8_t n) { return (0x0031 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PNR_(uint8_t n) { return (0x0100 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_MR_(uint8_t n) { return (0x0000 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_PSR_(uint8_t n) { return (0x0004 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_CR_(uint8_t n) { return (0x0010 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_IR_(uint8_t n) { return (0x0020 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_IMR_(uint8_t n) { return (0x0024 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_IRCLR_(uint8_t n) { return (0x0028 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_SR_(uint8_t n) { return (0x0030 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_ESR_(uint8_t n) { return (0x0031 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_PNR_(uint8_t n) { return (0x0100 << 8) + SREG_BLOCK(n); } constexpr uint32_t _Sn_NHR_(uint8_t n) { return _Sn_PNR_(n); } -constexpr uint32_t _Sn_TOSR_(uint8_t n) { return (0x0104 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TTLR_(uint8_t n) { return (0x0108 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TOSR_(uint8_t n) { return (0x0104 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_TTLR_(uint8_t n) { return (0x0108 << 8) + SREG_BLOCK(n); } constexpr uint32_t _Sn_HOPR_(uint8_t n) { return _Sn_TTLR_(n); } -constexpr uint32_t _Sn_FRGR_(uint8_t n) { return (0x010C << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_MSSR_(uint8_t n) { return (0x0110 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PORTR_(uint8_t n) { return (0x0114 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DHAR_(uint8_t n) { return (0x0118 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DIPR_(uint8_t n) { return (0x0120 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_FRGR_(uint8_t n) { return (0x010C << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_MSSR_(uint8_t n) { return (0x0110 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_PORTR_(uint8_t n) { return (0x0114 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_DHAR_(uint8_t n) { return (0x0118 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_DIPR_(uint8_t n) { return (0x0120 << 8) + SREG_BLOCK(n); } constexpr uint32_t _Sn_DIP4R_(uint8_t n) { return _Sn_DIPR_(n); } -constexpr uint32_t _Sn_DIP6R_(uint8_t n) { return (0x0130 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DPORTR_(uint8_t n) { return (0x0140 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_MR2_(uint8_t n) { return (0x0144 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RTR_(uint8_t n) { return (0x0180 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RCR_(uint8_t n) { return (0x0184 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_BSR_(uint8_t n) { return (0x0200 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_FSR_(uint8_t n) { return (0x0204 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_RD_(uint8_t n) { return (0x0208 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_WR_(uint8_t n) { return (0x020C << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_BSR_(uint8_t n) { return (0x0220 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_RSR_(uint8_t n) { return (0x0224 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_RD_(uint8_t n) { return (0x0228 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_WR_(uint8_t n) { return (0x022C << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_DIP6R_(uint8_t n) { return (0x0130 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_DPORTR_(uint8_t n) { return (0x0140 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_MR2_(uint8_t n) { return (0x0144 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RTR_(uint8_t n) { return (0x0180 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RCR_(uint8_t n) { return (0x0184 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_BSR_(uint8_t n) { return (0x0200 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_FSR_(uint8_t n) { return (0x0204 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_RD_(uint8_t n) { return (0x0208 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_WR_(uint8_t n) { return (0x020C << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_BSR_(uint8_t n) { return (0x0220 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_RSR_(uint8_t n) { return (0x0224 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_RD_(uint8_t n) { return (0x0228 << 8) + SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_WR_(uint8_t n) { return (0x022C << 8) + SREG_BLOCK(n); } constexpr uint8_t SYSR_CHPL = 1 << 7; constexpr uint8_t SYSR_NETL = 1 << 6; @@ -572,277 +572,275 @@ constexpr uint16_t BMSR_LINK_STATUS = 1 << 2; constexpr uint16_t BMSR_JABBER_DETECT = 1 << 1; constexpr uint16_t BMSR_EXT_CAPA = 1 << 0; -void wizchip_cris_enter(); -void wizchip_cris_exit(); -inline void WIZCHIP_CRITICAL_ENTER() { wizchip_cris_enter(); } -inline void WIZCHIP_CRITICAL_EXIT() { wizchip_cris_exit(); } +void cris_enter(); +void cris_exit(); -uint8_t WIZCHIP_READ(uint32_t AddrSel); -void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb); -void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); -void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); +uint8_t reg_read(uint32_t AddrSel); +void reg_write(uint32_t AddrSel, uint8_t wb); +void reg_read_buf(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); +void reg_write_buf(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); uint16_t getSn_TX_FSR(uint8_t sn); uint16_t getSn_RX_RSR(uint8_t sn); -inline uint8_t getRTL() { return WIZCHIP_READ(_RTL_); } -inline uint16_t getCIDR() { return (((uint16_t)WIZCHIP_READ(_CIDR_) | (((WIZCHIP_READ(_RTL_)) & 0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_, 1)); } -inline uint16_t getVER() { return (((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_, 1)); } -inline uint8_t getSYSR() { return WIZCHIP_READ(_SYSR_); } -inline uint8_t getSYCR0() { return WIZCHIP_READ(_SYCR0_); } -inline void setSYCR0(uint8_t v) { WIZCHIP_WRITE(_SYCR0_, v); } -inline uint8_t getSYCR1() { return WIZCHIP_READ(_SYCR1_); } -inline void setSYCR1(uint8_t v) { WIZCHIP_WRITE(_SYCR1_, v); } -inline uint16_t getTCNTR() { return (((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_, 1)); } -inline void setTCNTRCLR(uint8_t v) { WIZCHIP_WRITE(_TCNTRCLR_, v); } -inline uint8_t getIR() { return WIZCHIP_READ(_IR_); } -inline uint8_t getSIR() { return WIZCHIP_READ(_SIR_); } -inline uint8_t getSLIR() { return WIZCHIP_READ(_SLIR_); } -inline void setIMR(uint8_t v) { WIZCHIP_WRITE(_IMR_, v); } -inline uint8_t getIMR() { return WIZCHIP_READ(_IMR_); } -inline void setIRCLR(uint8_t v) { WIZCHIP_WRITE(_IRCLR_, v); } +inline uint8_t getRTL() { return reg_read(_RTL_); } +inline uint16_t getCIDR() { return (((uint16_t)reg_read(_CIDR_) | (((reg_read(_RTL_)) & 0x0F) << 1)) << 8) + reg_read(offset_inc(_CIDR_, 1)); } +inline uint16_t getVER() { return (((uint16_t)reg_read(_VER_)) << 8) + reg_read(offset_inc(_VER_, 1)); } +inline uint8_t getSYSR() { return reg_read(_SYSR_); } +inline uint8_t getSYCR0() { return reg_read(_SYCR0_); } +inline void setSYCR0(uint8_t v) { reg_write(_SYCR0_, v); } +inline uint8_t getSYCR1() { return reg_read(_SYCR1_); } +inline void setSYCR1(uint8_t v) { reg_write(_SYCR1_, v); } +inline uint16_t getTCNTR() { return (((uint16_t)reg_read(_TCNTR_)) << 8) + reg_read(offset_inc(_TCNTR_, 1)); } +inline void setTCNTRCLR(uint8_t v) { reg_write(_TCNTRCLR_, v); } +inline uint8_t getIR() { return reg_read(_IR_); } +inline uint8_t getSIR() { return reg_read(_SIR_); } +inline uint8_t getSLIR() { return reg_read(_SLIR_); } +inline void setIMR(uint8_t v) { reg_write(_IMR_, v); } +inline uint8_t getIMR() { return reg_read(_IMR_); } +inline void setIRCLR(uint8_t v) { reg_write(_IRCLR_, v); } inline void setIR(uint8_t v) { setIRCLR(v); } -inline void setSIMR(uint8_t v) { WIZCHIP_WRITE(_SIMR_, v); } -inline uint8_t getSIMR() { return WIZCHIP_READ(_SIMR_); } -inline void setSLIMR(uint8_t v) { WIZCHIP_WRITE(_SLIMR_, v); } -inline uint8_t getSLIMR() { return WIZCHIP_READ(_SLIMR_); } -inline void setSLIRCLR(uint8_t v) { WIZCHIP_WRITE(_SLIRCLR_, v); } +inline void setSIMR(uint8_t v) { reg_write(_SIMR_, v); } +inline uint8_t getSIMR() { return reg_read(_SIMR_); } +inline void setSLIMR(uint8_t v) { reg_write(_SLIMR_, v); } +inline uint8_t getSLIMR() { return reg_read(_SLIMR_); } +inline void setSLIRCLR(uint8_t v) { reg_write(_SLIRCLR_, v); } inline void setSLIR(uint8_t v) { setSLIRCLR(v); } -inline void setSLPSR(uint8_t v) { WIZCHIP_WRITE(_SLPSR_, v); } -inline uint8_t getSLPSR() { return WIZCHIP_READ(_SLPSR_); } -inline void setSLCR(uint8_t v) { WIZCHIP_WRITE(_SLCR_, v); } -inline uint8_t getSLCR() { return WIZCHIP_READ(_SLCR_); } -inline uint8_t getPHYSR() { return WIZCHIP_READ(_PHYSR_); } -inline void setPHYRAR(uint8_t v) { WIZCHIP_WRITE(_PHYRAR_, v); } -inline uint8_t getPHYRAR() { return WIZCHIP_READ(_PHYRAR_); } +inline void setSLPSR(uint8_t v) { reg_write(_SLPSR_, v); } +inline uint8_t getSLPSR() { return reg_read(_SLPSR_); } +inline void setSLCR(uint8_t v) { reg_write(_SLCR_, v); } +inline uint8_t getSLCR() { return reg_read(_SLCR_); } +inline uint8_t getPHYSR() { return reg_read(_PHYSR_); } +inline void setPHYRAR(uint8_t v) { reg_write(_PHYRAR_, v); } +inline uint8_t getPHYRAR() { return reg_read(_PHYRAR_); } inline void setPHYDIR(uint16_t v) { - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_, 1), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(_PHYDIR_, (uint8_t)v); + reg_write(offset_inc(_PHYDIR_, 1), (uint8_t)(v >> 8)); + reg_write(_PHYDIR_, (uint8_t)v); } -inline uint16_t getPHYDOR() { return (((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_, 1))) << 8) + WIZCHIP_READ(_PHYDOR_); } -inline void setPHYACR(uint8_t v) { WIZCHIP_WRITE(_PHYACR_, v); } -inline uint8_t getPHYACR() { return WIZCHIP_READ(_PHYACR_); } -inline void setPHYDIVR(uint8_t v) { WIZCHIP_WRITE(_PHYDIVR_, v); } -inline uint8_t getPHYDIVR() { return WIZCHIP_READ(_PHYDIVR_); } -inline void setPHYCR0(uint8_t v) { WIZCHIP_WRITE(_PHYCR0_, v); } -inline void setPHYCR1(uint8_t v) { WIZCHIP_WRITE(_PHYCR1_, v); } -inline uint8_t getPHYCR1() { return WIZCHIP_READ(_PHYCR1_); } -inline void setNET4MR(uint8_t v) { WIZCHIP_WRITE(_NET4MR_, v); } -inline void setNET6MR(uint8_t v) { WIZCHIP_WRITE(_NET6MR_, v); } -inline void setNETMR(uint8_t v) { WIZCHIP_WRITE(_NETMR_, v); } -inline void setNETMR2(uint8_t v) { WIZCHIP_WRITE(_NETMR2_, v); } -inline uint8_t getNET4MR() { return WIZCHIP_READ(_NET4MR_); } -inline uint8_t getNET6MR() { return WIZCHIP_READ(_NET6MR_); } -inline uint8_t getNETMR() { return WIZCHIP_READ(_NETMR_); } -inline uint8_t getNETMR2() { return WIZCHIP_READ(_NETMR2_); } -inline void setPTMR(uint8_t v) { WIZCHIP_WRITE(_PTMR_, v); } -inline uint8_t getPTMR() { return WIZCHIP_READ(_PTMR_); } -inline void setPMNR(uint8_t v) { WIZCHIP_WRITE(_PMNR_, v); } -inline uint8_t getPMNR() { return WIZCHIP_READ(_PMNR_); } -inline void setPHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_PHAR_, v, 6); } -inline void getPHAR(uint8_t* v) { WIZCHIP_READ_BUF(_PHAR_, v, 6); } +inline uint16_t getPHYDOR() { return (((uint16_t)reg_read(offset_inc(_PHYDOR_, 1))) << 8) + reg_read(_PHYDOR_); } +inline void setPHYACR(uint8_t v) { reg_write(_PHYACR_, v); } +inline uint8_t getPHYACR() { return reg_read(_PHYACR_); } +inline void setPHYDIVR(uint8_t v) { reg_write(_PHYDIVR_, v); } +inline uint8_t getPHYDIVR() { return reg_read(_PHYDIVR_); } +inline void setPHYCR0(uint8_t v) { reg_write(_PHYCR0_, v); } +inline void setPHYCR1(uint8_t v) { reg_write(_PHYCR1_, v); } +inline uint8_t getPHYCR1() { return reg_read(_PHYCR1_); } +inline void setNET4MR(uint8_t v) { reg_write(_NET4MR_, v); } +inline void setNET6MR(uint8_t v) { reg_write(_NET6MR_, v); } +inline void setNETMR(uint8_t v) { reg_write(_NETMR_, v); } +inline void setNETMR2(uint8_t v) { reg_write(_NETMR2_, v); } +inline uint8_t getNET4MR() { return reg_read(_NET4MR_); } +inline uint8_t getNET6MR() { return reg_read(_NET6MR_); } +inline uint8_t getNETMR() { return reg_read(_NETMR_); } +inline uint8_t getNETMR2() { return reg_read(_NETMR2_); } +inline void setPTMR(uint8_t v) { reg_write(_PTMR_, v); } +inline uint8_t getPTMR() { return reg_read(_PTMR_); } +inline void setPMNR(uint8_t v) { reg_write(_PMNR_, v); } +inline uint8_t getPMNR() { return reg_read(_PMNR_); } +inline void setPHAR(uint8_t* v) { reg_write_buf(_PHAR_, v, 6); } +inline void getPHAR(uint8_t* v) { reg_read_buf(_PHAR_, v, 6); } inline void setPSIDR(uint16_t v) { - WIZCHIP_WRITE(_PSIDR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_, 1), (uint8_t)v); + reg_write(_PSIDR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_PSIDR_, 1), (uint8_t)v); } -inline uint16_t getPSIDR() { return (((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_, 1)); } +inline uint16_t getPSIDR() { return (((uint16_t)reg_read(_PSIDR_)) << 8) + reg_read(offset_inc(_PSIDR_, 1)); } inline void setPMRUR(uint16_t v) { - WIZCHIP_WRITE(_PMRUR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_, 1), (uint8_t)v); + reg_write(_PMRUR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_PMRUR_, 1), (uint8_t)v); } -inline uint16_t getPMRUR() { return (((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_, 1)); } -inline void setSHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SHAR_, v, 6); } -inline void getSHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SHAR_, v, 6); } -inline void setGAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GAR_, v, 4); } -inline void getGAR(uint8_t* v) { WIZCHIP_READ_BUF(_GAR_, v, 4); } +inline uint16_t getPMRUR() { return (((uint16_t)reg_read(_PMRUR_)) << 8) + reg_read(offset_inc(_PMRUR_, 1)); } +inline void setSHAR(uint8_t* v) { reg_write_buf(_SHAR_, v, 6); } +inline void getSHAR(uint8_t* v) { reg_read_buf(_SHAR_, v, 6); } +inline void setGAR(uint8_t* v) { reg_write_buf(_GAR_, v, 4); } +inline void getGAR(uint8_t* v) { reg_read_buf(_GAR_, v, 4); } inline void setGA4R(uint8_t* v) { setGAR(v); } inline void getGA4R(uint8_t* v) { getGAR(v); } -inline void setSUBR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUBR_, v, 4); } -inline void getSUBR(uint8_t* v) { WIZCHIP_READ_BUF(_SUBR_, v, 4); } +inline void setSUBR(uint8_t* v) { reg_write_buf(_SUBR_, v, 4); } +inline void getSUBR(uint8_t* v) { reg_read_buf(_SUBR_, v, 4); } inline void setSUB4R(uint8_t* v) { setSUBR(v); } inline void getSUB4R(uint8_t* v) { getSUBR(v); } -inline void setSIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SIPR_, v, 4); } -inline void getSIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SIPR_, v, 4); } -inline void setLLAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_LLAR_, v, 16); } -inline void getLLAR(uint8_t* v) { WIZCHIP_READ_BUF(_LLAR_, v, 16); } -inline void setGUAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GUAR_, v, 16); } -inline void getGUAR(uint8_t* v) { WIZCHIP_READ_BUF(_GUAR_, v, 16); } -inline void setSUB6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUB6R_, v, 16); } -inline void getSUB6R(uint8_t* v) { WIZCHIP_READ_BUF(_SUB6R_, v, 16); } -inline void setGA6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_GA6R_, v, 16); } -inline void getGA6R(uint8_t* v) { WIZCHIP_READ_BUF(_GA6R_, v, 16); } -inline void setSLDIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIPR_, v, 4); } +inline void setSIPR(uint8_t* v) { reg_write_buf(_SIPR_, v, 4); } +inline void getSIPR(uint8_t* v) { reg_read_buf(_SIPR_, v, 4); } +inline void setLLAR(uint8_t* v) { reg_write_buf(_LLAR_, v, 16); } +inline void getLLAR(uint8_t* v) { reg_read_buf(_LLAR_, v, 16); } +inline void setGUAR(uint8_t* v) { reg_write_buf(_GUAR_, v, 16); } +inline void getGUAR(uint8_t* v) { reg_read_buf(_GUAR_, v, 16); } +inline void setSUB6R(uint8_t* v) { reg_write_buf(_SUB6R_, v, 16); } +inline void getSUB6R(uint8_t* v) { reg_read_buf(_SUB6R_, v, 16); } +inline void setGA6R(uint8_t* v) { reg_write_buf(_GA6R_, v, 16); } +inline void getGA6R(uint8_t* v) { reg_read_buf(_GA6R_, v, 16); } +inline void setSLDIPR(uint8_t* v) { reg_write_buf(_SLDIPR_, v, 4); } inline void setSLDIP4R(uint8_t* v) { setSLDIPR(v); } -inline void getSLDIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIPR_, v, 4); } +inline void getSLDIPR(uint8_t* v) { reg_read_buf(_SLDIPR_, v, 4); } inline void getSLDIP4R(uint8_t* v) { getSLDIPR(v); } -inline void setSLDIP6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIP6R_, v, 16); } -inline void getSLDIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIP6R_, v, 16); } -inline void getSLDHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDHAR_, v, 6); } +inline void setSLDIP6R(uint8_t* v) { reg_write_buf(_SLDIP6R_, v, 16); } +inline void getSLDIP6R(uint8_t* v) { reg_read_buf(_SLDIP6R_, v, 16); } +inline void getSLDHAR(uint8_t* v) { reg_read_buf(_SLDHAR_, v, 6); } inline void setPINGIDR(uint16_t v) { - WIZCHIP_WRITE(_PINGIDR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_, 1), (uint8_t)v); + reg_write(_PINGIDR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_PINGIDR_, 1), (uint8_t)v); } -inline uint16_t getPINGIDR() { return ((uint16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_, 1)); } +inline uint16_t getPINGIDR() { return ((uint16_t)(reg_read(_PINGIDR_) << 8)) + reg_read(offset_inc(_PINGIDR_, 1)); } inline void setPINGSEQR(uint16_t v) { - WIZCHIP_WRITE(_PINGSEQR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1), (uint8_t)v); + reg_write(_PINGSEQR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_PINGSEQR_, 1), (uint8_t)v); } -inline uint16_t getPINGSEQR() { return ((uint16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1)); } -inline void getUIPR(uint8_t* v) { WIZCHIP_READ_BUF(_UIPR_, v, 4); } +inline uint16_t getPINGSEQR() { return ((uint16_t)(reg_read(_PINGSEQR_) << 8)) + reg_read(offset_inc(_PINGSEQR_, 1)); } +inline void getUIPR(uint8_t* v) { reg_read_buf(_UIPR_, v, 4); } inline void getUIP4R(uint8_t* v) { getUIPR(v); } -inline uint16_t getUPORTR() { return (((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_, 1)); } +inline uint16_t getUPORTR() { return (((uint16_t)reg_read(_UPORTR_)) << 8) + reg_read(offset_inc(_UPORTR_, 1)); } inline uint16_t getUPORT4R() { return getUPORTR(); } -inline void getUIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_UIP6R_, v, 16); } -inline uint16_t getUPORT6R() { return (((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_, 1)); } +inline void getUIP6R(uint8_t* v) { reg_read_buf(_UIP6R_, v, 16); } +inline uint16_t getUPORT6R() { return (((uint16_t)reg_read(_UPORT6R_)) << 8) + reg_read(offset_inc(_UPORT6R_, 1)); } inline void setINTPTMR(uint16_t v) { - WIZCHIP_WRITE(_INTPTMR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_, 1), (uint8_t)v); + reg_write(_INTPTMR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_INTPTMR_, 1), (uint8_t)v); } -inline uint16_t getINTPTMR() { return (((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_, 1)); } -inline uint8_t getPLR() { return WIZCHIP_READ(_PLR_); } -inline uint8_t getPFR() { return WIZCHIP_READ(_PFR_); } +inline uint16_t getINTPTMR() { return (((uint16_t)reg_read(_INTPTMR_)) << 8) + reg_read(offset_inc(_INTPTMR_, 1)); } +inline uint8_t getPLR() { return reg_read(_PLR_); } +inline uint8_t getPFR() { return reg_read(_PFR_); } inline uint32_t getVLTR() { - return (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 1))) << 16) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 2))) << 8) + - ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 3))); + return (((uint32_t)reg_read(_VLTR_)) << 24) + + (((uint32_t)reg_read(offset_inc(_VLTR_, 1))) << 16) + + (((uint32_t)reg_read(offset_inc(_VLTR_, 2))) << 8) + + ((uint32_t)reg_read(offset_inc(_VLTR_, 3))); } inline uint32_t getPLTR() { - return (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 1))) << 16) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 2))) << 8) + - ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 3))); + return (((uint32_t)reg_read(_PLTR_)) << 24) + + (((uint32_t)reg_read(offset_inc(_PLTR_, 1))) << 16) + + (((uint32_t)reg_read(offset_inc(_PLTR_, 2))) << 8) + + ((uint32_t)reg_read(offset_inc(_PLTR_, 3))); } -inline void getPAR(uint8_t* v) { WIZCHIP_READ_BUF(_PAR_, v, 16); } -inline void setICMP6BLKR(uint8_t v) { WIZCHIP_WRITE(_ICMP6BLKR_, v); } -inline uint8_t getICMP6BLKR() { return WIZCHIP_READ(_ICMP6BLKR_); } -inline void setCHPLCKR(uint8_t v) { WIZCHIP_WRITE(_CHPLCKR_, v); } +inline void getPAR(uint8_t* v) { reg_read_buf(_PAR_, v, 16); } +inline void setICMP6BLKR(uint8_t v) { reg_write(_ICMP6BLKR_, v); } +inline uint8_t getICMP6BLKR() { return reg_read(_ICMP6BLKR_); } +inline void setCHPLCKR(uint8_t v) { reg_write(_CHPLCKR_, v); } inline uint8_t getCHPLCKR() { return (getSYSR() & SYSR_CHPL) >> 7; } inline void CHIPLOCK() { setCHPLCKR(0xFF); } inline void CHIPUNLOCK() { setCHPLCKR(0xCE); } -inline void setNETLCKR(uint8_t v) { WIZCHIP_WRITE(_NETLCKR_, v); } +inline void setNETLCKR(uint8_t v) { reg_write(_NETLCKR_, v); } inline uint8_t getNETLCKR() { return (getSYSR() & SYSR_NETL) >> 6; } inline void NETLOCK() { setNETLCKR(0xC5); } inline void NETUNLOCK() { setNETLCKR(0x3A); } -inline void setPHYLCKR(uint8_t v) { WIZCHIP_WRITE(_PHYLCKR_, v); } +inline void setPHYLCKR(uint8_t v) { reg_write(_PHYLCKR_, v); } inline uint8_t getPHYLCKR() { return (getSYSR() & SYSR_PHYL) >> 5; } inline void PHYLOCK() { setPHYLCKR(0xFF); } inline void PHYUNLOCK() { setPHYLCKR(0x53); } inline void setRTR(uint16_t v) { - WIZCHIP_WRITE(_RTR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_, 1), (uint8_t)v); + reg_write(_RTR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_RTR_, 1), (uint8_t)v); } -inline uint16_t getRTR() { return (((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); } -inline void setRCR(uint8_t v) { WIZCHIP_WRITE(_RCR_, v); } -inline uint8_t getRCR() { return WIZCHIP_READ(_RCR_); } +inline uint16_t getRTR() { return (((uint16_t)reg_read(_RTR_)) << 8) + reg_read(offset_inc(_RTR_, 1)); } +inline void setRCR(uint8_t v) { reg_write(_RCR_, v); } +inline uint8_t getRCR() { return reg_read(_RCR_); } inline void setSLRTR(uint16_t v) { - WIZCHIP_WRITE(_SLRTR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_, 1), (uint8_t)v); + reg_write(_SLRTR_, (uint8_t)(v >> 8)); + reg_write(offset_inc(_SLRTR_, 1), (uint8_t)v); } -inline uint16_t getSLRTR() { return (((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_, 1)); } -inline void setSLRCR(uint8_t v) { WIZCHIP_WRITE(_SLRCR_, v); } -inline uint8_t getSLRCR() { return WIZCHIP_READ(_SLRCR_); } -inline void setSLHOPR(uint8_t v) { WIZCHIP_WRITE(_SLHOPR_, v); } -inline uint8_t getSLHOPR() { return WIZCHIP_READ(_SLHOPR_); } +inline uint16_t getSLRTR() { return (((uint16_t)reg_read(_SLRTR_)) << 8) + reg_read(offset_inc(_SLRTR_, 1)); } +inline void setSLRCR(uint8_t v) { reg_write(_SLRCR_, v); } +inline uint8_t getSLRCR() { return reg_read(_SLRCR_); } +inline void setSLHOPR(uint8_t v) { reg_write(_SLHOPR_, v); } +inline uint8_t getSLHOPR() { return reg_read(_SLHOPR_); } -inline void setSn_MR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR_(sn), v); } -inline uint8_t getSn_MR(uint8_t sn) { return WIZCHIP_READ(_Sn_MR_(sn)); } -inline void setSn_PSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PSR_(sn), v); } -inline uint8_t getSn_PSR(uint8_t sn) { return WIZCHIP_READ(_Sn_PSR_(sn)); } -inline void setSn_CR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_CR_(sn), v); } -inline uint8_t getSn_CR(uint8_t sn) { return WIZCHIP_READ(_Sn_CR_(sn)); } -inline uint8_t getSn_IR(uint8_t sn) { return WIZCHIP_READ(_Sn_IR_(sn)); } -inline void setSn_IMR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IMR_(sn), v); } -inline uint8_t getSn_IMR(uint8_t sn) { return WIZCHIP_READ(_Sn_IMR_(sn)); } -inline void setSn_IRCLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IRCLR_(sn), v); } +inline void setSn_MR(uint8_t sn, uint8_t v) { reg_write(_Sn_MR_(sn), v); } +inline uint8_t getSn_MR(uint8_t sn) { return reg_read(_Sn_MR_(sn)); } +inline void setSn_PSR(uint8_t sn, uint8_t v) { reg_write(_Sn_PSR_(sn), v); } +inline uint8_t getSn_PSR(uint8_t sn) { return reg_read(_Sn_PSR_(sn)); } +inline void setSn_CR(uint8_t sn, uint8_t v) { reg_write(_Sn_CR_(sn), v); } +inline uint8_t getSn_CR(uint8_t sn) { return reg_read(_Sn_CR_(sn)); } +inline uint8_t getSn_IR(uint8_t sn) { return reg_read(_Sn_IR_(sn)); } +inline void setSn_IMR(uint8_t sn, uint8_t v) { reg_write(_Sn_IMR_(sn), v); } +inline uint8_t getSn_IMR(uint8_t sn) { return reg_read(_Sn_IMR_(sn)); } +inline void setSn_IRCLR(uint8_t sn, uint8_t v) { reg_write(_Sn_IRCLR_(sn), v); } inline void setSn_IR(uint8_t sn, uint8_t v) { setSn_IRCLR(sn, v); } -inline uint8_t getSn_SR(uint8_t sn) { return WIZCHIP_READ(_Sn_SR_(sn)); } -inline uint8_t getSn_ESR(uint8_t sn) { return WIZCHIP_READ(_Sn_ESR_(sn)); } -inline void setSn_PNR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PNR_(sn), v); } +inline uint8_t getSn_SR(uint8_t sn) { return reg_read(_Sn_SR_(sn)); } +inline uint8_t getSn_ESR(uint8_t sn) { return reg_read(_Sn_ESR_(sn)); } +inline void setSn_PNR(uint8_t sn, uint8_t v) { reg_write(_Sn_PNR_(sn), v); } inline void setSn_NHR(uint8_t sn, uint8_t v) { setSn_PNR(sn, v); } -inline uint8_t getSn_PNR(uint8_t sn) { return WIZCHIP_READ(_Sn_PNR_(sn)); } +inline uint8_t getSn_PNR(uint8_t sn) { return reg_read(_Sn_PNR_(sn)); } inline uint8_t getSn_NHR(uint8_t sn) { return getSn_PNR(sn); } -inline void setSn_TOSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TOSR_(sn), v); } -inline uint8_t getSn_TOSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TOSR_(sn)); } +inline void setSn_TOSR(uint8_t sn, uint8_t v) { reg_write(_Sn_TOSR_(sn), v); } +inline uint8_t getSn_TOSR(uint8_t sn) { return reg_read(_Sn_TOSR_(sn)); } inline uint8_t getSn_TOS(uint8_t sn) { return getSn_TOSR(sn); } inline void setSn_TOS(uint8_t sn, uint8_t v) { setSn_TOSR(sn, v); } -inline void setSn_TTLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TTLR_(sn), v); } -inline uint8_t getSn_TTLR(uint8_t sn) { return WIZCHIP_READ(_Sn_TTLR_(sn)); } +inline void setSn_TTLR(uint8_t sn, uint8_t v) { reg_write(_Sn_TTLR_(sn), v); } +inline uint8_t getSn_TTLR(uint8_t sn) { return reg_read(_Sn_TTLR_(sn)); } inline void setSn_TTL(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } inline uint8_t getSn_TTL(uint8_t sn) { return getSn_TTLR(sn); } inline void setSn_HOPR(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } inline uint8_t getSn_HOPR(uint8_t sn) { return getSn_TTLR(sn); } inline void setSn_FRGR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_FRGR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1), (uint8_t)v); + reg_write(_Sn_FRGR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_FRGR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1)); } +inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)reg_read(_Sn_FRGR_(sn))) << 8) + reg_read(offset_inc(_Sn_FRGR_(sn), 1)); } inline void setSn_MSSR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_MSSR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1), (uint8_t)v); + reg_write(_Sn_MSSR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_MSSR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1)); } +inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)reg_read(_Sn_MSSR_(sn))) << 8) + reg_read(offset_inc(_Sn_MSSR_(sn), 1)); } inline void setSn_PORTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_PORTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1), (uint8_t)v); + reg_write(_Sn_PORTR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_PORTR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1)); } -inline void setSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn), v, 6); } -inline void getSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DHAR_(sn), v, 6); } -inline void setSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn), v, 4); } -inline void getSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIPR_(sn), v, 4); } +inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)reg_read(_Sn_PORTR_(sn))) << 8) + reg_read(offset_inc(_Sn_PORTR_(sn), 1)); } +inline void setSn_DHAR(uint8_t sn, uint8_t* v) { reg_write_buf(_Sn_DHAR_(sn), v, 6); } +inline void getSn_DHAR(uint8_t sn, uint8_t* v) { reg_read_buf(_Sn_DHAR_(sn), v, 6); } +inline void setSn_DIPR(uint8_t sn, uint8_t* v) { reg_write_buf(_Sn_DIPR_(sn), v, 4); } +inline void getSn_DIPR(uint8_t sn, uint8_t* v) { reg_read_buf(_Sn_DIPR_(sn), v, 4); } inline void setSn_DIP4R(uint8_t sn, uint8_t* v) { setSn_DIPR(sn, v); } inline void getSn_DIP4R(uint8_t sn, uint8_t* v) { getSn_DIPR(sn, v); } -inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn), v, 16); } -inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIP6R_(sn), v, 16); } +inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { reg_write_buf(_Sn_DIP6R_(sn), v, 16); } +inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { reg_read_buf(_Sn_DIP6R_(sn), v, 16); } inline void setSn_DPORTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_DPORTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1), (uint8_t)v); + reg_write(_Sn_DPORTR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_DPORTR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1)); } +inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)reg_read(_Sn_DPORTR_(sn))) << 8) + reg_read(offset_inc(_Sn_DPORTR_(sn), 1)); } inline uint16_t getSn_DPORT(uint8_t sn) { return getSn_DPORTR(sn); } inline void setSn_DPORT(uint8_t sn, uint16_t v) { setSn_DPORTR(sn, v); } -inline void setSn_MR2(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR2_(sn), v); } -inline uint8_t getSn_MR2(uint8_t sn) { return WIZCHIP_READ(_Sn_MR2_(sn)); } +inline void setSn_MR2(uint8_t sn, uint8_t v) { reg_write(_Sn_MR2_(sn), v); } +inline uint8_t getSn_MR2(uint8_t sn) { return reg_read(_Sn_MR2_(sn)); } inline void setSn_RTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_RTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1), (uint8_t)v); + reg_write(_Sn_RTR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_RTR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1)); } -inline void setSn_RCR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RCR_(sn), v); } -inline uint8_t getSn_RCR(uint8_t sn) { return WIZCHIP_READ(_Sn_RCR_(sn)); } -inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_KPALVTR_(sn), v); } -inline uint8_t getSn_KPALVTR(uint8_t sn) { return WIZCHIP_READ(_Sn_KPALVTR_(sn)); } -inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TX_BSR_(sn), v); } +inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)reg_read(_Sn_RTR_(sn))) << 8) + reg_read(offset_inc(_Sn_RTR_(sn), 1)); } +inline void setSn_RCR(uint8_t sn, uint8_t v) { reg_write(_Sn_RCR_(sn), v); } +inline uint8_t getSn_RCR(uint8_t sn) { return reg_read(_Sn_RCR_(sn)); } +inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { reg_write(_Sn_KPALVTR_(sn), v); } +inline uint8_t getSn_KPALVTR(uint8_t sn) { return reg_read(_Sn_KPALVTR_(sn)); } +inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { reg_write(_Sn_TX_BSR_(sn), v); } inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_TX_BSR(sn, v); } -inline uint8_t getSn_TX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TX_BSR_(sn)); } +inline uint8_t getSn_TX_BSR(uint8_t sn) { return reg_read(_Sn_TX_BSR_(sn)); } inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) { return getSn_TX_BSR(sn); } inline uint16_t getSn_TxMAX(uint8_t sn) { return getSn_TX_BSR(sn) << 10; } -inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn), 1)); } +inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)reg_read(_Sn_TX_RD_(sn))) << 8) + reg_read(offset_inc(_Sn_TX_RD_(sn), 1)); } inline void setSn_TX_WR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1), (uint8_t)v); + reg_write(_Sn_TX_WR_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_TX_WR_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1)); } -inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RX_BSR_(sn), v); } +inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)reg_read(_Sn_TX_WR_(sn)) << 8) + reg_read(offset_inc(_Sn_TX_WR_(sn), 1)); } +inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { reg_write(_Sn_RX_BSR_(sn), v); } inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_RX_BSR(sn, v); } -inline uint8_t getSn_RX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_RX_BSR_(sn)); } +inline uint8_t getSn_RX_BSR(uint8_t sn) { return reg_read(_Sn_RX_BSR_(sn)); } inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) { return getSn_RX_BSR(sn); } inline uint16_t getSn_RxMAX(uint8_t sn) { return getSn_RX_BSR(sn) << 10; } inline void setSn_RX_RD(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1), (uint8_t)v); + reg_write(_Sn_RX_RD_(sn), (uint8_t)(v >> 8)); + reg_write(offset_inc(_Sn_RX_RD_(sn), 1), (uint8_t)v); } -inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1)); } -inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn), 1)); } +inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)reg_read(_Sn_RX_RD_(sn)) << 8) + reg_read(offset_inc(_Sn_RX_RD_(sn), 1)); } +inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)reg_read(_Sn_RX_WR_(sn)) << 8) + reg_read(offset_inc(_Sn_RX_WR_(sn), 1)); } static critical_section_t g_cris_sec; -void wizchip_cris_enter() { +void cris_enter() { critical_section_enter_blocking(&g_cris_sec); } -void wizchip_cris_exit() { +void cris_exit() { critical_section_exit(&g_cris_sec); } @@ -854,46 +852,46 @@ static uint16_t make_addr(uint32_t addr) { return static_cast((addr & 0x00FFFF00) >> 8); } -void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) { - WIZCHIP_CRITICAL_ENTER(); - wizchip_pio_frame_start(); - wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), &wb, 1); - wizchip_pio_frame_end(); - WIZCHIP_CRITICAL_EXIT(); +void reg_write(uint32_t AddrSel, uint8_t wb) { + cris_enter(); + pio_frame_start(); + pio_write(make_opcode(AddrSel, SPI_WRITE), make_addr(AddrSel), &wb, 1); + pio_frame_end(); + cris_exit(); } -uint8_t WIZCHIP_READ(uint32_t AddrSel) { +uint8_t reg_read(uint32_t AddrSel) { uint8_t ret[2] = {0}; - WIZCHIP_CRITICAL_ENTER(); - wizchip_pio_frame_start(); - wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), ret, 1); - wizchip_pio_frame_end(); - WIZCHIP_CRITICAL_EXIT(); + cris_enter(); + pio_frame_start(); + pio_read(make_opcode(AddrSel, SPI_READ), make_addr(AddrSel), ret, 1); + pio_frame_end(); + cris_exit(); return ret[0]; } -void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) { - WIZCHIP_CRITICAL_ENTER(); - wizchip_pio_frame_start(); - wizchip_pio_write(make_opcode(AddrSel, W6300_SPI_WRITE), make_addr(AddrSel), pBuf, len); - wizchip_pio_frame_end(); - WIZCHIP_CRITICAL_EXIT(); +void reg_write_buf(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) { + cris_enter(); + pio_frame_start(); + pio_write(make_opcode(AddrSel, SPI_WRITE), make_addr(AddrSel), pBuf, len); + pio_frame_end(); + cris_exit(); } -void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) { - WIZCHIP_CRITICAL_ENTER(); - wizchip_pio_frame_start(); - wizchip_pio_read(make_opcode(AddrSel, W6300_SPI_READ), make_addr(AddrSel), pBuf, len); - wizchip_pio_frame_end(); - WIZCHIP_CRITICAL_EXIT(); +void reg_read_buf(uint32_t AddrSel, uint8_t* pBuf, datasize_t len) { + cris_enter(); + pio_frame_start(); + pio_read(make_opcode(AddrSel, SPI_READ), make_addr(AddrSel), pBuf, len); + pio_frame_end(); + cris_exit(); } uint16_t getSn_TX_FSR(uint8_t sn) { uint16_t prev_val = -1, val = 0; do { prev_val = val; - val = WIZCHIP_READ(_Sn_TX_FSR_(sn)); - val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_FSR_(sn), 1)); + val = reg_read(_Sn_TX_FSR_(sn)); + val = (val << 8) + reg_read(offset_inc(_Sn_TX_FSR_(sn), 1)); } while (val != prev_val); return val; } @@ -902,42 +900,42 @@ uint16_t getSn_RX_RSR(uint8_t sn) { uint16_t prev_val = -1, val = 0; do { prev_val = val; - val = WIZCHIP_READ(_Sn_RX_RSR_(sn)); - val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RSR_(sn), 1)); + val = reg_read(_Sn_RX_RSR_(sn)); + val = (val << 8) + reg_read(offset_inc(_Sn_RX_RSR_(sn), 1)); } while (val != prev_val); return val; } -void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) { +void send_data(uint8_t sn, uint8_t *data, uint16_t len) { uint16_t ptr = getSn_TX_WR(sn); - uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_TXBUF_BLOCK(sn); - WIZCHIP_WRITE_BUF(addrsel, wizdata, len); + uint32_t addrsel = ((uint32_t)ptr << 8) + TXBUF_BLOCK(sn); + reg_write_buf(addrsel, data, len); ptr += len; setSn_TX_WR(sn, ptr); } -void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) { +void recv_data(uint8_t sn, uint8_t *data, uint16_t len) { if (len == 0) return; uint16_t ptr = getSn_RX_RD(sn); - uint32_t addrsel = ((uint32_t)ptr << 8) + WIZCHIP_RXBUF_BLOCK(sn); - WIZCHIP_READ_BUF(addrsel, wizdata, len); + uint32_t addrsel = ((uint32_t)ptr << 8) + RXBUF_BLOCK(sn); + reg_read_buf(addrsel, data, len); ptr += len; setSn_RX_RD(sn, ptr); } -void wiz_recv_ignore(uint8_t sn, uint16_t len) { +void recv_ignore(uint8_t sn, uint16_t len) { setSn_RX_RD(sn, getSn_RX_RD(sn) + len); } -void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) { +void mdio_write(uint8_t phyregaddr, uint16_t var) { setPHYRAR(phyregaddr); setPHYDIR(var); setPHYACR(PHYACR_WRITE); while (getPHYACR()); } -uint16_t wiz_mdio_read(uint8_t phyregaddr) { +uint16_t mdio_read(uint8_t phyregaddr) { setPHYRAR(phyregaddr); setPHYACR(PHYACR_READ); while (getPHYACR()); @@ -950,7 +948,7 @@ static uint8_t dns_[4]; static uint8_t dns6_[16]; static ipconf_mode ipmode_; -static constexpr char WIZCHIP_ID[] = "W6300"; +static constexpr char CHIP_ID[] = "W6300"; int8_t ctl_chip(chip_ctl cwtype, void* arg) { uint8_t tmp = *(uint8_t*)arg; @@ -997,7 +995,7 @@ int8_t ctl_chip(chip_ctl cwtype, void* arg) { *(uint16_t*)arg = getINTPTMR(); break; case CW_GET_ID: - memcpy(arg, WIZCHIP_ID, sizeof(WIZCHIP_ID)); + memcpy(arg, CHIP_ID, sizeof(CHIP_ID)); break; case CW_GET_VER: *(uint16_t*)arg = getVER(); @@ -1117,22 +1115,22 @@ intr_kind get_interrupt_mask() { } int8_t get_phy_link() { - if (wiz_mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON; + if (mdio_read(PHYRAR_BMSR) & BMSR_LINK_STATUS) return PHY_LINK_ON; return PHY_LINK_OFF; } int8_t get_phy_power_mode() { - if (wiz_mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN; + if (mdio_read(PHYRAR_BMCR) & BMCR_PWDN) return PHY_POWER_DOWN; return PHY_POWER_NORM; } void reset_phy() { - wiz_mdio_write(PHYRAR_BMCR, wiz_mdio_read(PHYRAR_BMCR) | BMCR_RST); - while (wiz_mdio_read(PHYRAR_BMCR) & BMCR_RST); + mdio_write(PHYRAR_BMCR, mdio_read(PHYRAR_BMCR) | BMCR_RST); + while (mdio_read(PHYRAR_BMCR) & BMCR_RST); } void set_phy_conf(phy_conf* phyconf) { - uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR); + uint16_t tmp = mdio_read(PHYRAR_BMCR); if (phyconf->mode == PHY_MODE_TE) { setPHYCR1(getPHYCR1() | PHYCR1_TE); setPHYCR0(PHYCR0_AUTO); @@ -1145,12 +1143,12 @@ void set_phy_conf(phy_conf* phyconf) { if (phyconf->duplex == PHY_DUPLEX_FULL) tmp |= BMCR_DPX; if (phyconf->speed == PHY_SPEED_100) tmp |= BMCR_SPD; } - wiz_mdio_write(PHYRAR_BMCR, tmp); + mdio_write(PHYRAR_BMCR, tmp); } } void get_phy_conf(phy_conf* phyconf) { - uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR); + uint16_t tmp = mdio_read(PHYRAR_BMCR); phyconf->mode = (getPHYCR1() & PHYCR1_TE) ? PHY_MODE_TE : ((tmp & BMCR_ANE) ? PHY_MODE_AUTONEGO : PHY_MODE_MANUAL); phyconf->duplex = (tmp & BMCR_DPX) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF; phyconf->speed = (tmp & BMCR_SPD) ? PHY_SPEED_100 : PHY_SPEED_10; @@ -1164,10 +1162,10 @@ void get_phy_status(phy_conf* phyconf) { } void set_phy_power_mode(uint8_t pmode) { - uint16_t tmp = wiz_mdio_read(PHYRAR_BMCR); + uint16_t tmp = mdio_read(PHYRAR_BMCR); if (pmode == PHY_POWER_DOWN) tmp |= BMCR_PWDN; else tmp &= ~BMCR_PWDN; - wiz_mdio_write(PHYRAR_BMCR, tmp); + mdio_write(PHYRAR_BMCR, tmp); } void set_net_info(net_info* p) { @@ -1468,7 +1466,7 @@ std::expected send(socket_id sid, std::span if ((sock_io_mode_bits & (1 << sn)) && (len > freesize)) FAIL(busy); if (len <= freesize) break; } - wiz_send_data(sn, const_cast(buf.data()), len); + send_data(sn, const_cast(buf.data()), len); if (sock_is_sending & (1 << sn)) { while (!(getSn_IR(sn) & Sn_IR_SENDOK)) { tmp = getSn_SR(sn); @@ -1519,7 +1517,7 @@ std::expected recv(socket_id sid, std::span buf) }; if (recvsize < len) len = recvsize; - wiz_recv_data(sn, buf.data(), len); + recv_data(sn, buf.data(), len); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); return len; @@ -1576,7 +1574,7 @@ std::expected sendto(socket_id sid, std::span freesize)) FAIL(busy); if (len <= freesize) break; }; - wiz_send_data(sn, const_cast(buf.data()), len); + send_data(sn, const_cast(buf.data()), len); setSn_CR(sn, tcmd); while (getSn_CR(sn)); while (1) { @@ -1624,7 +1622,7 @@ std::expected recvfrom(socket_id sid, std::span b }; } - wiz_recv_data(sn, head, 2); + recv_data(sn, head, 2); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); pack_len = head[0] & 0x07; @@ -1638,7 +1636,7 @@ std::expected recvfrom(socket_id sid, std::span b sock_pack_info[sn] = head[0] & 0xF8; if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16; else *addrlen = 4; - wiz_recv_data(sn, addr, *addrlen); + recv_data(sn, addr, *addrlen); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); break; @@ -1654,7 +1652,7 @@ std::expected recvfrom(socket_id sid, std::span b } if (len < sock_remained_size[sn]) pack_len = len; else pack_len = sock_remained_size[sn]; - wiz_recv_data(sn, buf.data(), pack_len); + recv_data(sn, buf.data(), pack_len); break; case Sn_MR_IPRAW6: case Sn_MR_IPRAW4: @@ -1663,13 +1661,13 @@ std::expected recvfrom(socket_id sid, std::span b sock_pack_info[sn] = head[0] & 0xF8; if (sock_pack_info[sn] & PACK_IPv6) *addrlen = 16; else *addrlen = 4; - wiz_recv_data(sn, addr, *addrlen); + recv_data(sn, addr, *addrlen); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); } break; default: - wiz_recv_ignore(sn, pack_len); + recv_ignore(sn, pack_len); sock_remained_size[sn] = pack_len; break; } @@ -1678,7 +1676,7 @@ std::expected recvfrom(socket_id sid, std::span b sock_pack_info[sn] |= PACK_FIRST; if ((getSn_MR(sn) & 0x03) == 0x02) { if (port == 0) FAIL(arg); - wiz_recv_data(sn, head, 2); + recv_data(sn, head, 2); *port = static_cast((((uint16_t)head[0]) << 8) + head[1]); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); @@ -1686,7 +1684,7 @@ std::expected recvfrom(socket_id sid, std::span b if (len < sock_remained_size[sn]) pack_len = len; else pack_len = sock_remained_size[sn]; - wiz_recv_data(sn, buf.data(), pack_len); + recv_data(sn, buf.data(), pack_len); setSn_CR(sn, Sn_CR_RECV); while (getSn_CR(sn)); @@ -1704,16 +1702,16 @@ std::optional peek_socket_msg(socket_id sid, std::span uint32_t rx_ptr = 0; uint16_t i = 0, sub_idx = 0; if ((getSn_RX_RSR(sn) > 0) && (subsize > 0)) { - rx_ptr = ((uint32_t)getSn_RX_RD(sn) << 8) + WIZCHIP_RXBUF_BLOCK(sn); + rx_ptr = ((uint32_t)getSn_RX_RD(sn) << 8) + RXBUF_BLOCK(sn); sub_idx = 0; for (i = 0; i < getSn_RX_RSR(sn); i++) { - if (WIZCHIP_READ(rx_ptr) == submsg[sub_idx]) { + if (reg_read(rx_ptr) == submsg[sub_idx]) { sub_idx++; if (sub_idx == subsize) return static_cast(i + 1 - sub_idx); } else { sub_idx = 0; } - rx_ptr = WIZCHIP_OFFSET_INC(rx_ptr, 1); + rx_ptr = offset_inc(rx_ptr, 1); } } return std::nullopt; @@ -1729,7 +1727,7 @@ void reset() { } void init_spi() { - wizchip_pio_init(); + pio_init(); } void init_critical_section() { @@ -1737,7 +1735,7 @@ void init_critical_section() { } void init() { - wizchip_pio_frame_end(); + pio_frame_end(); uint8_t memsize[2][8] = {{4, 4, 4, 4, 4, 4, 4, 4}, {4, 4, 4, 4, 4, 4, 4, 4}}; ctl_chip(CW_INIT_WIZCHIP, (void *)memsize); }