diff --git a/CMakeLists.txt b/CMakeLists.txt index 290bfce..a246983 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -12,7 +12,7 @@ pico_sdk_init() add_executable(picomap picomap.cpp w6300/w6300.cpp - w6300/wizchip_qspi_pio.cpp + w6300/pio.cpp ) target_include_directories(picomap PRIVATE @@ -20,7 +20,7 @@ target_include_directories(picomap PRIVATE w6300 ) -pico_generate_pio_header(picomap ${CMAKE_CURRENT_LIST_DIR}/w6300/wizchip_qspi_pio.pio) +pico_generate_pio_header(picomap ${CMAKE_CURRENT_LIST_DIR}/w6300/pio.pio) pico_enable_stdio_usb(picomap 1) pico_enable_stdio_uart(picomap 0) diff --git a/picomap.cpp b/picomap.cpp index b7f5fdc..97c7a2f 100644 --- a/picomap.cpp +++ b/picomap.cpp @@ -4,8 +4,7 @@ #include "pico/unique_id.h" #include "device.h" -#include "wizchip_conf.h" -#include "wizchip_spi.h" +#include "w6300.h" static void send_bytes(const std::vector &data) { for (auto b : data) { @@ -19,15 +18,18 @@ static bool w6300_init() { wizchip_cris_initialize(); wizchip_reset(); wizchip_initialize(); - if (getCIDR() != 0x6300) return false; + if (!wizchip_check()) return false; pico_unique_board_id_t uid; pico_get_unique_board_id(&uid); - uint8_t mac[6] = { - static_cast((uid.id[0] & 0xFC) | 0x02), - uid.id[1], uid.id[2], uid.id[3], uid.id[4], uid.id[5] - }; - setSHAR(mac); + wiz_NetInfo net_info = {}; + net_info.mac[0] = (uid.id[0] & 0xFC) | 0x02; + net_info.mac[1] = uid.id[1]; + net_info.mac[2] = uid.id[2]; + net_info.mac[3] = uid.id[3]; + net_info.mac[4] = uid.id[4]; + net_info.mac[5] = uid.id[5]; + network_initialize(net_info); return true; } @@ -67,7 +69,9 @@ int main() { pico_unique_board_id_t uid; pico_get_unique_board_id(&uid); std::copy(uid.id, uid.id + 8, info.board_id.begin()); - getSHAR(info.mac.data()); + wiz_NetInfo net_info; + wizchip_getnetinfo(&net_info); + std::copy(net_info.mac, net_info.mac + 6, info.mac.begin()); send_bytes(encode_response(msg->message_id, info)); break; } diff --git a/w6300/wizchip_qspi_pio.cpp b/w6300/pio.cpp similarity index 99% rename from w6300/wizchip_qspi_pio.cpp rename to w6300/pio.cpp index f30cf4b..23fcc04 100644 --- a/w6300/wizchip_qspi_pio.cpp +++ b/w6300/pio.cpp @@ -5,9 +5,9 @@ #include "pico/error.h" #include "hardware/dma.h" #include "hardware/clocks.h" -#include "wizchip_spi.h" -#include "wizchip_qspi_pio.h" -#include "wizchip_qspi_pio.pio.h" +#include "w6300_internal.h" +#include "pio.h" +#include "pio.pio.h" #define PIO_PROGRAM_NAME wizchip_pio_spi_quad_write_read #define PIO_PROGRAM_FUNC __CONCAT(PIO_PROGRAM_NAME, _program) diff --git a/w6300/wizchip_qspi_pio.h b/w6300/pio.h similarity index 100% rename from w6300/wizchip_qspi_pio.h rename to w6300/pio.h diff --git a/w6300/wizchip_qspi_pio.pio b/w6300/pio.pio similarity index 100% rename from w6300/wizchip_qspi_pio.pio rename to w6300/pio.pio diff --git a/w6300/socket.h b/w6300/socket.h deleted file mode 100644 index 45f03b5..0000000 --- a/w6300/socket.h +++ /dev/null @@ -1,118 +0,0 @@ -#pragma once -#include "wizchip_conf.h" - -using SOCKET = uint8_t; - -constexpr int16_t SOCK_OK = 1; -constexpr int16_t SOCK_BUSY = 0; -constexpr int16_t SOCK_FATAL = -1000; -constexpr int16_t SOCK_ERROR = 0; -constexpr int16_t SOCKERR_SOCKNUM = SOCK_ERROR - 1; -constexpr int16_t SOCKERR_SOCKOPT = SOCK_ERROR - 2; -constexpr int16_t SOCKERR_SOCKINIT = SOCK_ERROR - 3; -constexpr int16_t SOCKERR_SOCKCLOSED = SOCK_ERROR - 4; -constexpr int16_t SOCKERR_SOCKMODE = SOCK_ERROR - 5; -constexpr int16_t SOCKERR_SOCKFLAG = SOCK_ERROR - 6; -constexpr int16_t SOCKERR_SOCKSTATUS = SOCK_ERROR - 7; -constexpr int16_t SOCKERR_ARG = SOCK_ERROR - 10; -constexpr int16_t SOCKERR_PORTZERO = SOCK_ERROR - 11; -constexpr int16_t SOCKERR_IPINVALID = SOCK_ERROR - 12; -constexpr int16_t SOCKERR_TIMEOUT = SOCK_ERROR - 13; -constexpr int16_t SOCKERR_DATALEN = SOCK_ERROR - 14; -constexpr int16_t SOCKERR_BUFFER = SOCK_ERROR - 15; -constexpr int16_t SOCKFATAL_PACKLEN = SOCK_FATAL - 1; - -constexpr uint8_t SF_MULTI_ENABLE = Sn_MR_MULTI; -constexpr uint8_t SF_ETHER_OWN = Sn_MR_MF; -constexpr uint8_t SF_BROAD_BLOCK = Sn_MR_BRDB; -constexpr uint8_t SF_TCP_FPSH = Sn_MR_FPSH; -constexpr uint8_t SF_TCP_NODELAY = Sn_MR_ND; -constexpr uint8_t SF_IGMP_VER2 = Sn_MR_MC; -constexpr uint8_t SF_SOLICIT_BLOCK = Sn_MR_SMB; -constexpr uint8_t SF_ETHER_MULTI4B = Sn_MR_MMB4; -constexpr uint8_t SF_UNI_BLOCK = Sn_MR_UNIB; -constexpr uint8_t SF_ETHER_MULIT6B = Sn_MR_MMB6; -constexpr uint8_t SF_FORCE_ARP = Sn_MR2_FARP; -constexpr uint8_t SF_DHA_MANUAL = Sn_MR2_DHAM; -constexpr uint8_t SF_IO_NONBLOCK = 0x01 << 3; - -constexpr uint8_t PACK_IPv6 = 1 << 7; -constexpr uint8_t PACK_IPV6_ALLNODE = PACK_IPv6 | (1 << 6); -constexpr uint8_t PACK_IPV6_MULTI = PACK_IPv6 | (1 << 5); -constexpr uint8_t PACK_IPV6_LLA = PACK_IPv6 | (1 << 4); -constexpr uint8_t PACK_COMPLETED = 1 << 3; -constexpr uint8_t PACK_REMAINED = 1 << 2; -constexpr uint8_t PACK_FIRST = 1 << 1; -constexpr uint8_t PACK_NONE = 0x00; - -constexpr uint8_t SRCV6_PREFER_AUTO = PSR_AUTO; -constexpr uint8_t SRCV6_PREFER_LLA = PSR_LLA; -constexpr uint8_t SRCV6_PREFER_GUA = PSR_GUA; - -constexpr uint8_t TCPSOCK_MODE = Sn_ESR_TCPM; -constexpr uint8_t TCPSOCK_OP = Sn_ESR_TCPOP; -constexpr uint8_t TCPSOCK_SIP = Sn_ESR_IP6T; - -constexpr uint8_t SOCK_IO_BLOCK = 0; -constexpr uint8_t SOCK_IO_NONBLOCK = 1; - -int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag); -int8_t close(uint8_t sn); -int8_t listen(uint8_t sn); -int8_t disconnect(uint8_t sn); -int32_t send(uint8_t sn, uint8_t * buf, uint16_t len); -int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len); - -typedef enum { - SIK_CONNECTED = (1 << 0), - SIK_DISCONNECTED = (1 << 1), - SIK_RECEIVED = (1 << 2), - SIK_TIMEOUT = (1 << 3), - SIK_SENT = (1 << 4), - SIK_ALL = 0x1F -} sockint_kind; - -typedef enum { - CS_SET_IOMODE, - CS_GET_IOMODE, - CS_GET_MAXTXBUF, - CS_GET_MAXRXBUF, - CS_CLR_INTERRUPT, - CS_GET_INTERRUPT, - CS_SET_PREFER, - CS_GET_PREFER, - CS_SET_INTMASK, - CS_GET_INTMASK -} ctlsock_type; - -typedef enum { - SO_FLAG, - SO_TTL, - SO_TOS, - SO_MSS, - SO_DESTIP, - SO_DESTPORT, - SO_KEEPALIVESEND, - SO_KEEPALIVEAUTO, - SO_SENDBUF, - SO_RECVBUF, - SO_STATUS, - SO_EXTSTATUS, - SO_MODE, - SO_REMAINSIZE, - SO_PACKINFO -} sockopt_type; - -int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg); -int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg); -int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg); -int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize); - -int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen); -int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen); -int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen); - -inline int8_t connect(uint8_t sn, uint8_t* addr, uint16_t port, uint8_t addrlen) { return connect_W6x00(sn, addr, port, addrlen); } -inline int32_t sendto(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t port, uint8_t addrlen) { return sendto_W6x00(sn, buf, len, addr, port, addrlen); } -inline int32_t recvfrom(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t* port, uint8_t* addrlen) { return recvfrom_W6x00(sn, buf, len, addr, port, addrlen); } - diff --git a/w6300/w6300.cpp b/w6300/w6300.cpp index f382b36..855b477 100644 --- a/w6300/w6300.cpp +++ b/w6300/w6300.cpp @@ -2,9 +2,8 @@ #include #include "pico/stdlib.h" #include "pico/critical_section.h" -#include "socket.h" -#include "wizchip_spi.h" -#include "wizchip_qspi_pio.h" +#include "w6300_internal.h" +#include "pio.h" static critical_section_t g_cris_sec; @@ -39,11 +38,8 @@ void wizchip_initialize() { ctlwizchip(CW_INIT_WIZCHIP, (void *)memsize); } -void wizchip_check() { - if (getCIDR() != 0x6300) { - printf("W6300 ACCESS ERR: CIDR = 0x%04x\n", getCIDR()); - while (1); - } +bool wizchip_check() { + return getCIDR() == 0x6300; } void network_initialize(wiz_NetInfo net_info) { @@ -611,7 +607,7 @@ int8_t listen(uint8_t sn) { return SOCK_OK; } -int8_t connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen) { +int8_t connect(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen) { CHECK_SOCKNUM(); CHECK_TCPMODE(); CHECK_SOCKINIT(); @@ -732,7 +728,7 @@ int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len) { return (int32_t)len; } -int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen) { +int32_t sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen) { uint8_t tmp = 0; uint8_t tcmd = Sn_CR_SEND; uint16_t freesize = 0; @@ -796,7 +792,7 @@ int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, ui return (int32_t)len; } -int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen) { +int32_t recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen) { uint8_t mr; uint8_t head[8]; uint16_t pack_len = 0; diff --git a/w6300/w6300.h b/w6300/w6300.h index 690767c..3f11bb1 100644 --- a/w6300/w6300.h +++ b/w6300/w6300.h @@ -1,570 +1,278 @@ #pragma once #include -#include "wizchip_conf.h" -constexpr uint8_t W6300_SPI_READ = (0x00 << 5); -constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5); +constexpr int WIZCHIP_SOCK_NUM = 8; -constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00; -constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; } -constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; } -constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; } +enum ctlwizchip_type { + CW_SYS_LOCK, CW_SYS_UNLOCK, CW_GET_SYSLOCK, + CW_RESET_WIZCHIP, CW_INIT_WIZCHIP, + CW_GET_INTERRUPT, CW_CLR_INTERRUPT, CW_SET_INTRMASK, CW_GET_INTRMASK, + CW_SET_INTRTIME, CW_GET_INTRTIME, CW_SET_IEN, CW_GET_IEN, + CW_GET_ID, CW_GET_VER, CW_SET_SYSCLK, CW_GET_SYSCLK, + CW_RESET_PHY, CW_SET_PHYCONF, CW_GET_PHYCONF, CW_GET_PHYSTATUS, + CW_SET_PHYPOWMODE, CW_GET_PHYPOWMODE, CW_GET_PHYLINK +}; -constexpr uint32_t WIZCHIP_OFFSET_INC(uint32_t addr, uint32_t n) { return addr + (n << 8); } +enum ctlnetwork_type { + CN_SET_NETINFO, CN_GET_NETINFO, CN_SET_NETMODE, CN_GET_NETMODE, + CN_SET_TIMEOUT, CN_GET_TIMEOUT, CN_SET_PREFER, CN_GET_PREFER, +}; -constexpr uint32_t _CIDR_ = (0x0000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RTL_ = (0x0004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _VER_ = (0x0002 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYSR_ = (0x2000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYCR0_ = (0x2004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SYCR1_ = WIZCHIP_OFFSET_INC(_SYCR0_, 1); -constexpr uint32_t _TCNTR_ = (0x2016 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _TCNTRCLR_ = (0x2020 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IR_ = (0x2100 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SIR_ = (0x2101 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIR_ = (0x2102 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IMR_ = (0x2104 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _IRCLR_ = (0x2108 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SIMR_ = (0x2114 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIMR_ = (0x2124 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLIRCLR_ = (0x2128 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLPSR_ = (0x212C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLCR_ = (0x2130 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYSR_ = (0x3000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYRAR_ = (0x3008 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDIR_ = (0x300C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDOR_ = (0x3010 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYACR_ = (0x3014 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYDIVR_ = (0x3018 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYCR0_ = (0x301C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYCR1_ = WIZCHIP_OFFSET_INC(_PHYCR0_, 1); -constexpr uint32_t _NET4MR_ = (0x4000 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NET6MR_ = (0x4004 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETMR_ = (0x4008 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETMR2_ = (0x4009 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PTMR_ = (0x4100 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PMNR_ = (0x4104 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHAR_ = (0x4108 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PSIDR_ = (0x4110 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PMRUR_ = (0x4114 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SHAR_ = (0x4120 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GAR_ = (0x4130 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GA4R_ = _GAR_; -constexpr uint32_t _SUBR_ = (0x4134 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SUB4R_ = _SUBR_; -constexpr uint32_t _SIPR_ = (0x4138 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SIP4R_ = _SIPR_; -constexpr uint32_t _LLAR_ = (0x4140 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GUAR_ = (0x4150 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SUB6R_ = (0x4160 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _GA6R_ = (0x4170 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLDIP6R_ = (0x4180 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLDIPR_ = (0x418C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLDIP4R_ = _SLDIPR_; -constexpr uint32_t _SLDHAR_ = (0x4190 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PINGIDR_ = (0x4198 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PINGSEQR_ = (0x419C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UIPR_ = (0x41A0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UIP4R_ = _UIPR_; -constexpr uint32_t _UPORTR_ = (0x41A4 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UPORT4R_ = _UPORTR_; -constexpr uint32_t _UIP6R_ = (0x41B0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _UPORT6R_ = (0x41C0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _INTPTMR_ = (0x41C5 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PLR_ = (0x41D0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PFR_ = (0x41D4 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _VLTR_ = (0x41D8 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PLTR_ = (0x41DC << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PAR_ = (0x41E0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _CHPLCKR_ = (0x41F4 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _NETLCKR_ = (0x41F5 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _PHYLCKR_ = (0x41F6 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RTR_ = (0x4200 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _RCR_ = (0x4204 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLRTR_ = (0x4208 << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLRCR_ = (0x420C << 8) + WIZCHIP_CREG_BLOCK; -constexpr uint32_t _SLHOPR_ = (0x420F << 8) + WIZCHIP_CREG_BLOCK; +enum ctlnetservice_type { + CNS_ARP, CNS_PING, CNS_DAD, CNS_SLAAC, CNS_UNSOL_NA, CNS_GET_PREFIX +}; -constexpr uint32_t _Sn_MR_(uint8_t n) { return (0x0000 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PSR_(uint8_t n) { return (0x0004 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_CR_(uint8_t n) { return (0x0010 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IR_(uint8_t n) { return (0x0020 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IMR_(uint8_t n) { return (0x0024 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_IRCLR_(uint8_t n) { return (0x0028 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_SR_(uint8_t n) { return (0x0030 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_ESR_(uint8_t n) { return (0x0031 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PNR_(uint8_t n) { return (0x0100 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_NHR_(uint8_t n) { return _Sn_PNR_(n); } -constexpr uint32_t _Sn_TOSR_(uint8_t n) { return (0x0104 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TTLR_(uint8_t n) { return (0x0108 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_HOPR_(uint8_t n) { return _Sn_TTLR_(n); } -constexpr uint32_t _Sn_FRGR_(uint8_t n) { return (0x010C << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_MSSR_(uint8_t n) { return (0x0110 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_PORTR_(uint8_t n) { return (0x0114 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DHAR_(uint8_t n) { return (0x0118 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DIPR_(uint8_t n) { return (0x0120 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DIP4R_(uint8_t n) { return _Sn_DIPR_(n); } -constexpr uint32_t _Sn_DIP6R_(uint8_t n) { return (0x0130 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_DPORTR_(uint8_t n) { return (0x0140 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_MR2_(uint8_t n) { return (0x0144 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RTR_(uint8_t n) { return (0x0180 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RCR_(uint8_t n) { return (0x0184 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_BSR_(uint8_t n) { return (0x0200 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_FSR_(uint8_t n) { return (0x0204 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_RD_(uint8_t n) { return (0x0208 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_TX_WR_(uint8_t n) { return (0x020C << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_BSR_(uint8_t n) { return (0x0220 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_RSR_(uint8_t n) { return (0x0224 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_RD_(uint8_t n) { return (0x0228 << 8) + WIZCHIP_SREG_BLOCK(n); } -constexpr uint32_t _Sn_RX_WR_(uint8_t n) { return (0x022C << 8) + WIZCHIP_SREG_BLOCK(n); } +enum intr_kind : uint32_t { + IK_PPPOE_TERMINATED = (1 << 0), IK_DEST_UNREACH = (1 << 1), IK_IP_CONFLICT = (1 << 2), + IK_DEST_UNREACH6 = (1 << 4), IK_WOL = (1 << 7), IK_NET_ALL = 0x97, + IK_SOCK_0 = (1 << 8), IK_SOCK_1 = (1 << 9), IK_SOCK_2 = (1 << 10), IK_SOCK_3 = (1 << 11), + IK_SOCK_4 = (1 << 12), IK_SOCK_5 = (1 << 13), IK_SOCK_6 = (1 << 14), IK_SOCK_7 = (1 << 15), + IK_SOCK_ALL = (0xFF << 8), + IK_SOCKL_TOUT = (1 << 16), IK_SOCKL_ARP4 = (1 << 17), IK_SOCKL_PING4 = (1 << 18), + IK_SOCKL_ARP6 = (1 << 19), IK_SOCKL_PING6 = (1 << 20), IK_SOCKL_NS = (1 << 21), + IK_SOCKL_RS = (1 << 22), IK_SOCKL_RA = (1 << 23), IK_SOCKL_ALL = (0xFF << 16), + IK_INT_ALL = 0x00FFFF97 +}; -constexpr uint8_t SYSR_CHPL = 1 << 7; -constexpr uint8_t SYSR_NETL = 1 << 6; -constexpr uint8_t SYSR_PHYL = 1 << 5; -constexpr uint8_t SYSR_IND = 1 << 5; -constexpr uint8_t SYSR_SPI = 1 << 0; -constexpr uint8_t SYCR0_RST = 0x00; -constexpr uint8_t SYCR1_IEN = 1 << 7; -constexpr uint8_t SYCR1_CLKSEL = 1 << 0; -constexpr uint8_t SYCR1_CLKSEL_25M = 1; -constexpr uint8_t SYCR1_CLKSEL_100M = 0; -constexpr uint8_t IR_WOL = 1 << 7; -constexpr uint8_t IR_UNR6 = 1 << 4; -constexpr uint8_t IR_IPCONF = 1 << 2; -constexpr uint8_t IR_UNR4 = 1 << 1; -constexpr uint8_t IR_PTERM = 1 << 0; -constexpr uint8_t SIR_INT(uint8_t n) { return 1 << n; } -constexpr uint8_t SLIR_TOUT = 1 << 7; -constexpr uint8_t SLIR_ARP4 = 1 << 6; -constexpr uint8_t SLIR_PING4 = 1 << 5; -constexpr uint8_t SLIR_ARP6 = 1 << 4; -constexpr uint8_t SLIR_PING6 = 1 << 3; -constexpr uint8_t SLIR_NS = 1 << 2; -constexpr uint8_t SLIR_RS = 1 << 1; -constexpr uint8_t SLIR_RA = 1 << 0; -constexpr uint8_t PSR_AUTO = 0x00; -constexpr uint8_t PSR_LLA = 0x02; -constexpr uint8_t PSR_GUA = 0x03; -constexpr uint8_t SLCR_ARP4 = 1 << 6; -constexpr uint8_t SLCR_PING4 = 1 << 5; -constexpr uint8_t SLCR_ARP6 = 1 << 4; -constexpr uint8_t SLCR_PING6 = 1 << 3; -constexpr uint8_t SLCR_NS = 1 << 2; -constexpr uint8_t SLCR_RS = 1 << 1; -constexpr uint8_t SLCR_UNA = 1 << 0; -constexpr uint8_t PHYSR_CAB = 1 << 7; -constexpr uint8_t PHYSR_CAB_OFF = 1 << 7; -constexpr uint8_t PHYSR_CAB_ON = 0 << 7; -constexpr uint8_t PHYSR_MODE = 7 << 3; -constexpr uint8_t PHYSR_MODE_AUTO = 0 << 3; -constexpr uint8_t PHYSR_MODE_100F = 4 << 3; -constexpr uint8_t PHYSR_MODE_100H = 5 << 3; -constexpr uint8_t PHYSR_MODE_10F = 6 << 3; -constexpr uint8_t PHYSR_MODE_10H = 7 << 3; -constexpr uint8_t PHYSR_DPX = 1 << 2; -constexpr uint8_t PHYSR_DPX_HALF = 1 << 2; -constexpr uint8_t PHYSR_DPX_FULL = 0 << 2; -constexpr uint8_t PHYSR_SPD = 1 << 1; -constexpr uint8_t PHYSR_SPD_10M = 1 << 1; -constexpr uint8_t PHYSR_SPD_100M = 0 << 1; -constexpr uint8_t PHYSR_LNK = 1 << 0; -constexpr uint8_t PHYSR_LNK_UP = 1 << 0; -constexpr uint8_t PHYSR_LNK_DOWN = 0 << 0; -constexpr uint8_t PHYACR_READ = 0x02; -constexpr uint8_t PHYACR_WRITE = 0x01; -constexpr uint8_t PHYDIVR_32 = 0x00; -constexpr uint8_t PHYDIVR_64 = 0x01; -constexpr uint8_t PHYDIVR_128 = 0xFF; -constexpr uint8_t PHYCR0_AUTO = 0x00; -constexpr uint8_t PHYCR0_100F = 0x04; -constexpr uint8_t PHYCR0_100H = 0x05; -constexpr uint8_t PHYCR0_10F = 0x06; -constexpr uint8_t PHYCR0_10H = 0x07; -constexpr uint8_t PHYCR1_PWDN = 1 << 5; -constexpr uint8_t PHYCR1_TE = 1 << 3; -constexpr uint8_t PHYCR1_RST = 1 << 0; -constexpr uint8_t NETxMR_UNRB = 1 << 3; -constexpr uint8_t NETxMR_PARP = 1 << 2; -constexpr uint8_t NETxMR_RSTB = 1 << 1; -constexpr uint8_t NETxMR_PB = 1 << 0; -constexpr uint8_t NETMR_ANB = 1 << 5; -constexpr uint8_t NETMR_M6B = 1 << 4; -constexpr uint8_t NETMR_WOL = 1 << 2; -constexpr uint8_t NETMR_IP6B = 1 << 1; -constexpr uint8_t NETMR_IP4B = 1 << 0; -constexpr uint8_t NETMR2_DHAS = 1 << 7; -constexpr uint8_t NETMR2_DHAS_ARP = 1 << 7; -constexpr uint8_t NETMR2_DHAS_ETH = 0 << 7; -constexpr uint8_t NETMR2_PPPoE = 1 << 0; -constexpr uint8_t ICMP6BLKR_PING6 = 1 << 4; -constexpr uint8_t ICMP6BLKR_MLD = 1 << 3; -constexpr uint8_t ICMP6BLKR_RA = 1 << 2; -constexpr uint8_t ICMP6BLKR_NA = 1 << 1; -constexpr uint8_t ICMP6BLKR_NS = 1 << 0; -constexpr uint8_t Sn_MR_MULTI = 1 << 7; -constexpr uint8_t Sn_MR_MF = 1 << 7; -constexpr uint8_t Sn_MR_BRDB = 1 << 6; -constexpr uint8_t Sn_MR_FPSH = 1 << 6; -constexpr uint8_t Sn_MR_ND = 1 << 5; -constexpr uint8_t Sn_MR_MC = 1 << 5; -constexpr uint8_t Sn_MR_SMB = 1 << 5; -constexpr uint8_t Sn_MR_MMB = 1 << 5; -constexpr uint8_t Sn_MR_MMB4 = Sn_MR_MMB; -constexpr uint8_t Sn_MR_UNIB = 1 << 4; -constexpr uint8_t Sn_MR_MMB6 = 1 << 4; -constexpr uint8_t Sn_MR_CLOSE = 0x00; -constexpr uint8_t Sn_MR_TCP = 0x01; -constexpr uint8_t Sn_MR_TCP4 = Sn_MR_TCP; -constexpr uint8_t Sn_MR_UDP = 0x02; -constexpr uint8_t Sn_MR_UDP4 = Sn_MR_UDP; -constexpr uint8_t Sn_MR_IPRAW = 0x03; -constexpr uint8_t Sn_MR_IPRAW4 = Sn_MR_IPRAW; -constexpr uint8_t Sn_MR_MACRAW = 0x07; -constexpr uint8_t Sn_MR_TCP6 = 0x09; -constexpr uint8_t Sn_MR_UDP6 = 0x0A; -constexpr uint8_t Sn_MR_IPRAW6 = 0x0B; -constexpr uint8_t Sn_MR_TCPD = 0x0D; -constexpr uint8_t Sn_MR_UDPD = 0x0E; -constexpr uint8_t Sn_CR_OPEN = 0x01; -constexpr uint8_t Sn_CR_LISTEN = 0x02; -constexpr uint8_t Sn_CR_CONNECT = 0x04; -constexpr uint8_t Sn_CR_CONNECT6 = 0x84; -constexpr uint8_t Sn_CR_DISCON = 0x08; -constexpr uint8_t Sn_CR_CLOSE = 0x10; -constexpr uint8_t Sn_CR_SEND = 0x20; -constexpr uint8_t Sn_CR_SEND6 = 0xA0; -constexpr uint8_t Sn_CR_SEND_KEEP = 0x22; -constexpr uint8_t Sn_CR_RECV = 0x40; -constexpr uint8_t Sn_IR_SENDOK = 0x10; -constexpr uint8_t Sn_IR_TIMEOUT = 0x08; -constexpr uint8_t Sn_IR_RECV = 0x04; -constexpr uint8_t Sn_IR_DISCON = 0x02; -constexpr uint8_t Sn_IR_CON = 0x01; -constexpr uint8_t SOCK_CLOSED = 0x00; -constexpr uint8_t SOCK_INIT = 0x13; -constexpr uint8_t SOCK_LISTEN = 0x14; -constexpr uint8_t SOCK_SYNSENT = 0x15; -constexpr uint8_t SOCK_SYNRECV = 0x16; -constexpr uint8_t SOCK_ESTABLISHED = 0x17; -constexpr uint8_t SOCK_FIN_WAIT = 0x18; -constexpr uint8_t SOCK_TIME_WAIT = 0x1B; -constexpr uint8_t SOCK_CLOSE_WAIT = 0x1C; -constexpr uint8_t SOCK_LAST_ACK = 0x1D; -constexpr uint8_t SOCK_UDP = 0x22; -constexpr uint8_t SOCK_IPRAW4 = 0x32; -constexpr uint8_t SOCK_IPRAW = SOCK_IPRAW4; -constexpr uint8_t SOCK_IPRAW6 = 0x33; -constexpr uint8_t SOCK_MACRAW = 0x42; -constexpr uint8_t Sn_ESR_TCPM = 1 << 2; -constexpr uint8_t Sn_ESR_TCPM_IPV4 = 0 << 2; -constexpr uint8_t Sn_ESR_TCPM_IPV6 = 1 << 2; -constexpr uint8_t Sn_ESR_TCPOP = 1 << 1; -constexpr uint8_t Sn_ESR_TCPOP_SVR = 0 << 1; -constexpr uint8_t Sn_ESR_TCPOP_CLT = 1 << 1; -constexpr uint8_t Sn_ESR_IP6T = 1 << 0; -constexpr uint8_t Sn_ESR_IP6T_LLA = 0 << 0; -constexpr uint8_t Sn_ESR_IP6T_GUA = 1 << 0; -constexpr uint8_t Sn_MR2_DHAM = 1 << 1; -constexpr uint8_t Sn_MR2_DHAM_AUTO = 0 << 1; -constexpr uint8_t Sn_MR2_DHAM_MANUAL = 1 << 1; -constexpr uint8_t Sn_MR2_FARP = 1 << 0; -constexpr uint8_t PHYRAR_BMCR = 0x00; -constexpr uint8_t PHYRAR_BMSR = 0x01; -constexpr uint16_t BMCR_RST = 1 << 15; -constexpr uint16_t BMCR_LB = 1 << 14; -constexpr uint16_t BMCR_SPD = 1 << 13; -constexpr uint16_t BMCR_ANE = 1 << 12; -constexpr uint16_t BMCR_PWDN = 1 << 11; -constexpr uint16_t BMCR_ISOL = 1 << 10; -constexpr uint16_t BMCR_REAN = 1 << 9; -constexpr uint16_t BMCR_DPX = 1 << 8; -constexpr uint16_t BMCR_COLT = 1 << 7; -constexpr uint16_t BMSR_100_T4 = 1 << 15; -constexpr uint16_t BMSR_100_FDX = 1 << 14; -constexpr uint16_t BMSR_100_HDX = 1 << 13; -constexpr uint16_t BMSR_10_FDX = 1 << 12; -constexpr uint16_t BMSR_10_HDX = 1 << 11; -constexpr uint16_t BMSR_MF_SUP = 1 << 6; -constexpr uint16_t BMSR_AN_COMP = 1 << 5; -constexpr uint16_t BMSR_REMOTE_FAULT = 1 << 4; -constexpr uint16_t BMSR_AN_ABILITY = 1 << 3; -constexpr uint16_t BMSR_LINK_STATUS = 1 << 2; -constexpr uint16_t BMSR_JABBER_DETECT = 1 << 1; -constexpr uint16_t BMSR_EXT_CAPA = 1 << 0; +constexpr uint8_t SYS_CHIP_LOCK = (1 << 2); +constexpr uint8_t SYS_NET_LOCK = (1 << 1); +constexpr uint8_t SYS_PHY_LOCK = (1 << 0); -void wizchip_cris_enter(); -void wizchip_cris_exit(); -inline void WIZCHIP_CRITICAL_ENTER() { wizchip_cris_enter(); } -inline void WIZCHIP_CRITICAL_EXIT() { wizchip_cris_exit(); } +constexpr uint8_t PHY_MODE_MANUAL = 0; +constexpr uint8_t PHY_MODE_AUTONEGO = 1; +constexpr uint8_t PHY_MODE_TE = 2; +constexpr uint8_t PHY_CONFBY_HW = 0; +constexpr uint8_t PHY_CONFBY_SW = 1; +constexpr uint8_t PHY_SPEED_10 = 0; +constexpr uint8_t PHY_SPEED_100 = 1; +constexpr uint8_t PHY_DUPLEX_HALF = 0; +constexpr uint8_t PHY_DUPLEX_FULL = 1; +constexpr uint8_t PHY_LINK_OFF = 0; +constexpr uint8_t PHY_LINK_ON = 1; +constexpr uint8_t PHY_POWER_NORM = 0; +constexpr uint8_t PHY_POWER_DOWN = 1; -uint8_t WIZCHIP_READ(uint32_t AddrSel); -void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb); -void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); -void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); +struct wiz_PhyConf { + uint8_t by; + uint8_t mode; + uint8_t speed; + uint8_t duplex; +}; -inline uint8_t getRTL() { return WIZCHIP_READ(_RTL_); } -inline uint16_t getCIDR() { return (((uint16_t)WIZCHIP_READ(_CIDR_) | (((WIZCHIP_READ(_RTL_)) & 0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_, 1)); } -inline uint16_t getVER() { return (((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_, 1)); } -inline uint8_t getSYSR() { return WIZCHIP_READ(_SYSR_); } -inline uint8_t getSYCR0() { return WIZCHIP_READ(_SYCR0_); } -inline void setSYCR0(uint8_t v) { WIZCHIP_WRITE(_SYCR0_, v); } -inline uint8_t getSYCR1() { return WIZCHIP_READ(_SYCR1_); } -inline void setSYCR1(uint8_t v) { WIZCHIP_WRITE(_SYCR1_, v); } -inline uint16_t getTCNTR() { return (((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_, 1)); } -inline void setTCNTRCLR(uint8_t v) { WIZCHIP_WRITE(_TCNTRCLR_, v); } -inline uint8_t getIR() { return WIZCHIP_READ(_IR_); } -inline uint8_t getSIR() { return WIZCHIP_READ(_SIR_); } -inline uint8_t getSLIR() { return WIZCHIP_READ(_SLIR_); } -inline void setIMR(uint8_t v) { WIZCHIP_WRITE(_IMR_, v); } -inline uint8_t getIMR() { return WIZCHIP_READ(_IMR_); } -inline void setIRCLR(uint8_t v) { WIZCHIP_WRITE(_IRCLR_, v); } -inline void setIR(uint8_t v) { setIRCLR(v); } -inline void setSIMR(uint8_t v) { WIZCHIP_WRITE(_SIMR_, v); } -inline uint8_t getSIMR() { return WIZCHIP_READ(_SIMR_); } -inline void setSLIMR(uint8_t v) { WIZCHIP_WRITE(_SLIMR_, v); } -inline uint8_t getSLIMR() { return WIZCHIP_READ(_SLIMR_); } -inline void setSLIRCLR(uint8_t v) { WIZCHIP_WRITE(_SLIRCLR_, v); } -inline void setSLIR(uint8_t v) { setSLIRCLR(v); } -inline void setSLPSR(uint8_t v) { WIZCHIP_WRITE(_SLPSR_, v); } -inline uint8_t getSLPSR() { return WIZCHIP_READ(_SLPSR_); } -inline void setSLCR(uint8_t v) { WIZCHIP_WRITE(_SLCR_, v); } -inline uint8_t getSLCR() { return WIZCHIP_READ(_SLCR_); } -inline uint8_t getPHYSR() { return WIZCHIP_READ(_PHYSR_); } -inline void setPHYRAR(uint8_t v) { WIZCHIP_WRITE(_PHYRAR_, v); } -inline uint8_t getPHYRAR() { return WIZCHIP_READ(_PHYRAR_); } -inline void setPHYDIR(uint16_t v) { - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_, 1), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(_PHYDIR_, (uint8_t)v); -} -inline uint16_t getPHYDOR() { return (((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_, 1))) << 8) + WIZCHIP_READ(_PHYDOR_); } -inline void setPHYACR(uint8_t v) { WIZCHIP_WRITE(_PHYACR_, v); } -inline uint8_t getPHYACR() { return WIZCHIP_READ(_PHYACR_); } -inline void setPHYDIVR(uint8_t v) { WIZCHIP_WRITE(_PHYDIVR_, v); } -inline uint8_t getPHYDIVR() { return WIZCHIP_READ(_PHYDIVR_); } -inline void setPHYCR0(uint8_t v) { WIZCHIP_WRITE(_PHYCR0_, v); } -inline void setPHYCR1(uint8_t v) { WIZCHIP_WRITE(_PHYCR1_, v); } -inline uint8_t getPHYCR1() { return WIZCHIP_READ(_PHYCR1_); } -inline void setNET4MR(uint8_t v) { WIZCHIP_WRITE(_NET4MR_, v); } -inline void setNET6MR(uint8_t v) { WIZCHIP_WRITE(_NET6MR_, v); } -inline void setNETMR(uint8_t v) { WIZCHIP_WRITE(_NETMR_, v); } -inline void setNETMR2(uint8_t v) { WIZCHIP_WRITE(_NETMR2_, v); } -inline uint8_t getNET4MR() { return WIZCHIP_READ(_NET4MR_); } -inline uint8_t getNET6MR() { return WIZCHIP_READ(_NET6MR_); } -inline uint8_t getNETMR() { return WIZCHIP_READ(_NETMR_); } -inline uint8_t getNETMR2() { return WIZCHIP_READ(_NETMR2_); } -inline void setPTMR(uint8_t v) { WIZCHIP_WRITE(_PTMR_, v); } -inline uint8_t getPTMR() { return WIZCHIP_READ(_PTMR_); } -inline void setPMNR(uint8_t v) { WIZCHIP_WRITE(_PMNR_, v); } -inline uint8_t getPMNR() { return WIZCHIP_READ(_PMNR_); } -inline void setPHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_PHAR_, v, 6); } -inline void getPHAR(uint8_t* v) { WIZCHIP_READ_BUF(_PHAR_, v, 6); } -inline void setPSIDR(uint16_t v) { - WIZCHIP_WRITE(_PSIDR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_, 1), (uint8_t)v); -} -inline uint16_t getPSIDR() { return (((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_, 1)); } -inline void setPMRUR(uint16_t v) { - WIZCHIP_WRITE(_PMRUR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_, 1), (uint8_t)v); -} -inline uint16_t getPMRUR() { return (((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_, 1)); } -inline void setSHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SHAR_, v, 6); } -inline void getSHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SHAR_, v, 6); } -inline void setGAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GAR_, v, 4); } -inline void getGAR(uint8_t* v) { WIZCHIP_READ_BUF(_GAR_, v, 4); } -inline void setGA4R(uint8_t* v) { setGAR(v); } -inline void getGA4R(uint8_t* v) { getGAR(v); } -inline void setSUBR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUBR_, v, 4); } -inline void getSUBR(uint8_t* v) { WIZCHIP_READ_BUF(_SUBR_, v, 4); } -inline void setSUB4R(uint8_t* v) { setSUBR(v); } -inline void getSUB4R(uint8_t* v) { getSUBR(v); } -inline void setSIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SIPR_, v, 4); } -inline void getSIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SIPR_, v, 4); } -inline void setLLAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_LLAR_, v, 16); } -inline void getLLAR(uint8_t* v) { WIZCHIP_READ_BUF(_LLAR_, v, 16); } -inline void setGUAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GUAR_, v, 16); } -inline void getGUAR(uint8_t* v) { WIZCHIP_READ_BUF(_GUAR_, v, 16); } -inline void setSUB6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUB6R_, v, 16); } -inline void getSUB6R(uint8_t* v) { WIZCHIP_READ_BUF(_SUB6R_, v, 16); } -inline void setGA6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_GA6R_, v, 16); } -inline void getGA6R(uint8_t* v) { WIZCHIP_READ_BUF(_GA6R_, v, 16); } -inline void setSLDIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIPR_, v, 4); } -inline void setSLDIP4R(uint8_t* v) { setSLDIPR(v); } -inline void getSLDIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIPR_, v, 4); } -inline void getSLDIP4R(uint8_t* v) { getSLDIPR(v); } -inline void setSLDIP6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIP6R_, v, 16); } -inline void getSLDIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIP6R_, v, 16); } -inline void getSLDHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDHAR_, v, 6); } -inline void setPINGIDR(uint16_t v) { - WIZCHIP_WRITE(_PINGIDR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_, 1), (uint8_t)v); -} -inline uint16_t getPINGIDR() { return ((uint16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_, 1)); } -inline void setPINGSEQR(uint16_t v) { - WIZCHIP_WRITE(_PINGSEQR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1), (uint8_t)v); -} -inline uint16_t getPINGSEQR() { return ((uint16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1)); } -inline void getUIPR(uint8_t* v) { WIZCHIP_READ_BUF(_UIPR_, v, 4); } -inline void getUIP4R(uint8_t* v) { getUIPR(v); } -inline uint16_t getUPORTR() { return (((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_, 1)); } -inline uint16_t getUPORT4R() { return getUPORTR(); } -inline void getUIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_UIP6R_, v, 16); } -inline uint16_t getUPORT6R() { return (((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_, 1)); } -inline void setINTPTMR(uint16_t v) { - WIZCHIP_WRITE(_INTPTMR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_, 1), (uint8_t)v); -} -inline uint16_t getINTPTMR() { return (((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_, 1)); } -inline uint8_t getPLR() { return WIZCHIP_READ(_PLR_); } -inline uint8_t getPFR() { return WIZCHIP_READ(_PFR_); } -inline uint32_t getVLTR() { - return (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 1))) << 16) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 2))) << 8) + - ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 3))); -} -inline uint32_t getPLTR() { - return (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 1))) << 16) + - (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 2))) << 8) + - ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 3))); -} -inline void getPAR(uint8_t* v) { WIZCHIP_READ_BUF(_PAR_, v, 16); } -inline void setICMP6BLKR(uint8_t v) { WIZCHIP_WRITE(_ICMP6BLKR_, v); } -inline uint8_t getICMP6BLKR() { return WIZCHIP_READ(_ICMP6BLKR_); } -inline void setCHPLCKR(uint8_t v) { WIZCHIP_WRITE(_CHPLCKR_, v); } -inline uint8_t getCHPLCKR() { return (getSYSR() & SYSR_CHPL) >> 7; } -inline void CHIPLOCK() { setCHPLCKR(0xFF); } -inline void CHIPUNLOCK() { setCHPLCKR(0xCE); } -inline void setNETLCKR(uint8_t v) { WIZCHIP_WRITE(_NETLCKR_, v); } -inline uint8_t getNETLCKR() { return (getSYSR() & SYSR_NETL) >> 6; } -inline void NETLOCK() { setNETLCKR(0xC5); } -inline void NETUNLOCK() { setNETLCKR(0x3A); } -inline void setPHYLCKR(uint8_t v) { WIZCHIP_WRITE(_PHYLCKR_, v); } -inline uint8_t getPHYLCKR() { return (getSYSR() & SYSR_PHYL) >> 5; } -inline void PHYLOCK() { setPHYLCKR(0xFF); } -inline void PHYUNLOCK() { setPHYLCKR(0x53); } -inline void setRTR(uint16_t v) { - WIZCHIP_WRITE(_RTR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_, 1), (uint8_t)v); -} -inline uint16_t getRTR() { return (((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); } -inline void setRCR(uint8_t v) { WIZCHIP_WRITE(_RCR_, v); } -inline uint8_t getRCR() { return WIZCHIP_READ(_RCR_); } -inline void setSLRTR(uint16_t v) { - WIZCHIP_WRITE(_SLRTR_, (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_, 1), (uint8_t)v); -} -inline uint16_t getSLRTR() { return (((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_, 1)); } -inline void setSLRCR(uint8_t v) { WIZCHIP_WRITE(_SLRCR_, v); } -inline uint8_t getSLRCR() { return WIZCHIP_READ(_SLRCR_); } -inline void setSLHOPR(uint8_t v) { WIZCHIP_WRITE(_SLHOPR_, v); } -inline uint8_t getSLHOPR() { return WIZCHIP_READ(_SLHOPR_); } +enum ipconf_mode : uint8_t { + NETINFO_NONE = 0x00, NETINFO_STATIC_V4 = 0x01, NETINFO_STATIC_V6 = 0x02, + NETINFO_STATIC_ALL = 0x03, NETINFO_SLAAC_V6 = 0x04, + NETINFO_DHCP_V4 = 0x10, NETINFO_DHCP_V6 = 0x20, NETINFO_DHCP_ALL = 0x30 +}; -inline void setSn_MR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR_(sn), v); } -inline uint8_t getSn_MR(uint8_t sn) { return WIZCHIP_READ(_Sn_MR_(sn)); } -inline void setSn_PSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PSR_(sn), v); } -inline uint8_t getSn_PSR(uint8_t sn) { return WIZCHIP_READ(_Sn_PSR_(sn)); } -inline void setSn_CR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_CR_(sn), v); } -inline uint8_t getSn_CR(uint8_t sn) { return WIZCHIP_READ(_Sn_CR_(sn)); } -inline uint8_t getSn_IR(uint8_t sn) { return WIZCHIP_READ(_Sn_IR_(sn)); } -inline void setSn_IMR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IMR_(sn), v); } -inline uint8_t getSn_IMR(uint8_t sn) { return WIZCHIP_READ(_Sn_IMR_(sn)); } -inline void setSn_IRCLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IRCLR_(sn), v); } -inline void setSn_IR(uint8_t sn, uint8_t v) { setSn_IRCLR(sn, v); } -inline uint8_t getSn_SR(uint8_t sn) { return WIZCHIP_READ(_Sn_SR_(sn)); } -inline uint8_t getSn_ESR(uint8_t sn) { return WIZCHIP_READ(_Sn_ESR_(sn)); } -inline void setSn_PNR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PNR_(sn), v); } -inline void setSn_NHR(uint8_t sn, uint8_t v) { setSn_PNR(sn, v); } -inline uint8_t getSn_PNR(uint8_t sn) { return WIZCHIP_READ(_Sn_PNR_(sn)); } -inline uint8_t getSn_NHR(uint8_t sn) { return getSn_PNR(sn); } -inline void setSn_TOSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TOSR_(sn), v); } -inline uint8_t getSn_TOSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TOSR_(sn)); } -inline uint8_t getSn_TOS(uint8_t sn) { return getSn_TOSR(sn); } -inline void setSn_TOS(uint8_t sn, uint8_t v) { setSn_TOSR(sn, v); } -inline void setSn_TTLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TTLR_(sn), v); } -inline uint8_t getSn_TTLR(uint8_t sn) { return WIZCHIP_READ(_Sn_TTLR_(sn)); } -inline void setSn_TTL(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } -inline uint8_t getSn_TTL(uint8_t sn) { return getSn_TTLR(sn); } -inline void setSn_HOPR(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } -inline uint8_t getSn_HOPR(uint8_t sn) { return getSn_TTLR(sn); } -inline void setSn_FRGR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_FRGR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1)); } -inline void setSn_MSSR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_MSSR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1)); } -inline void setSn_PORTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_PORTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1)); } -inline void setSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn), v, 6); } -inline void getSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DHAR_(sn), v, 6); } -inline void setSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn), v, 4); } -inline void getSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIPR_(sn), v, 4); } -inline void setSn_DIP4R(uint8_t sn, uint8_t* v) { setSn_DIPR(sn, v); } -inline void getSn_DIP4R(uint8_t sn, uint8_t* v) { getSn_DIPR(sn, v); } -inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn), v, 16); } -inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIP6R_(sn), v, 16); } -inline void setSn_DPORTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_DPORTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1)); } -inline uint16_t getSn_DPORT(uint8_t sn) { return getSn_DPORTR(sn); } -inline void setSn_DPORT(uint8_t sn, uint16_t v) { setSn_DPORTR(sn, v); } -inline void setSn_MR2(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR2_(sn), v); } -inline uint8_t getSn_MR2(uint8_t sn) { return WIZCHIP_READ(_Sn_MR2_(sn)); } -inline void setSn_RTR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_RTR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1)); } -inline void setSn_RCR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RCR_(sn), v); } -inline uint8_t getSn_RCR(uint8_t sn) { return WIZCHIP_READ(_Sn_RCR_(sn)); } -inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_KPALVTR_(sn), v); } -inline uint8_t getSn_KPALVTR(uint8_t sn) { return WIZCHIP_READ(_Sn_KPALVTR_(sn)); } -inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TX_BSR_(sn), v); } -inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_TX_BSR(sn, v); } -inline uint8_t getSn_TX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TX_BSR_(sn)); } -inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) { return getSn_TX_BSR(sn); } -inline uint16_t getSn_TxMAX(uint8_t sn) { return getSn_TX_BSR(sn) << 10; } +enum dhcp_mode : uint8_t { NETINFO_STATIC = 1, NETINFO_DHCP }; -uint16_t getSn_TX_FSR(uint8_t sn); +struct wiz_NetInfo { + uint8_t mac[6]; + uint8_t ip[4]; + uint8_t sn[4]; + uint8_t gw[4]; + uint8_t lla[16]; + uint8_t gua[16]; + uint8_t sn6[16]; + uint8_t gw6[16]; + uint8_t dns[4]; + uint8_t dns6[16]; + ipconf_mode ipmode; + dhcp_mode dhcp; +}; -inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn), 1)); } -inline void setSn_TX_WR(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1)); } -inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RX_BSR_(sn), v); } -inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_RX_BSR(sn, v); } -inline uint8_t getSn_RX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_RX_BSR_(sn)); } -inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) { return getSn_RX_BSR(sn); } -inline uint16_t getSn_RxMAX(uint8_t sn) { return getSn_RX_BSR(sn) << 10; } +enum netmode_type : uint32_t { + NM_IPB_V4 = (1 << 0), NM_IPB_V6 = (1 << 1), NM_WOL = (1 << 2), + NM_PB6_MULTI = (1 << 4), NM_PB6_ALLNODE = (1 << 5), NM_MR_MASK = 0x37, + NM_PPPoE = (1 << 8), NM_DHA_SELECT = (1 << 15), NM_MR2_MASK = (0x09 << 8), + NM_PB4_ALL = (1 << 16), NM_TRSTB_V4 = (1 << 17), NM_PARP_V4 = (1 << 18), + NM_UNRB_V4 = (1 << 19), NM_NET4_MASK = (0x0F << 16), + NM_PB6_ALL = (1 << 24), NM_TRSTB_V6 = (1 << 25), NM_PARP_V6 = (1 << 26), + NM_UNRB_V6 = (1 << 27), NM_NET6_MASK = (0x0F << 24), + NM_MASK_ALL = 0x0F0F0937 +}; -uint16_t getSn_RX_RSR(uint8_t s); +struct wiz_NetTimeout { + uint8_t s_retry_cnt; + uint16_t s_time_100us; + uint8_t sl_retry_cnt; + uint16_t sl_time_100us; +}; -inline void setSn_RX_RD(uint8_t sn, uint16_t v) { - WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)(v >> 8)); - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1), (uint8_t)v); -} -inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1)); } -inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn), 1)); } -void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len); -void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len); -void wiz_recv_ignore(uint8_t sn, uint16_t len); -void wiz_delay_ms(uint32_t ms); +struct wiz_IPAddress { + uint8_t ip[16]; + uint8_t len; +}; -void wiz_mdio_write(uint8_t phyregaddr, uint16_t var); -uint16_t wiz_mdio_read(uint8_t phyregaddr); +struct wiz_Prefix { + uint8_t len; + uint8_t flag; + uint32_t valid_lifetime; + uint32_t preferred_lifetime; + uint8_t prefix[16]; +}; +struct wiz_ARP { + wiz_IPAddress destinfo; + uint8_t dha[6]; +}; + +struct wiz_PING { + uint16_t id; + uint16_t seq; + wiz_IPAddress destinfo; +}; + +int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg); +int8_t ctlnetwork(ctlnetwork_type cntype, void* arg); +int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg); + +void wizchip_sw_reset(); +int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize); +void wizchip_clrinterrupt(intr_kind intr); +intr_kind wizchip_getinterrupt(); +void wizchip_setinterruptmask(intr_kind intr); +intr_kind wizchip_getinterruptmask(); + +int8_t wizphy_getphylink(); +int8_t wizphy_getphypmode(); +void wizphy_reset(); +void wizphy_setphyconf(wiz_PhyConf* phyconf); +void wizphy_getphyconf(wiz_PhyConf* phyconf); +void wizphy_getphystat(wiz_PhyConf* phyconf); +void wizphy_setphypmode(uint8_t pmode); + +void wizchip_setnetinfo(wiz_NetInfo* pnetinfo); +void wizchip_getnetinfo(wiz_NetInfo* pnetinfo); +void wizchip_setnetmode(netmode_type netmode); +netmode_type wizchip_getnetmode(); +void wizchip_settimeout(wiz_NetTimeout* nettime); +void wizchip_gettimeout(wiz_NetTimeout* nettime); + +int8_t wizchip_arp(wiz_ARP* arp); +int8_t wizchip_ping(wiz_PING* ping); +int8_t wizchip_dad(uint8_t* ipv6); +int8_t wizchip_slaac(wiz_Prefix* prefix); +int8_t wizchip_unsolicited(); +int8_t wizchip_getprefix(wiz_Prefix* prefix); + +void wizchip_spi_initialize(); +void wizchip_cris_initialize(); +void wizchip_reset(); +void wizchip_initialize(); +bool wizchip_check(); +void network_initialize(wiz_NetInfo net_info); + +using SOCKET = uint8_t; +using iodata_t = uint8_t; +using datasize_t = int16_t; + +constexpr int16_t SOCK_OK = 1; +constexpr int16_t SOCK_BUSY = 0; +constexpr int16_t SOCK_FATAL = -1000; +constexpr int16_t SOCK_ERROR = 0; +constexpr int16_t SOCKERR_SOCKNUM = SOCK_ERROR - 1; +constexpr int16_t SOCKERR_SOCKOPT = SOCK_ERROR - 2; +constexpr int16_t SOCKERR_SOCKINIT = SOCK_ERROR - 3; +constexpr int16_t SOCKERR_SOCKCLOSED = SOCK_ERROR - 4; +constexpr int16_t SOCKERR_SOCKMODE = SOCK_ERROR - 5; +constexpr int16_t SOCKERR_SOCKFLAG = SOCK_ERROR - 6; +constexpr int16_t SOCKERR_SOCKSTATUS = SOCK_ERROR - 7; +constexpr int16_t SOCKERR_ARG = SOCK_ERROR - 10; +constexpr int16_t SOCKERR_PORTZERO = SOCK_ERROR - 11; +constexpr int16_t SOCKERR_IPINVALID = SOCK_ERROR - 12; +constexpr int16_t SOCKERR_TIMEOUT = SOCK_ERROR - 13; +constexpr int16_t SOCKERR_DATALEN = SOCK_ERROR - 14; +constexpr int16_t SOCKERR_BUFFER = SOCK_ERROR - 15; +constexpr int16_t SOCKFATAL_PACKLEN = SOCK_FATAL - 1; + +constexpr uint8_t SF_MULTI_ENABLE = 1 << 7; +constexpr uint8_t SF_ETHER_OWN = 1 << 7; +constexpr uint8_t SF_BROAD_BLOCK = 1 << 6; +constexpr uint8_t SF_TCP_FPSH = 1 << 6; +constexpr uint8_t SF_TCP_NODELAY = 1 << 5; +constexpr uint8_t SF_IGMP_VER2 = 1 << 5; +constexpr uint8_t SF_SOLICIT_BLOCK = 1 << 5; +constexpr uint8_t SF_ETHER_MULTI4B = 1 << 5; +constexpr uint8_t SF_UNI_BLOCK = 1 << 4; +constexpr uint8_t SF_ETHER_MULIT6B = 1 << 4; +constexpr uint8_t SF_FORCE_ARP = 1 << 0; +constexpr uint8_t SF_DHA_MANUAL = 1 << 1; +constexpr uint8_t SF_IO_NONBLOCK = 1 << 3; + +constexpr uint8_t PACK_IPv6 = 1 << 7; +constexpr uint8_t PACK_IPV6_ALLNODE = PACK_IPv6 | (1 << 6); +constexpr uint8_t PACK_IPV6_MULTI = PACK_IPv6 | (1 << 5); +constexpr uint8_t PACK_IPV6_LLA = PACK_IPv6 | (1 << 4); +constexpr uint8_t PACK_COMPLETED = 1 << 3; +constexpr uint8_t PACK_REMAINED = 1 << 2; +constexpr uint8_t PACK_FIRST = 1 << 1; +constexpr uint8_t PACK_NONE = 0x00; + +constexpr uint8_t SRCV6_PREFER_AUTO = 0x00; +constexpr uint8_t SRCV6_PREFER_LLA = 0x02; +constexpr uint8_t SRCV6_PREFER_GUA = 0x03; + +constexpr uint8_t TCPSOCK_MODE = 1 << 2; +constexpr uint8_t TCPSOCK_OP = 1 << 1; +constexpr uint8_t TCPSOCK_SIP = 1 << 0; + +constexpr uint8_t SOCK_IO_BLOCK = 0; +constexpr uint8_t SOCK_IO_NONBLOCK = 1; + +int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag); +int8_t close(uint8_t sn); +int8_t listen(uint8_t sn); +int8_t disconnect(uint8_t sn); +int32_t send(uint8_t sn, uint8_t * buf, uint16_t len); +int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len); + +typedef enum { + SIK_CONNECTED = (1 << 0), + SIK_DISCONNECTED = (1 << 1), + SIK_RECEIVED = (1 << 2), + SIK_TIMEOUT = (1 << 3), + SIK_SENT = (1 << 4), + SIK_ALL = 0x1F +} sockint_kind; + +typedef enum { + CS_SET_IOMODE, + CS_GET_IOMODE, + CS_GET_MAXTXBUF, + CS_GET_MAXRXBUF, + CS_CLR_INTERRUPT, + CS_GET_INTERRUPT, + CS_SET_PREFER, + CS_GET_PREFER, + CS_SET_INTMASK, + CS_GET_INTMASK +} ctlsock_type; + +typedef enum { + SO_FLAG, + SO_TTL, + SO_TOS, + SO_MSS, + SO_DESTIP, + SO_DESTPORT, + SO_KEEPALIVESEND, + SO_KEEPALIVEAUTO, + SO_SENDBUF, + SO_RECVBUF, + SO_STATUS, + SO_EXTSTATUS, + SO_MODE, + SO_REMAINSIZE, + SO_PACKINFO +} sockopt_type; + +int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg); +int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg); +int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg); +int16_t peeksockmsg(uint8_t sn, uint8_t* submsg, uint16_t subsize); + +int8_t connect(uint8_t sn, uint8_t* addr, uint16_t port, uint8_t addrlen); +int32_t sendto(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t port, uint8_t addrlen); +int32_t recvfrom(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t* port, uint8_t* addrlen); diff --git a/w6300/w6300_internal.h b/w6300/w6300_internal.h new file mode 100644 index 0000000..6443a68 --- /dev/null +++ b/w6300/w6300_internal.h @@ -0,0 +1,589 @@ +#pragma once +#include "w6300.h" + +constexpr int _WIZCHIP_ = 6300; +constexpr uint8_t _WIZCHIP_QSPI_MODE_ = 0x02 << 6; +constexpr int _WIZCHIP_SOCK_NUM_ = WIZCHIP_SOCK_NUM; + +constexpr uint8_t PIN_INT = 15; +constexpr uint8_t PIN_CS = 16; +constexpr uint8_t PIO_SPI_SCK_PIN = 17; +constexpr uint8_t PIO_SPI_DATA_IO0_PIN = 18; +constexpr uint8_t PIO_SPI_DATA_IO1_PIN = 19; +constexpr uint8_t PIO_SPI_DATA_IO2_PIN = 20; +constexpr uint8_t PIO_SPI_DATA_IO3_PIN = 21; +constexpr uint8_t PIN_RST = 22; + +constexpr uint16_t WIZNET_SPI_CLKDIV_MAJOR_DEFAULT = 2; +constexpr uint8_t WIZNET_SPI_CLKDIV_MINOR_DEFAULT = 0; + +constexpr uint16_t _PHY_IO_MODE_PHYCR_ = 0x0000; +constexpr uint16_t _PHY_IO_MODE_MII_ = 0x0010; +constexpr uint16_t _PHY_IO_MODE_ = _PHY_IO_MODE_MII_; + +constexpr uint8_t W6300_SPI_READ = (0x00 << 5); +constexpr uint8_t W6300_SPI_WRITE = (0x01 << 5); + +constexpr uint32_t WIZCHIP_CREG_BLOCK = 0x00; +constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; } +constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; } +constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; } + +constexpr uint32_t WIZCHIP_OFFSET_INC(uint32_t addr, uint32_t n) { return addr + (n << 8); } + +constexpr uint32_t _CIDR_ = (0x0000 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _RTL_ = (0x0004 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _VER_ = (0x0002 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SYSR_ = (0x2000 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SYCR0_ = (0x2004 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SYCR1_ = WIZCHIP_OFFSET_INC(_SYCR0_, 1); +constexpr uint32_t _TCNTR_ = (0x2016 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _TCNTRCLR_ = (0x2020 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _IR_ = (0x2100 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SIR_ = (0x2101 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLIR_ = (0x2102 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _IMR_ = (0x2104 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _IRCLR_ = (0x2108 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SIMR_ = (0x2114 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLIMR_ = (0x2124 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLIRCLR_ = (0x2128 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLPSR_ = (0x212C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLCR_ = (0x2130 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYSR_ = (0x3000 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYRAR_ = (0x3008 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYDIR_ = (0x300C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYDOR_ = (0x3010 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYACR_ = (0x3014 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYDIVR_ = (0x3018 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYCR0_ = (0x301C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYCR1_ = WIZCHIP_OFFSET_INC(_PHYCR0_, 1); +constexpr uint32_t _NET4MR_ = (0x4000 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _NET6MR_ = (0x4004 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _NETMR_ = (0x4008 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _NETMR2_ = (0x4009 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PTMR_ = (0x4100 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PMNR_ = (0x4104 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHAR_ = (0x4108 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PSIDR_ = (0x4110 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PMRUR_ = (0x4114 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SHAR_ = (0x4120 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _GAR_ = (0x4130 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _GA4R_ = _GAR_; +constexpr uint32_t _SUBR_ = (0x4134 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SUB4R_ = _SUBR_; +constexpr uint32_t _SIPR_ = (0x4138 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SIP4R_ = _SIPR_; +constexpr uint32_t _LLAR_ = (0x4140 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _GUAR_ = (0x4150 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SUB6R_ = (0x4160 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _GA6R_ = (0x4170 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLDIP6R_ = (0x4180 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLDIPR_ = (0x418C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLDIP4R_ = _SLDIPR_; +constexpr uint32_t _SLDHAR_ = (0x4190 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PINGIDR_ = (0x4198 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PINGSEQR_ = (0x419C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UIPR_ = (0x41A0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UIP4R_ = _UIPR_; +constexpr uint32_t _UPORTR_ = (0x41A4 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UPORT4R_ = _UPORTR_; +constexpr uint32_t _UIP6R_ = (0x41B0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _UPORT6R_ = (0x41C0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _INTPTMR_ = (0x41C5 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PLR_ = (0x41D0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PFR_ = (0x41D4 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _VLTR_ = (0x41D8 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PLTR_ = (0x41DC << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PAR_ = (0x41E0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _CHPLCKR_ = (0x41F4 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _NETLCKR_ = (0x41F5 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _PHYLCKR_ = (0x41F6 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _RTR_ = (0x4200 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _RCR_ = (0x4204 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLRTR_ = (0x4208 << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLRCR_ = (0x420C << 8) + WIZCHIP_CREG_BLOCK; +constexpr uint32_t _SLHOPR_ = (0x420F << 8) + WIZCHIP_CREG_BLOCK; + +constexpr uint32_t _Sn_MR_(uint8_t n) { return (0x0000 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_PSR_(uint8_t n) { return (0x0004 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_CR_(uint8_t n) { return (0x0010 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_IR_(uint8_t n) { return (0x0020 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_IMR_(uint8_t n) { return (0x0024 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_IRCLR_(uint8_t n) { return (0x0028 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_SR_(uint8_t n) { return (0x0030 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_ESR_(uint8_t n) { return (0x0031 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_PNR_(uint8_t n) { return (0x0100 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_NHR_(uint8_t n) { return _Sn_PNR_(n); } +constexpr uint32_t _Sn_TOSR_(uint8_t n) { return (0x0104 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TTLR_(uint8_t n) { return (0x0108 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_HOPR_(uint8_t n) { return _Sn_TTLR_(n); } +constexpr uint32_t _Sn_FRGR_(uint8_t n) { return (0x010C << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_MSSR_(uint8_t n) { return (0x0110 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_PORTR_(uint8_t n) { return (0x0114 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_DHAR_(uint8_t n) { return (0x0118 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_DIPR_(uint8_t n) { return (0x0120 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_DIP4R_(uint8_t n) { return _Sn_DIPR_(n); } +constexpr uint32_t _Sn_DIP6R_(uint8_t n) { return (0x0130 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_DPORTR_(uint8_t n) { return (0x0140 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_MR2_(uint8_t n) { return (0x0144 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RTR_(uint8_t n) { return (0x0180 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RCR_(uint8_t n) { return (0x0184 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_BSR_(uint8_t n) { return (0x0200 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_FSR_(uint8_t n) { return (0x0204 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_RD_(uint8_t n) { return (0x0208 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_TX_WR_(uint8_t n) { return (0x020C << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_BSR_(uint8_t n) { return (0x0220 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_RSR_(uint8_t n) { return (0x0224 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_RD_(uint8_t n) { return (0x0228 << 8) + WIZCHIP_SREG_BLOCK(n); } +constexpr uint32_t _Sn_RX_WR_(uint8_t n) { return (0x022C << 8) + WIZCHIP_SREG_BLOCK(n); } + +constexpr uint8_t SYSR_CHPL = 1 << 7; +constexpr uint8_t SYSR_NETL = 1 << 6; +constexpr uint8_t SYSR_PHYL = 1 << 5; +constexpr uint8_t SYSR_IND = 1 << 5; +constexpr uint8_t SYSR_SPI = 1 << 0; +constexpr uint8_t SYCR0_RST = 0x00; +constexpr uint8_t SYCR1_IEN = 1 << 7; +constexpr uint8_t SYCR1_CLKSEL = 1 << 0; +constexpr uint8_t SYCR1_CLKSEL_25M = 1; +constexpr uint8_t SYCR1_CLKSEL_100M = 0; +constexpr uint8_t IR_WOL = 1 << 7; +constexpr uint8_t IR_UNR6 = 1 << 4; +constexpr uint8_t IR_IPCONF = 1 << 2; +constexpr uint8_t IR_UNR4 = 1 << 1; +constexpr uint8_t IR_PTERM = 1 << 0; +constexpr uint8_t SIR_INT(uint8_t n) { return 1 << n; } +constexpr uint8_t SLIR_TOUT = 1 << 7; +constexpr uint8_t SLIR_ARP4 = 1 << 6; +constexpr uint8_t SLIR_PING4 = 1 << 5; +constexpr uint8_t SLIR_ARP6 = 1 << 4; +constexpr uint8_t SLIR_PING6 = 1 << 3; +constexpr uint8_t SLIR_NS = 1 << 2; +constexpr uint8_t SLIR_RS = 1 << 1; +constexpr uint8_t SLIR_RA = 1 << 0; +constexpr uint8_t PSR_AUTO = 0x00; +constexpr uint8_t PSR_LLA = 0x02; +constexpr uint8_t PSR_GUA = 0x03; +constexpr uint8_t SLCR_ARP4 = 1 << 6; +constexpr uint8_t SLCR_PING4 = 1 << 5; +constexpr uint8_t SLCR_ARP6 = 1 << 4; +constexpr uint8_t SLCR_PING6 = 1 << 3; +constexpr uint8_t SLCR_NS = 1 << 2; +constexpr uint8_t SLCR_RS = 1 << 1; +constexpr uint8_t SLCR_UNA = 1 << 0; +constexpr uint8_t PHYSR_CAB = 1 << 7; +constexpr uint8_t PHYSR_CAB_OFF = 1 << 7; +constexpr uint8_t PHYSR_CAB_ON = 0 << 7; +constexpr uint8_t PHYSR_MODE = 7 << 3; +constexpr uint8_t PHYSR_MODE_AUTO = 0 << 3; +constexpr uint8_t PHYSR_MODE_100F = 4 << 3; +constexpr uint8_t PHYSR_MODE_100H = 5 << 3; +constexpr uint8_t PHYSR_MODE_10F = 6 << 3; +constexpr uint8_t PHYSR_MODE_10H = 7 << 3; +constexpr uint8_t PHYSR_DPX = 1 << 2; +constexpr uint8_t PHYSR_DPX_HALF = 1 << 2; +constexpr uint8_t PHYSR_DPX_FULL = 0 << 2; +constexpr uint8_t PHYSR_SPD = 1 << 1; +constexpr uint8_t PHYSR_SPD_10M = 1 << 1; +constexpr uint8_t PHYSR_SPD_100M = 0 << 1; +constexpr uint8_t PHYSR_LNK = 1 << 0; +constexpr uint8_t PHYSR_LNK_UP = 1 << 0; +constexpr uint8_t PHYSR_LNK_DOWN = 0 << 0; +constexpr uint8_t PHYACR_READ = 0x02; +constexpr uint8_t PHYACR_WRITE = 0x01; +constexpr uint8_t PHYDIVR_32 = 0x00; +constexpr uint8_t PHYDIVR_64 = 0x01; +constexpr uint8_t PHYDIVR_128 = 0xFF; +constexpr uint8_t PHYCR0_AUTO = 0x00; +constexpr uint8_t PHYCR0_100F = 0x04; +constexpr uint8_t PHYCR0_100H = 0x05; +constexpr uint8_t PHYCR0_10F = 0x06; +constexpr uint8_t PHYCR0_10H = 0x07; +constexpr uint8_t PHYCR1_PWDN = 1 << 5; +constexpr uint8_t PHYCR1_TE = 1 << 3; +constexpr uint8_t PHYCR1_RST = 1 << 0; +constexpr uint8_t NETxMR_UNRB = 1 << 3; +constexpr uint8_t NETxMR_PARP = 1 << 2; +constexpr uint8_t NETxMR_RSTB = 1 << 1; +constexpr uint8_t NETxMR_PB = 1 << 0; +constexpr uint8_t NETMR_ANB = 1 << 5; +constexpr uint8_t NETMR_M6B = 1 << 4; +constexpr uint8_t NETMR_WOL = 1 << 2; +constexpr uint8_t NETMR_IP6B = 1 << 1; +constexpr uint8_t NETMR_IP4B = 1 << 0; +constexpr uint8_t NETMR2_DHAS = 1 << 7; +constexpr uint8_t NETMR2_DHAS_ARP = 1 << 7; +constexpr uint8_t NETMR2_DHAS_ETH = 0 << 7; +constexpr uint8_t NETMR2_PPPoE = 1 << 0; +constexpr uint8_t ICMP6BLKR_PING6 = 1 << 4; +constexpr uint8_t ICMP6BLKR_MLD = 1 << 3; +constexpr uint8_t ICMP6BLKR_RA = 1 << 2; +constexpr uint8_t ICMP6BLKR_NA = 1 << 1; +constexpr uint8_t ICMP6BLKR_NS = 1 << 0; +constexpr uint8_t Sn_MR_MULTI = 1 << 7; +constexpr uint8_t Sn_MR_MF = 1 << 7; +constexpr uint8_t Sn_MR_BRDB = 1 << 6; +constexpr uint8_t Sn_MR_FPSH = 1 << 6; +constexpr uint8_t Sn_MR_ND = 1 << 5; +constexpr uint8_t Sn_MR_MC = 1 << 5; +constexpr uint8_t Sn_MR_SMB = 1 << 5; +constexpr uint8_t Sn_MR_MMB = 1 << 5; +constexpr uint8_t Sn_MR_MMB4 = Sn_MR_MMB; +constexpr uint8_t Sn_MR_UNIB = 1 << 4; +constexpr uint8_t Sn_MR_MMB6 = 1 << 4; +constexpr uint8_t Sn_MR_CLOSE = 0x00; +constexpr uint8_t Sn_MR_TCP = 0x01; +constexpr uint8_t Sn_MR_TCP4 = Sn_MR_TCP; +constexpr uint8_t Sn_MR_UDP = 0x02; +constexpr uint8_t Sn_MR_UDP4 = Sn_MR_UDP; +constexpr uint8_t Sn_MR_IPRAW = 0x03; +constexpr uint8_t Sn_MR_IPRAW4 = Sn_MR_IPRAW; +constexpr uint8_t Sn_MR_MACRAW = 0x07; +constexpr uint8_t Sn_MR_TCP6 = 0x09; +constexpr uint8_t Sn_MR_UDP6 = 0x0A; +constexpr uint8_t Sn_MR_IPRAW6 = 0x0B; +constexpr uint8_t Sn_MR_TCPD = 0x0D; +constexpr uint8_t Sn_MR_UDPD = 0x0E; +constexpr uint8_t Sn_CR_OPEN = 0x01; +constexpr uint8_t Sn_CR_LISTEN = 0x02; +constexpr uint8_t Sn_CR_CONNECT = 0x04; +constexpr uint8_t Sn_CR_CONNECT6 = 0x84; +constexpr uint8_t Sn_CR_DISCON = 0x08; +constexpr uint8_t Sn_CR_CLOSE = 0x10; +constexpr uint8_t Sn_CR_SEND = 0x20; +constexpr uint8_t Sn_CR_SEND6 = 0xA0; +constexpr uint8_t Sn_CR_SEND_KEEP = 0x22; +constexpr uint8_t Sn_CR_RECV = 0x40; +constexpr uint8_t Sn_IR_SENDOK = 0x10; +constexpr uint8_t Sn_IR_TIMEOUT = 0x08; +constexpr uint8_t Sn_IR_RECV = 0x04; +constexpr uint8_t Sn_IR_DISCON = 0x02; +constexpr uint8_t Sn_IR_CON = 0x01; +constexpr uint8_t SOCK_CLOSED = 0x00; +constexpr uint8_t SOCK_INIT = 0x13; +constexpr uint8_t SOCK_LISTEN = 0x14; +constexpr uint8_t SOCK_SYNSENT = 0x15; +constexpr uint8_t SOCK_SYNRECV = 0x16; +constexpr uint8_t SOCK_ESTABLISHED = 0x17; +constexpr uint8_t SOCK_FIN_WAIT = 0x18; +constexpr uint8_t SOCK_TIME_WAIT = 0x1B; +constexpr uint8_t SOCK_CLOSE_WAIT = 0x1C; +constexpr uint8_t SOCK_LAST_ACK = 0x1D; +constexpr uint8_t SOCK_UDP = 0x22; +constexpr uint8_t SOCK_IPRAW4 = 0x32; +constexpr uint8_t SOCK_IPRAW = SOCK_IPRAW4; +constexpr uint8_t SOCK_IPRAW6 = 0x33; +constexpr uint8_t SOCK_MACRAW = 0x42; +constexpr uint8_t Sn_ESR_TCPM = 1 << 2; +constexpr uint8_t Sn_ESR_TCPM_IPV4 = 0 << 2; +constexpr uint8_t Sn_ESR_TCPM_IPV6 = 1 << 2; +constexpr uint8_t Sn_ESR_TCPOP = 1 << 1; +constexpr uint8_t Sn_ESR_TCPOP_SVR = 0 << 1; +constexpr uint8_t Sn_ESR_TCPOP_CLT = 1 << 1; +constexpr uint8_t Sn_ESR_IP6T = 1 << 0; +constexpr uint8_t Sn_ESR_IP6T_LLA = 0 << 0; +constexpr uint8_t Sn_ESR_IP6T_GUA = 1 << 0; +constexpr uint8_t Sn_MR2_DHAM = 1 << 1; +constexpr uint8_t Sn_MR2_DHAM_AUTO = 0 << 1; +constexpr uint8_t Sn_MR2_DHAM_MANUAL = 1 << 1; +constexpr uint8_t Sn_MR2_FARP = 1 << 0; +constexpr uint8_t PHYRAR_BMCR = 0x00; +constexpr uint8_t PHYRAR_BMSR = 0x01; +constexpr uint16_t BMCR_RST = 1 << 15; +constexpr uint16_t BMCR_LB = 1 << 14; +constexpr uint16_t BMCR_SPD = 1 << 13; +constexpr uint16_t BMCR_ANE = 1 << 12; +constexpr uint16_t BMCR_PWDN = 1 << 11; +constexpr uint16_t BMCR_ISOL = 1 << 10; +constexpr uint16_t BMCR_REAN = 1 << 9; +constexpr uint16_t BMCR_DPX = 1 << 8; +constexpr uint16_t BMCR_COLT = 1 << 7; +constexpr uint16_t BMSR_100_T4 = 1 << 15; +constexpr uint16_t BMSR_100_FDX = 1 << 14; +constexpr uint16_t BMSR_100_HDX = 1 << 13; +constexpr uint16_t BMSR_10_FDX = 1 << 12; +constexpr uint16_t BMSR_10_HDX = 1 << 11; +constexpr uint16_t BMSR_MF_SUP = 1 << 6; +constexpr uint16_t BMSR_AN_COMP = 1 << 5; +constexpr uint16_t BMSR_REMOTE_FAULT = 1 << 4; +constexpr uint16_t BMSR_AN_ABILITY = 1 << 3; +constexpr uint16_t BMSR_LINK_STATUS = 1 << 2; +constexpr uint16_t BMSR_JABBER_DETECT = 1 << 1; +constexpr uint16_t BMSR_EXT_CAPA = 1 << 0; + +void wizchip_cris_enter(); +void wizchip_cris_exit(); +inline void WIZCHIP_CRITICAL_ENTER() { wizchip_cris_enter(); } +inline void WIZCHIP_CRITICAL_EXIT() { wizchip_cris_exit(); } + +uint8_t WIZCHIP_READ(uint32_t AddrSel); +void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb); +void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); +void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len); + +inline uint8_t getRTL() { return WIZCHIP_READ(_RTL_); } +inline uint16_t getCIDR() { return (((uint16_t)WIZCHIP_READ(_CIDR_) | (((WIZCHIP_READ(_RTL_)) & 0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_, 1)); } +inline uint16_t getVER() { return (((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_, 1)); } +inline uint8_t getSYSR() { return WIZCHIP_READ(_SYSR_); } +inline uint8_t getSYCR0() { return WIZCHIP_READ(_SYCR0_); } +inline void setSYCR0(uint8_t v) { WIZCHIP_WRITE(_SYCR0_, v); } +inline uint8_t getSYCR1() { return WIZCHIP_READ(_SYCR1_); } +inline void setSYCR1(uint8_t v) { WIZCHIP_WRITE(_SYCR1_, v); } +inline uint16_t getTCNTR() { return (((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_, 1)); } +inline void setTCNTRCLR(uint8_t v) { WIZCHIP_WRITE(_TCNTRCLR_, v); } +inline uint8_t getIR() { return WIZCHIP_READ(_IR_); } +inline uint8_t getSIR() { return WIZCHIP_READ(_SIR_); } +inline uint8_t getSLIR() { return WIZCHIP_READ(_SLIR_); } +inline void setIMR(uint8_t v) { WIZCHIP_WRITE(_IMR_, v); } +inline uint8_t getIMR() { return WIZCHIP_READ(_IMR_); } +inline void setIRCLR(uint8_t v) { WIZCHIP_WRITE(_IRCLR_, v); } +inline void setIR(uint8_t v) { setIRCLR(v); } +inline void setSIMR(uint8_t v) { WIZCHIP_WRITE(_SIMR_, v); } +inline uint8_t getSIMR() { return WIZCHIP_READ(_SIMR_); } +inline void setSLIMR(uint8_t v) { WIZCHIP_WRITE(_SLIMR_, v); } +inline uint8_t getSLIMR() { return WIZCHIP_READ(_SLIMR_); } +inline void setSLIRCLR(uint8_t v) { WIZCHIP_WRITE(_SLIRCLR_, v); } +inline void setSLIR(uint8_t v) { setSLIRCLR(v); } +inline void setSLPSR(uint8_t v) { WIZCHIP_WRITE(_SLPSR_, v); } +inline uint8_t getSLPSR() { return WIZCHIP_READ(_SLPSR_); } +inline void setSLCR(uint8_t v) { WIZCHIP_WRITE(_SLCR_, v); } +inline uint8_t getSLCR() { return WIZCHIP_READ(_SLCR_); } +inline uint8_t getPHYSR() { return WIZCHIP_READ(_PHYSR_); } +inline void setPHYRAR(uint8_t v) { WIZCHIP_WRITE(_PHYRAR_, v); } +inline uint8_t getPHYRAR() { return WIZCHIP_READ(_PHYRAR_); } +inline void setPHYDIR(uint16_t v) { + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_, 1), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(_PHYDIR_, (uint8_t)v); +} +inline uint16_t getPHYDOR() { return (((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_, 1))) << 8) + WIZCHIP_READ(_PHYDOR_); } +inline void setPHYACR(uint8_t v) { WIZCHIP_WRITE(_PHYACR_, v); } +inline uint8_t getPHYACR() { return WIZCHIP_READ(_PHYACR_); } +inline void setPHYDIVR(uint8_t v) { WIZCHIP_WRITE(_PHYDIVR_, v); } +inline uint8_t getPHYDIVR() { return WIZCHIP_READ(_PHYDIVR_); } +inline void setPHYCR0(uint8_t v) { WIZCHIP_WRITE(_PHYCR0_, v); } +inline void setPHYCR1(uint8_t v) { WIZCHIP_WRITE(_PHYCR1_, v); } +inline uint8_t getPHYCR1() { return WIZCHIP_READ(_PHYCR1_); } +inline void setNET4MR(uint8_t v) { WIZCHIP_WRITE(_NET4MR_, v); } +inline void setNET6MR(uint8_t v) { WIZCHIP_WRITE(_NET6MR_, v); } +inline void setNETMR(uint8_t v) { WIZCHIP_WRITE(_NETMR_, v); } +inline void setNETMR2(uint8_t v) { WIZCHIP_WRITE(_NETMR2_, v); } +inline uint8_t getNET4MR() { return WIZCHIP_READ(_NET4MR_); } +inline uint8_t getNET6MR() { return WIZCHIP_READ(_NET6MR_); } +inline uint8_t getNETMR() { return WIZCHIP_READ(_NETMR_); } +inline uint8_t getNETMR2() { return WIZCHIP_READ(_NETMR2_); } +inline void setPTMR(uint8_t v) { WIZCHIP_WRITE(_PTMR_, v); } +inline uint8_t getPTMR() { return WIZCHIP_READ(_PTMR_); } +inline void setPMNR(uint8_t v) { WIZCHIP_WRITE(_PMNR_, v); } +inline uint8_t getPMNR() { return WIZCHIP_READ(_PMNR_); } +inline void setPHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_PHAR_, v, 6); } +inline void getPHAR(uint8_t* v) { WIZCHIP_READ_BUF(_PHAR_, v, 6); } +inline void setPSIDR(uint16_t v) { + WIZCHIP_WRITE(_PSIDR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_, 1), (uint8_t)v); +} +inline uint16_t getPSIDR() { return (((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_, 1)); } +inline void setPMRUR(uint16_t v) { + WIZCHIP_WRITE(_PMRUR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_, 1), (uint8_t)v); +} +inline uint16_t getPMRUR() { return (((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_, 1)); } +inline void setSHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SHAR_, v, 6); } +inline void getSHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SHAR_, v, 6); } +inline void setGAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GAR_, v, 4); } +inline void getGAR(uint8_t* v) { WIZCHIP_READ_BUF(_GAR_, v, 4); } +inline void setGA4R(uint8_t* v) { setGAR(v); } +inline void getGA4R(uint8_t* v) { getGAR(v); } +inline void setSUBR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUBR_, v, 4); } +inline void getSUBR(uint8_t* v) { WIZCHIP_READ_BUF(_SUBR_, v, 4); } +inline void setSUB4R(uint8_t* v) { setSUBR(v); } +inline void getSUB4R(uint8_t* v) { getSUBR(v); } +inline void setSIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SIPR_, v, 4); } +inline void getSIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SIPR_, v, 4); } +inline void setLLAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_LLAR_, v, 16); } +inline void getLLAR(uint8_t* v) { WIZCHIP_READ_BUF(_LLAR_, v, 16); } +inline void setGUAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GUAR_, v, 16); } +inline void getGUAR(uint8_t* v) { WIZCHIP_READ_BUF(_GUAR_, v, 16); } +inline void setSUB6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUB6R_, v, 16); } +inline void getSUB6R(uint8_t* v) { WIZCHIP_READ_BUF(_SUB6R_, v, 16); } +inline void setGA6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_GA6R_, v, 16); } +inline void getGA6R(uint8_t* v) { WIZCHIP_READ_BUF(_GA6R_, v, 16); } +inline void setSLDIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIPR_, v, 4); } +inline void setSLDIP4R(uint8_t* v) { setSLDIPR(v); } +inline void getSLDIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIPR_, v, 4); } +inline void getSLDIP4R(uint8_t* v) { getSLDIPR(v); } +inline void setSLDIP6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIP6R_, v, 16); } +inline void getSLDIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIP6R_, v, 16); } +inline void getSLDHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDHAR_, v, 6); } +inline void setPINGIDR(uint16_t v) { + WIZCHIP_WRITE(_PINGIDR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_, 1), (uint8_t)v); +} +inline uint16_t getPINGIDR() { return ((uint16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_, 1)); } +inline void setPINGSEQR(uint16_t v) { + WIZCHIP_WRITE(_PINGSEQR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1), (uint8_t)v); +} +inline uint16_t getPINGSEQR() { return ((uint16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1)); } +inline void getUIPR(uint8_t* v) { WIZCHIP_READ_BUF(_UIPR_, v, 4); } +inline void getUIP4R(uint8_t* v) { getUIPR(v); } +inline uint16_t getUPORTR() { return (((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_, 1)); } +inline uint16_t getUPORT4R() { return getUPORTR(); } +inline void getUIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_UIP6R_, v, 16); } +inline uint16_t getUPORT6R() { return (((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_, 1)); } +inline void setINTPTMR(uint16_t v) { + WIZCHIP_WRITE(_INTPTMR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_, 1), (uint8_t)v); +} +inline uint16_t getINTPTMR() { return (((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_, 1)); } +inline uint8_t getPLR() { return WIZCHIP_READ(_PLR_); } +inline uint8_t getPFR() { return WIZCHIP_READ(_PFR_); } +inline uint32_t getVLTR() { + return (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) + + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 1))) << 16) + + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 2))) << 8) + + ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 3))); +} +inline uint32_t getPLTR() { + return (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) + + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 1))) << 16) + + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 2))) << 8) + + ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 3))); +} +inline void getPAR(uint8_t* v) { WIZCHIP_READ_BUF(_PAR_, v, 16); } +inline void setICMP6BLKR(uint8_t v) { WIZCHIP_WRITE(_ICMP6BLKR_, v); } +inline uint8_t getICMP6BLKR() { return WIZCHIP_READ(_ICMP6BLKR_); } +inline void setCHPLCKR(uint8_t v) { WIZCHIP_WRITE(_CHPLCKR_, v); } +inline uint8_t getCHPLCKR() { return (getSYSR() & SYSR_CHPL) >> 7; } +inline void CHIPLOCK() { setCHPLCKR(0xFF); } +inline void CHIPUNLOCK() { setCHPLCKR(0xCE); } +inline void setNETLCKR(uint8_t v) { WIZCHIP_WRITE(_NETLCKR_, v); } +inline uint8_t getNETLCKR() { return (getSYSR() & SYSR_NETL) >> 6; } +inline void NETLOCK() { setNETLCKR(0xC5); } +inline void NETUNLOCK() { setNETLCKR(0x3A); } +inline void setPHYLCKR(uint8_t v) { WIZCHIP_WRITE(_PHYLCKR_, v); } +inline uint8_t getPHYLCKR() { return (getSYSR() & SYSR_PHYL) >> 5; } +inline void PHYLOCK() { setPHYLCKR(0xFF); } +inline void PHYUNLOCK() { setPHYLCKR(0x53); } +inline void setRTR(uint16_t v) { + WIZCHIP_WRITE(_RTR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_, 1), (uint8_t)v); +} +inline uint16_t getRTR() { return (((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); } +inline void setRCR(uint8_t v) { WIZCHIP_WRITE(_RCR_, v); } +inline uint8_t getRCR() { return WIZCHIP_READ(_RCR_); } +inline void setSLRTR(uint16_t v) { + WIZCHIP_WRITE(_SLRTR_, (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_, 1), (uint8_t)v); +} +inline uint16_t getSLRTR() { return (((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_, 1)); } +inline void setSLRCR(uint8_t v) { WIZCHIP_WRITE(_SLRCR_, v); } +inline uint8_t getSLRCR() { return WIZCHIP_READ(_SLRCR_); } +inline void setSLHOPR(uint8_t v) { WIZCHIP_WRITE(_SLHOPR_, v); } +inline uint8_t getSLHOPR() { return WIZCHIP_READ(_SLHOPR_); } + +inline void setSn_MR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR_(sn), v); } +inline uint8_t getSn_MR(uint8_t sn) { return WIZCHIP_READ(_Sn_MR_(sn)); } +inline void setSn_PSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PSR_(sn), v); } +inline uint8_t getSn_PSR(uint8_t sn) { return WIZCHIP_READ(_Sn_PSR_(sn)); } +inline void setSn_CR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_CR_(sn), v); } +inline uint8_t getSn_CR(uint8_t sn) { return WIZCHIP_READ(_Sn_CR_(sn)); } +inline uint8_t getSn_IR(uint8_t sn) { return WIZCHIP_READ(_Sn_IR_(sn)); } +inline void setSn_IMR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IMR_(sn), v); } +inline uint8_t getSn_IMR(uint8_t sn) { return WIZCHIP_READ(_Sn_IMR_(sn)); } +inline void setSn_IRCLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IRCLR_(sn), v); } +inline void setSn_IR(uint8_t sn, uint8_t v) { setSn_IRCLR(sn, v); } +inline uint8_t getSn_SR(uint8_t sn) { return WIZCHIP_READ(_Sn_SR_(sn)); } +inline uint8_t getSn_ESR(uint8_t sn) { return WIZCHIP_READ(_Sn_ESR_(sn)); } +inline void setSn_PNR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PNR_(sn), v); } +inline void setSn_NHR(uint8_t sn, uint8_t v) { setSn_PNR(sn, v); } +inline uint8_t getSn_PNR(uint8_t sn) { return WIZCHIP_READ(_Sn_PNR_(sn)); } +inline uint8_t getSn_NHR(uint8_t sn) { return getSn_PNR(sn); } +inline void setSn_TOSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TOSR_(sn), v); } +inline uint8_t getSn_TOSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TOSR_(sn)); } +inline uint8_t getSn_TOS(uint8_t sn) { return getSn_TOSR(sn); } +inline void setSn_TOS(uint8_t sn, uint8_t v) { setSn_TOSR(sn, v); } +inline void setSn_TTLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TTLR_(sn), v); } +inline uint8_t getSn_TTLR(uint8_t sn) { return WIZCHIP_READ(_Sn_TTLR_(sn)); } +inline void setSn_TTL(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } +inline uint8_t getSn_TTL(uint8_t sn) { return getSn_TTLR(sn); } +inline void setSn_HOPR(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); } +inline uint8_t getSn_HOPR(uint8_t sn) { return getSn_TTLR(sn); } +inline void setSn_FRGR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_FRGR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1)); } +inline void setSn_MSSR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_MSSR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1)); } +inline void setSn_PORTR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_PORTR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1)); } +inline void setSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn), v, 6); } +inline void getSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DHAR_(sn), v, 6); } +inline void setSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn), v, 4); } +inline void getSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIPR_(sn), v, 4); } +inline void setSn_DIP4R(uint8_t sn, uint8_t* v) { setSn_DIPR(sn, v); } +inline void getSn_DIP4R(uint8_t sn, uint8_t* v) { getSn_DIPR(sn, v); } +inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn), v, 16); } +inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIP6R_(sn), v, 16); } +inline void setSn_DPORTR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_DPORTR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1)); } +inline uint16_t getSn_DPORT(uint8_t sn) { return getSn_DPORTR(sn); } +inline void setSn_DPORT(uint8_t sn, uint16_t v) { setSn_DPORTR(sn, v); } +inline void setSn_MR2(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR2_(sn), v); } +inline uint8_t getSn_MR2(uint8_t sn) { return WIZCHIP_READ(_Sn_MR2_(sn)); } +inline void setSn_RTR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_RTR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1)); } +inline void setSn_RCR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RCR_(sn), v); } +inline uint8_t getSn_RCR(uint8_t sn) { return WIZCHIP_READ(_Sn_RCR_(sn)); } +inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_KPALVTR_(sn), v); } +inline uint8_t getSn_KPALVTR(uint8_t sn) { return WIZCHIP_READ(_Sn_KPALVTR_(sn)); } +inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TX_BSR_(sn), v); } +inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_TX_BSR(sn, v); } +inline uint8_t getSn_TX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TX_BSR_(sn)); } +inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) { return getSn_TX_BSR(sn); } +inline uint16_t getSn_TxMAX(uint8_t sn) { return getSn_TX_BSR(sn) << 10; } + +uint16_t getSn_TX_FSR(uint8_t sn); + +inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn), 1)); } +inline void setSn_TX_WR(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1)); } +inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RX_BSR_(sn), v); } +inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_RX_BSR(sn, v); } +inline uint8_t getSn_RX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_RX_BSR_(sn)); } +inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) { return getSn_RX_BSR(sn); } +inline uint16_t getSn_RxMAX(uint8_t sn) { return getSn_RX_BSR(sn) << 10; } + +uint16_t getSn_RX_RSR(uint8_t s); + +inline void setSn_RX_RD(uint8_t sn, uint16_t v) { + WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)(v >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1), (uint8_t)v); +} +inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1)); } +inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn), 1)); } +void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len); +void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len); +void wiz_recv_ignore(uint8_t sn, uint16_t len); +void wiz_delay_ms(uint32_t ms); + +void wiz_mdio_write(uint8_t phyregaddr, uint16_t var); +uint16_t wiz_mdio_read(uint8_t phyregaddr); + diff --git a/w6300/wizchip_conf.h b/w6300/wizchip_conf.h deleted file mode 100644 index 0e410ad..0000000 --- a/w6300/wizchip_conf.h +++ /dev/null @@ -1,172 +0,0 @@ -#pragma once -#include - -constexpr int _WIZCHIP_ = 6300; - -constexpr uint16_t _PHY_IO_MODE_PHYCR_ = 0x0000; -constexpr uint16_t _PHY_IO_MODE_MII_ = 0x0010; -constexpr uint16_t _PHY_IO_MODE_ = _PHY_IO_MODE_MII_; - -constexpr uint8_t _WIZCHIP_QSPI_MODE_ = 0x02 << 6; - -using iodata_t = uint8_t; -using datasize_t = int16_t; - -#include "w6300.h" - -constexpr int WIZCHIP_SOCK_NUM = 8; -constexpr int _WIZCHIP_SOCK_NUM_ = WIZCHIP_SOCK_NUM; - -enum ctlwizchip_type { - CW_SYS_LOCK, CW_SYS_UNLOCK, CW_GET_SYSLOCK, - CW_RESET_WIZCHIP, CW_INIT_WIZCHIP, - CW_GET_INTERRUPT, CW_CLR_INTERRUPT, CW_SET_INTRMASK, CW_GET_INTRMASK, - CW_SET_INTRTIME, CW_GET_INTRTIME, CW_SET_IEN, CW_GET_IEN, - CW_GET_ID, CW_GET_VER, CW_SET_SYSCLK, CW_GET_SYSCLK, - CW_RESET_PHY, CW_SET_PHYCONF, CW_GET_PHYCONF, CW_GET_PHYSTATUS, - CW_SET_PHYPOWMODE, CW_GET_PHYPOWMODE, CW_GET_PHYLINK -}; - -enum ctlnetwork_type { - CN_SET_NETINFO, CN_GET_NETINFO, CN_SET_NETMODE, CN_GET_NETMODE, - CN_SET_TIMEOUT, CN_GET_TIMEOUT, CN_SET_PREFER, CN_GET_PREFER, -}; - -enum ctlnetservice_type { - CNS_ARP, CNS_PING, CNS_DAD, CNS_SLAAC, CNS_UNSOL_NA, CNS_GET_PREFIX -}; - -enum intr_kind : uint32_t { - IK_PPPOE_TERMINATED = (1 << 0), IK_DEST_UNREACH = (1 << 1), IK_IP_CONFLICT = (1 << 2), - IK_DEST_UNREACH6 = (1 << 4), IK_WOL = (1 << 7), IK_NET_ALL = 0x97, - IK_SOCK_0 = (1 << 8), IK_SOCK_1 = (1 << 9), IK_SOCK_2 = (1 << 10), IK_SOCK_3 = (1 << 11), - IK_SOCK_4 = (1 << 12), IK_SOCK_5 = (1 << 13), IK_SOCK_6 = (1 << 14), IK_SOCK_7 = (1 << 15), - IK_SOCK_ALL = (0xFF << 8), - IK_SOCKL_TOUT = (1 << 16), IK_SOCKL_ARP4 = (1 << 17), IK_SOCKL_PING4 = (1 << 18), - IK_SOCKL_ARP6 = (1 << 19), IK_SOCKL_PING6 = (1 << 20), IK_SOCKL_NS = (1 << 21), - IK_SOCKL_RS = (1 << 22), IK_SOCKL_RA = (1 << 23), IK_SOCKL_ALL = (0xFF << 16), - IK_INT_ALL = 0x00FFFF97 -}; - -constexpr uint8_t SYS_CHIP_LOCK = (1 << 2); -constexpr uint8_t SYS_NET_LOCK = (1 << 1); -constexpr uint8_t SYS_PHY_LOCK = (1 << 0); - -constexpr uint8_t PHY_MODE_MANUAL = 0; -constexpr uint8_t PHY_MODE_AUTONEGO = 1; -constexpr uint8_t PHY_MODE_TE = 2; -constexpr uint8_t PHY_CONFBY_HW = 0; -constexpr uint8_t PHY_CONFBY_SW = 1; -constexpr uint8_t PHY_SPEED_10 = 0; -constexpr uint8_t PHY_SPEED_100 = 1; -constexpr uint8_t PHY_DUPLEX_HALF = 0; -constexpr uint8_t PHY_DUPLEX_FULL = 1; -constexpr uint8_t PHY_LINK_OFF = 0; -constexpr uint8_t PHY_LINK_ON = 1; -constexpr uint8_t PHY_POWER_NORM = 0; -constexpr uint8_t PHY_POWER_DOWN = 1; - -struct wiz_PhyConf { - uint8_t by; - uint8_t mode; - uint8_t speed; - uint8_t duplex; -}; - -enum ipconf_mode : uint8_t { - NETINFO_NONE = 0x00, NETINFO_STATIC_V4 = 0x01, NETINFO_STATIC_V6 = 0x02, - NETINFO_STATIC_ALL = 0x03, NETINFO_SLAAC_V6 = 0x04, - NETINFO_DHCP_V4 = 0x10, NETINFO_DHCP_V6 = 0x20, NETINFO_DHCP_ALL = 0x30 -}; - -enum dhcp_mode : uint8_t { NETINFO_STATIC = 1, NETINFO_DHCP }; - -struct wiz_NetInfo { - uint8_t mac[6]; - uint8_t ip[4]; - uint8_t sn[4]; - uint8_t gw[4]; - uint8_t lla[16]; - uint8_t gua[16]; - uint8_t sn6[16]; - uint8_t gw6[16]; - uint8_t dns[4]; - uint8_t dns6[16]; - ipconf_mode ipmode; - dhcp_mode dhcp; -}; - -enum netmode_type : uint32_t { - NM_IPB_V4 = (1 << 0), NM_IPB_V6 = (1 << 1), NM_WOL = (1 << 2), - NM_PB6_MULTI = (1 << 4), NM_PB6_ALLNODE = (1 << 5), NM_MR_MASK = 0x37, - NM_PPPoE = (1 << 8), NM_DHA_SELECT = (1 << 15), NM_MR2_MASK = (0x09 << 8), - NM_PB4_ALL = (1 << 16), NM_TRSTB_V4 = (1 << 17), NM_PARP_V4 = (1 << 18), - NM_UNRB_V4 = (1 << 19), NM_NET4_MASK = (0x0F << 16), - NM_PB6_ALL = (1 << 24), NM_TRSTB_V6 = (1 << 25), NM_PARP_V6 = (1 << 26), - NM_UNRB_V6 = (1 << 27), NM_NET6_MASK = (0x0F << 24), - NM_MASK_ALL = 0x0F0F0937 -}; - -struct wiz_NetTimeout { - uint8_t s_retry_cnt; - uint16_t s_time_100us; - uint8_t sl_retry_cnt; - uint16_t sl_time_100us; -}; - -struct wiz_IPAddress { - uint8_t ip[16]; - uint8_t len; -}; - -struct wiz_Prefix { - uint8_t len; - uint8_t flag; - uint32_t valid_lifetime; - uint32_t preferred_lifetime; - uint8_t prefix[16]; -}; - -struct wiz_ARP { - wiz_IPAddress destinfo; - uint8_t dha[6]; -}; - -struct wiz_PING { - uint16_t id; - uint16_t seq; - wiz_IPAddress destinfo; -}; - -int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg); -int8_t ctlnetwork(ctlnetwork_type cntype, void* arg); -int8_t ctlnetservice(ctlnetservice_type cnstype, void* arg); - -void wizchip_sw_reset(); -int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize); -void wizchip_clrinterrupt(intr_kind intr); -intr_kind wizchip_getinterrupt(); -void wizchip_setinterruptmask(intr_kind intr); -intr_kind wizchip_getinterruptmask(); - -int8_t wizphy_getphylink(); -int8_t wizphy_getphypmode(); -void wizphy_reset(); -void wizphy_setphyconf(wiz_PhyConf* phyconf); -void wizphy_getphyconf(wiz_PhyConf* phyconf); -void wizphy_getphystat(wiz_PhyConf* phyconf); -void wizphy_setphypmode(uint8_t pmode); - -void wizchip_setnetinfo(wiz_NetInfo* pnetinfo); -void wizchip_getnetinfo(wiz_NetInfo* pnetinfo); -void wizchip_setnetmode(netmode_type netmode); -netmode_type wizchip_getnetmode(); -void wizchip_settimeout(wiz_NetTimeout* nettime); -void wizchip_gettimeout(wiz_NetTimeout* nettime); - -int8_t wizchip_arp(wiz_ARP* arp); -int8_t wizchip_ping(wiz_PING* ping); -int8_t wizchip_dad(uint8_t* ipv6); -int8_t wizchip_slaac(wiz_Prefix* prefix); -int8_t wizchip_unsolicited(); -int8_t wizchip_getprefix(wiz_Prefix* prefix); diff --git a/w6300/wizchip_spi.h b/w6300/wizchip_spi.h deleted file mode 100644 index c9ff021..0000000 --- a/w6300/wizchip_spi.h +++ /dev/null @@ -1,22 +0,0 @@ -#pragma once -#include -#include "wizchip_conf.h" - -constexpr uint8_t PIN_INT = 15; -constexpr uint8_t PIN_CS = 16; -constexpr uint8_t PIO_SPI_SCK_PIN = 17; -constexpr uint8_t PIO_SPI_DATA_IO0_PIN = 18; -constexpr uint8_t PIO_SPI_DATA_IO1_PIN = 19; -constexpr uint8_t PIO_SPI_DATA_IO2_PIN = 20; -constexpr uint8_t PIO_SPI_DATA_IO3_PIN = 21; -constexpr uint8_t PIN_RST = 22; - -constexpr uint16_t WIZNET_SPI_CLKDIV_MAJOR_DEFAULT = 2; -constexpr uint8_t WIZNET_SPI_CLKDIV_MINOR_DEFAULT = 0; - -void wizchip_spi_initialize(); -void wizchip_cris_initialize(); -void wizchip_reset(); -void wizchip_initialize(); -void wizchip_check(); -void network_initialize(wiz_NetInfo net_info);