diff --git a/w6300/socket.cpp b/w6300/socket.cpp
index 3cc611a..9642458 100644
--- a/w6300/socket.cpp
+++ b/w6300/socket.cpp
@@ -1,6 +1,6 @@
 #include "socket.h"
 
-#define SOCK_ANY_PORT_NUM  0xC000
+constexpr uint16_t SOCK_ANY_PORT_NUM = 0xC000;
 
 static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
 static uint16_t sock_io_mode = 0;
@@ -18,15 +18,6 @@ uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
 #define CHECK_SOCKDATA()  do { if(len == 0) return SOCKERR_DATALEN; } while(0)
 #define CHECK_IPZERO(addr, addrlen) do { uint16_t ipzero=0; for(uint8_t i=0; i<addrlen; i++) ipzero += (uint16_t)addr[i]; if(ipzero == 0) return SOCKERR_IPINVALID; } while(0)
 
-#define Sn_MR_TCP4    (Sn_MR_TCP)
-#define Sn_MR_UDP4    (Sn_MR_UDP)
-#define Sn_MR_IPRAW4  (Sn_MR_IPRAW)
-#define Sn_MR_TCP6    (0x09)
-#define Sn_MR_UDP6    (0x0A)
-#define Sn_MR_IPRAW6  (0x0B)
-#define Sn_MR_TCPD    (0x0D)
-#define Sn_MR_UDPD    (0x0E)
-
 int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag) {
     uint8_t taddr[16];
     CHECK_SOCKNUM();
diff --git a/w6300/socket.h b/w6300/socket.h
index e2e5f00..45f03b5 100644
--- a/w6300/socket.h
+++ b/w6300/socket.h
@@ -1,62 +1,60 @@
 #pragma once
 #include "wizchip_conf.h"
 
-#define SOCKET                uint8_t
+using SOCKET = uint8_t;
 
-#define SOCK_OK               1
-#define SOCK_BUSY             0
-#define SOCK_FATAL            -1000
+constexpr int16_t SOCK_OK             = 1;
+constexpr int16_t SOCK_BUSY           = 0;
+constexpr int16_t SOCK_FATAL          = -1000;
+constexpr int16_t SOCK_ERROR          = 0;
+constexpr int16_t SOCKERR_SOCKNUM     = SOCK_ERROR - 1;
+constexpr int16_t SOCKERR_SOCKOPT     = SOCK_ERROR - 2;
+constexpr int16_t SOCKERR_SOCKINIT    = SOCK_ERROR - 3;
+constexpr int16_t SOCKERR_SOCKCLOSED  = SOCK_ERROR - 4;
+constexpr int16_t SOCKERR_SOCKMODE    = SOCK_ERROR - 5;
+constexpr int16_t SOCKERR_SOCKFLAG    = SOCK_ERROR - 6;
+constexpr int16_t SOCKERR_SOCKSTATUS  = SOCK_ERROR - 7;
+constexpr int16_t SOCKERR_ARG         = SOCK_ERROR - 10;
+constexpr int16_t SOCKERR_PORTZERO    = SOCK_ERROR - 11;
+constexpr int16_t SOCKERR_IPINVALID   = SOCK_ERROR - 12;
+constexpr int16_t SOCKERR_TIMEOUT     = SOCK_ERROR - 13;
+constexpr int16_t SOCKERR_DATALEN     = SOCK_ERROR - 14;
+constexpr int16_t SOCKERR_BUFFER      = SOCK_ERROR - 15;
+constexpr int16_t SOCKFATAL_PACKLEN   = SOCK_FATAL - 1;
 
-#define SOCK_ERROR            0
-#define SOCKERR_SOCKNUM       (SOCK_ERROR - 1)
-#define SOCKERR_SOCKOPT       (SOCK_ERROR - 2)
-#define SOCKERR_SOCKINIT      (SOCK_ERROR - 3)
-#define SOCKERR_SOCKCLOSED    (SOCK_ERROR - 4)
-#define SOCKERR_SOCKMODE      (SOCK_ERROR - 5)
-#define SOCKERR_SOCKFLAG      (SOCK_ERROR - 6)
-#define SOCKERR_SOCKSTATUS    (SOCK_ERROR - 7)
-#define SOCKERR_ARG           (SOCK_ERROR - 10)
-#define SOCKERR_PORTZERO      (SOCK_ERROR - 11)
-#define SOCKERR_IPINVALID     (SOCK_ERROR - 12)
-#define SOCKERR_TIMEOUT       (SOCK_ERROR - 13)
-#define SOCKERR_DATALEN       (SOCK_ERROR - 14)
-#define SOCKERR_BUFFER        (SOCK_ERROR - 15)
+constexpr uint8_t SF_MULTI_ENABLE     = Sn_MR_MULTI;
+constexpr uint8_t SF_ETHER_OWN        = Sn_MR_MF;
+constexpr uint8_t SF_BROAD_BLOCK      = Sn_MR_BRDB;
+constexpr uint8_t SF_TCP_FPSH         = Sn_MR_FPSH;
+constexpr uint8_t SF_TCP_NODELAY      = Sn_MR_ND;
+constexpr uint8_t SF_IGMP_VER2        = Sn_MR_MC;
+constexpr uint8_t SF_SOLICIT_BLOCK    = Sn_MR_SMB;
+constexpr uint8_t SF_ETHER_MULTI4B    = Sn_MR_MMB4;
+constexpr uint8_t SF_UNI_BLOCK        = Sn_MR_UNIB;
+constexpr uint8_t SF_ETHER_MULIT6B    = Sn_MR_MMB6;
+constexpr uint8_t SF_FORCE_ARP        = Sn_MR2_FARP;
+constexpr uint8_t SF_DHA_MANUAL       = Sn_MR2_DHAM;
+constexpr uint8_t SF_IO_NONBLOCK      = 0x01 << 3;
 
-#define SOCKFATAL_PACKLEN     (SOCK_FATAL - 1)
+constexpr uint8_t PACK_IPv6           = 1 << 7;
+constexpr uint8_t PACK_IPV6_ALLNODE   = PACK_IPv6 | (1 << 6);
+constexpr uint8_t PACK_IPV6_MULTI     = PACK_IPv6 | (1 << 5);
+constexpr uint8_t PACK_IPV6_LLA       = PACK_IPv6 | (1 << 4);
+constexpr uint8_t PACK_COMPLETED      = 1 << 3;
+constexpr uint8_t PACK_REMAINED       = 1 << 2;
+constexpr uint8_t PACK_FIRST          = 1 << 1;
+constexpr uint8_t PACK_NONE           = 0x00;
 
-#define SF_MULTI_ENABLE      (Sn_MR_MULTI)
-#define SF_ETHER_OWN         (Sn_MR_MF)
-#define SF_BROAD_BLOCK       (Sn_MR_BRDB)
-#define SF_TCP_FPSH          (Sn_MR_FPSH)
-#define SF_TCP_NODELAY       (Sn_MR_ND)
-#define SF_IGMP_VER2         (Sn_MR_MC)
-#define SF_SOLICIT_BLOCK     (Sn_MR_SMB)
-#define SF_ETHER_MULTI4B     (Sn_MR_MMB4)
-#define SF_UNI_BLOCK         (Sn_MR_UNIB)
-#define SF_ETHER_MULIT6B     (Sn_MR_MMB6)
-#define SF_FORCE_ARP         (Sn_MR2_FARP)
-#define SF_DHA_MANUAL        (Sn_MR2_DHAM)
-#define SF_IO_NONBLOCK       (0x01 << 3)
+constexpr uint8_t SRCV6_PREFER_AUTO   = PSR_AUTO;
+constexpr uint8_t SRCV6_PREFER_LLA    = PSR_LLA;
+constexpr uint8_t SRCV6_PREFER_GUA    = PSR_GUA;
 
-#define PACK_IPv6            (1<<7)
-#define PACK_IPV6_ALLNODE    (PACK_IPv6 | (1<<6))
-#define PACK_IPV6_MULTI      (PACK_IPv6 | (1<<5))
-#define PACK_IPV6_LLA        (PACK_IPv6 | (1<<4))
-#define PACK_COMPLETED       (1<<3)
-#define PACK_REMAINED        (1<<2)
-#define PACK_FIRST           (1<<1)
-#define PACK_NONE            (0x00)
+constexpr uint8_t TCPSOCK_MODE        = Sn_ESR_TCPM;
+constexpr uint8_t TCPSOCK_OP          = Sn_ESR_TCPOP;
+constexpr uint8_t TCPSOCK_SIP         = Sn_ESR_IP6T;
 
-#define SRCV6_PREFER_AUTO    (PSR_AUTO)
-#define SRCV6_PREFER_LLA     (PSR_LLA)
-#define SRCV6_PREFER_GUA     (PSR_GUA)
-
-#define TCPSOCK_MODE         (Sn_ESR_TCPM)
-#define TCPSOCK_OP           (Sn_ESR_TCPOP)
-#define TCPSOCK_SIP          (Sn_ESR_IP6T)
-
-#define SOCK_IO_BLOCK         0
-#define SOCK_IO_NONBLOCK      1
+constexpr uint8_t SOCK_IO_BLOCK       = 0;
+constexpr uint8_t SOCK_IO_NONBLOCK    = 1;
 
 int8_t  socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag);
 int8_t  close(uint8_t sn);
@@ -114,7 +112,7 @@ int8_t  connect_W6x00(uint8_t sn, uint8_t * addr, uint16_t port, uint8_t addrlen
 int32_t sendto_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port, uint8_t addrlen);
 int32_t recvfrom_W6x00(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port, uint8_t *addrlen);
 
-#define connect(sn, addr, port, addrlen) connect_W6x00(sn, addr, port, addrlen)
-#define sendto(sn, buf, len, addr, port, addrlen) sendto_W6x00(sn, buf, len, addr, port, addrlen)
-#define recvfrom(sn, buf, len, addr, port, addrlen) recvfrom_W6x00(sn, buf, len, addr, port, addrlen)
+inline int8_t connect(uint8_t sn, uint8_t* addr, uint16_t port, uint8_t addrlen) { return connect_W6x00(sn, addr, port, addrlen); }
+inline int32_t sendto(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t port, uint8_t addrlen) { return sendto_W6x00(sn, buf, len, addr, port, addrlen); }
+inline int32_t recvfrom(uint8_t sn, uint8_t* buf, uint16_t len, uint8_t* addr, uint16_t* port, uint8_t* addrlen) { return recvfrom_W6x00(sn, buf, len, addr, port, addrlen); }
 
diff --git a/w6300/w6300.cpp b/w6300/w6300.cpp
index 6ba0750..069df4e 100644
--- a/w6300/w6300.cpp
+++ b/w6300/w6300.cpp
@@ -91,7 +91,6 @@ void wiz_delay_ms(uint32_t milliseconds) {
     }
 }
 
-#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
 void wiz_mdio_write(uint8_t phyregaddr, uint16_t var) {
     setPHYRAR(phyregaddr);
     setPHYDIR(var);
@@ -105,4 +104,3 @@ uint16_t wiz_mdio_read(uint8_t phyregaddr) {
     while (getPHYACR());
     return getPHYDOR();
 }
-#endif
diff --git a/w6300/w6300.h b/w6300/w6300.h
index c793d0c..690767c 100644
--- a/w6300/w6300.h
+++ b/w6300/w6300.h
@@ -10,893 +10,561 @@ constexpr uint32_t WIZCHIP_SREG_BLOCK(uint8_t n) { return 1 + 4 * n; }
 constexpr uint32_t WIZCHIP_TXBUF_BLOCK(uint8_t n) { return 2 + 4 * n; }
 constexpr uint32_t WIZCHIP_RXBUF_BLOCK(uint8_t n) { return 3 + 4 * n; }
 
-#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8))
+constexpr uint32_t WIZCHIP_OFFSET_INC(uint32_t addr, uint32_t n) { return addr + (n << 8); }
 
-#define _CIDR_               ((0x0000 << 8) + WIZCHIP_CREG_BLOCK)
-#define _RTL_                ((0x0004 << 8) + WIZCHIP_CREG_BLOCK)
-#define _VER_                ((0x0002 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SYSR_               ((0x2000 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SYCR0_              ((0x2004 << 8) + WIZCHIP_CREG_BLOCK)
+constexpr uint32_t _CIDR_      = (0x0000 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _RTL_       = (0x0004 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _VER_       = (0x0002 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SYSR_      = (0x2000 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SYCR0_     = (0x2004 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SYCR1_     = WIZCHIP_OFFSET_INC(_SYCR0_, 1);
+constexpr uint32_t _TCNTR_     = (0x2016 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _TCNTRCLR_  = (0x2020 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _IR_        = (0x2100 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SIR_       = (0x2101 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLIR_      = (0x2102 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _IMR_       = (0x2104 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _IRCLR_     = (0x2108 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SIMR_      = (0x2114 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLIMR_     = (0x2124 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLIRCLR_   = (0x2128 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLPSR_     = (0x212C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLCR_      = (0x2130 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYSR_     = (0x3000 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYRAR_    = (0x3008 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYDIR_    = (0x300C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYDOR_    = (0x3010 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYACR_    = (0x3014 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYDIVR_   = (0x3018 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYCR0_    = (0x301C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYCR1_    = WIZCHIP_OFFSET_INC(_PHYCR0_, 1);
+constexpr uint32_t _NET4MR_    = (0x4000 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _NET6MR_    = (0x4004 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _NETMR_     = (0x4008 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _NETMR2_    = (0x4009 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PTMR_      = (0x4100 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PMNR_      = (0x4104 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHAR_      = (0x4108 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PSIDR_     = (0x4110 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PMRUR_     = (0x4114 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SHAR_      = (0x4120 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _GAR_       = (0x4130 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _GA4R_      = _GAR_;
+constexpr uint32_t _SUBR_      = (0x4134 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SUB4R_     = _SUBR_;
+constexpr uint32_t _SIPR_      = (0x4138 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SIP4R_     = _SIPR_;
+constexpr uint32_t _LLAR_      = (0x4140 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _GUAR_      = (0x4150 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SUB6R_     = (0x4160 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _GA6R_      = (0x4170 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLDIP6R_   = (0x4180 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLDIPR_    = (0x418C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLDIP4R_   = _SLDIPR_;
+constexpr uint32_t _SLDHAR_    = (0x4190 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PINGIDR_   = (0x4198 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PINGSEQR_  = (0x419C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _UIPR_      = (0x41A0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _UIP4R_     = _UIPR_;
+constexpr uint32_t _UPORTR_    = (0x41A4 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _UPORT4R_   = _UPORTR_;
+constexpr uint32_t _UIP6R_     = (0x41B0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _UPORT6R_   = (0x41C0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _INTPTMR_   = (0x41C5 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PLR_       = (0x41D0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PFR_       = (0x41D4 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _VLTR_      = (0x41D8 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PLTR_      = (0x41DC << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PAR_       = (0x41E0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _ICMP6BLKR_ = (0x41F0 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _CHPLCKR_   = (0x41F4 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _NETLCKR_   = (0x41F5 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _PHYLCKR_   = (0x41F6 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _RTR_       = (0x4200 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _RCR_       = (0x4204 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLRTR_     = (0x4208 << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLRCR_     = (0x420C << 8) + WIZCHIP_CREG_BLOCK;
+constexpr uint32_t _SLHOPR_    = (0x420F << 8) + WIZCHIP_CREG_BLOCK;
 
-#define _SYCR1_              (WIZCHIP_OFFSET_INC(_SYCR0_,1))
-#define _TCNTR_              ((0x2016 << 8) + WIZCHIP_CREG_BLOCK)
-#define _TCNTRCLR_           ((0x2020 << 8) + WIZCHIP_CREG_BLOCK)
-#define _IR_                 ((0x2100 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SIR_                ((0x2101 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLIR_               ((0x2102 << 8) + WIZCHIP_CREG_BLOCK)
-#define _IMR_                ((0x2104 << 8) + WIZCHIP_CREG_BLOCK)
-#define _IRCLR_              ((0x2108 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SIMR_               ((0x2114 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLIMR_              ((0x2124 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLIRCLR_            ((0x2128 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLPSR_              ((0x212C << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLCR_               ((0x2130 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYSR_              ((0x3000 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYRAR_             ((0x3008 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYDIR_             ((0x300C << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYDOR_             ((0x3010 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYACR_             ((0x3014 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYDIVR_            ((0x3018 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYCR0_             ((0x301C << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYCR1_             WIZCHIP_OFFSET_INC(_PHYCR0_,1)
-#define _NET4MR_             ((0x4000 << 8) + WIZCHIP_CREG_BLOCK)
-#define _NET6MR_             ((0x4004 << 8) + WIZCHIP_CREG_BLOCK)
-#define _NETMR_              ((0x4008 << 8) + WIZCHIP_CREG_BLOCK)
-#define _NETMR2_             ((0x4009 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PTMR_               ((0x4100 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PMNR_               ((0x4104 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHAR_               ((0x4108 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PSIDR_              ((0x4110 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PMRUR_              ((0x4114 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SHAR_               ((0x4120 << 8) + WIZCHIP_CREG_BLOCK)
-#define _GAR_                ((0x4130 << 8) + WIZCHIP_CREG_BLOCK)
-#define _GA4R_               (_GAR_)
-#define _SUBR_               ((0x4134 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SUB4R_              (_SUBR_)
-
-#define _SIPR_               ((0x4138 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SIP4R_              (_SIPR_)
-#define _LLAR_               ((0x4140 << 8) + WIZCHIP_CREG_BLOCK)
-#define _GUAR_               ((0x4150 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SUB6R_              ((0x4160 << 8) + WIZCHIP_CREG_BLOCK)
-#define _GA6R_               ((0x4170 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLDIP6R_            ((0x4180 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLDIPR_             ((0x418C << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLDIP4R_            (_SLDIPR_)
-#define _SLDHAR_             ((0x4190 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PINGIDR_            ((0x4198 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PINGSEQR_           ((0x419C << 8) + WIZCHIP_CREG_BLOCK)
-#define _UIPR_               ((0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _UIP4R_              (_UIPR_)
-#define _UPORTR_             ((0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
-#define _UPORT4R_            (_UPORTR_)
-#define _UIP6R_              ((0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _UPORT6R_            ((0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _INTPTMR_            ((0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PLR_                ((0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PFR_                ((0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
-#define _VLTR_               ((0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PLTR_               ((0x41DC << 8) + WIZCHIP_CREG_BLOCK)
-#define _PAR_                ((0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _ICMP6BLKR_          ((0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
-#define _CHPLCKR_            ((0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
-#define _NETLCKR_            ((0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
-#define _PHYLCKR_            ((0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
-#define _RTR_                ((0x4200 << 8) + WIZCHIP_CREG_BLOCK)
-#define _RCR_                ((0x4204 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLRTR_              ((0x4208 << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLRCR_              ((0x420C << 8) + WIZCHIP_CREG_BLOCK)
-#define _SLHOPR_             ((0x420F << 8) + WIZCHIP_CREG_BLOCK)
-
-#define _Sn_MR_(N)           ((0x0000 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_PSR_(N)          ((0x0004 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_CR_(N)           ((0x0010 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_IR_(N)           ((0x0020 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_IMR_(N)          ((0x0024 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_IRCLR_(N)        ((0x0028 << 8) + WIZCHIP_SREG_BLOCK(N))
-
-
-
-#define _Sn_SR_(N)           ((0x0030 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_ESR_(N)          ((0x0031 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_PNR_(N)          ((0x0100 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_NHR_(N)          (_Sn_PNR_(N))
-#define _Sn_TOSR_(N)         ((0x0104 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_TTLR_(N)         ((0x0108 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_HOPR_(N)         (_Sn_TTLR_(N))
-#define _Sn_FRGR_(N)         ((0x010C << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_MSSR_(N)         ((0x0110 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_PORTR_(N)        ((0x0114 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_DHAR_(N)         ((0x0118 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_DIPR_(N)         ((0x0120 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_DIP4R_(N)        (_Sn_DIPR_(N))
-#define _Sn_DIP6R_(N)        ((0x0130 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_DPORTR_(N)       ((0x0140 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_MR2_(N)          ((0x0144 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RTR_(N)          ((0x0180 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RCR_(N)          ((0x0184 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_KPALVTR_(N)      ((0x0188 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_TX_BSR_(N)       ((0x0200 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_TX_FSR_(N)       ((0x0204 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_TX_RD_(N)        ((0x0208 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_TX_WR_(N)        ((0x020C << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RX_BSR_(N)       ((0x0220 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RX_RSR_(N)       ((0x0224 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RX_RD_(N)        ((0x0228 << 8) + WIZCHIP_SREG_BLOCK(N))
-#define _Sn_RX_WR_(N)        ((0x022C << 8) + WIZCHIP_SREG_BLOCK(N))
-
-#define SYSR_CHPL            (1 << 7)
-#define SYSR_NETL            (1 << 6)
-#define SYSR_PHYL            (1 << 5)
-
-#define SYSR_IND             (1 << 5)
-#define SYSR_SPI             (1 << 0)
-#define SYCR0_RST            (0x00)
-#define SYCR1_IEN            (1 << 7)
-#define SYCR1_CLKSEL         (1 << 0)
-#define SYCR1_CLKSEL_25M     1
-#define SYCR1_CLKSEL_100M    0
-#define IR_WOL               (1<<7)
-#define IR_UNR6              (1<<4)
-#define IR_IPCONF            (1<<2)
-#define IR_UNR4              (1<<1)
-#define IR_PTERM             (1<<0)
-#define SIR_INT(N)           (1<<N)
-#define SLIR_TOUT            (1<<7)
-#define SLIR_ARP4            (1<<6)
-#define SLIR_PING4           (1<<5)
-#define SLIR_ARP6            (1<<4)
-#define SLIR_PING6           (1<<3)
-#define SLIR_NS              (1<<2)
-#define SLIR_RS              (1<<1)
-#define SLIR_RA              (1<<0)
-#define PSR_AUTO             (0x00)
-#define PSR_LLA              (0x02)
-#define PSR_GUA              (0x03)
-#define SLCR_ARP4            (1<<6)
-#define SLCR_PING4           (1<<5)
-#define SLCR_ARP6            (1<<4)
-#define SLCR_PING6           (1<<3)
-#define SLCR_NS              (1<<2)
-#define SLCR_RS              (1<<1)
-#define SLCR_UNA             (1<<0)
-#define PHYSR_CAB            (1<<7)
-#define PHYSR_CAB_OFF        (1<<7)
-#define PHYSR_CAB_ON         (0<<7)
-#define PHYSR_MODE           (7<<3)
-#define PHYSR_MODE_AUTO      (0<<3)
-
-#define PHYSR_MODE_100F      (4<<3)
-#define PHYSR_MODE_100H      (5<<3)
-#define PHYSR_MODE_10F       (6<<3)
-#define PHYSR_MODE_10H       (7<<3)
-#define PHYSR_DPX            (1<<2)
-#define PHYSR_DPX_HALF       (1<<2)
-#define PHYSR_DPX_FULL       (0<<2)
-#define PHYSR_SPD            (1<<1)
-#define PHYSR_SPD_10M        (1<<1)
-#define PHYSR_SPD_100M       (0<<1)
-#define PHYSR_LNK            (1<<0)
-#define PHYSR_LNK_UP         (1<<0)
-#define PHYSR_LNK_DOWN       (0<<0)
-#define PHYACR_READ          (0x02)
-#define PHYACR_WRITE         (0x01)
-#define PHYDIVR_32           (0x00)
-#define PHYDIVR_64           (0x01)
-#define PHYDIVR_128          (0xFF)
-#define PHYCR0_AUTO          (0x00)
-#define PHYCR0_100F          (0x04)
-#define PHYCR0_100H          (0x05)
-#define PHYCR0_10F           (0x06)
-#define PHYCR0_10H           (0x07)
-#define PHYCR1_PWDN          (1<<5)
-#define PHYCR1_TE            (1<<3)
-#define PHYCR1_RST           (1<<0)
-#define NETxMR_UNRB          (1<<3)
-#define NETxMR_PARP          (1<<2)
-#define NETxMR_RSTB          (1<<1)
-#define NETxMR_PB            (1<<0)
-#define NETMR_ANB            (1<<5)
-#define NETMR_M6B            (1<<4)
-#define NETMR_WOL            (1<<2)
-#define NETMR_IP6B           (1<<1)
-#define NETMR_IP4B           (1<<0)
-#define NETMR2_DHAS          (1<<7)
-#define NETMR2_DHAS_ARP      (1<<7)
-#define NETMR2_DHAS_ETH      (0<<7)
-#define NETMR2_PPPoE         (1<<0)
-#define ICMP6BLKR_PING6      (1<<4)
-#define ICMP6BLKR_MLD        (1<<3)
-#define ICMP6BLKR_RA         (1<<2)
-#define ICMP6BLKR_NA         (1<<1)
-#define ICMP6BLKR_NS         (1<<0)
-#define Sn_MR_MULTI          (1<<7)
-#define Sn_MR_MF             (1<<7)
-#define Sn_MR_BRDB           (1<<6)
-#define Sn_MR_FPSH           (1<<6)
-#define Sn_MR_ND             (1<<5)
-#define Sn_MR_MC             (1<<5)
-#define Sn_MR_SMB            (1<<5)
-#define Sn_MR_MMB            (1<<5)
-#define Sn_MR_MMB4           (Sn_MR_MMB)
-#define Sn_MR_UNIB           (1<<4)
-#define Sn_MR_MMB6           (1<<4)
-#define Sn_MR_CLOSE          (0x00)
-#define Sn_MR_TCP            (0x01)
-#define Sn_MR_TCP4           (Sn_MR_TCP)
-#define Sn_MR_UDP            (0x02)
-#define Sn_MR_UDP4           (Sn_MR_UDP)
-#define Sn_MR_IPRAW          (0x03)
-#define Sn_MR_IPRAW4         (Sn_MR_IPRAW)
-#define Sn_MR_MACRAW         (0x07)
-#define Sn_MR_TCP6           (0x09)
-#define Sn_MR_UDP6           (0x0A)
-#define Sn_MR_IPRAW6         (0x0B)
-#define Sn_MR_TCPD           (0x0D)
-#define Sn_MR_UDPD           (0x0E)
-#define Sn_CR_OPEN           (0x01)
-#define Sn_CR_LISTEN         (0x02)
-#define Sn_CR_CONNECT        (0x04)
-#define Sn_CR_CONNECT6       (0x84)
-#define Sn_CR_DISCON         (0x08)
-#define Sn_CR_CLOSE          (0x10)
-#define Sn_CR_SEND           (0x20)
-#define Sn_CR_SEND6          (0xA0)
-#define Sn_CR_SEND_KEEP      (0x22)
-#define Sn_CR_RECV           (0x40)
-#define Sn_IR_SENDOK         (0x10)
-#define Sn_IR_TIMEOUT        (0x08)
-#define Sn_IR_RECV           (0x04)
-#define Sn_IR_DISCON         (0x02)
-#define Sn_IR_CON            (0x01)
-#define SOCK_CLOSED          (0x00)
-#define SOCK_INIT            (0x13)
-#define SOCK_LISTEN          (0x14)
-#define SOCK_SYNSENT         (0x15)
-#define SOCK_SYNRECV         (0x16)
-#define SOCK_ESTABLISHED     (0x17)
-#define SOCK_FIN_WAIT        (0x18)
-
-#define SOCK_TIME_WAIT       (0x1B)
-#define SOCK_CLOSE_WAIT      (0x1C)
-#define SOCK_LAST_ACK        (0x1D)
-#define SOCK_UDP             (0x22)
-#define SOCK_IPRAW4          (0x32)
-#define SOCK_IPRAW           (SOCK_IPRAW4)
-#define SOCK_IPRAW6          (0x33)
-#define SOCK_MACRAW          (0x42)
-#define Sn_ESR_TCPM          (1<<2)
-#define Sn_ESR_TCPM_IPV4     (0<<2)
-#define Sn_ESR_TCPM_IPV6     (1<<2)
-#define Sn_ESR_TCPOP         (1<<1)
-#define Sn_ESR_TCPOP_SVR     (0<<1)
-#define Sn_ESR_TCPOP_CLT     (1<<1)
-#define Sn_ESR_IP6T          (1<<0)
-#define Sn_ESR_IP6T_LLA      (0<<0)
-#define Sn_ESR_IP6T_GUA      (1<<0)
-#define Sn_MR2_DHAM          (1<<1)
-#define Sn_MR2_DHAM_AUTO     (0<<1)
-#define Sn_MR2_DHAM_MANUAL   (1<<1)
-#define Sn_MR2_FARP          (1<<0)
-#define PHYRAR_BMCR          (0x00)
-#define PHYRAR_BMSR          (0x01)
-#define BMCR_RST             (1<<15)
-#define BMCR_LB              (1<<14)
-#define BMCR_SPD             (1<<13)
-#define BMCR_ANE             (1<<12)
-#define BMCR_PWDN            (1<<11)
-#define BMCR_ISOL            (1<<10)
-#define BMCR_REAN            (1<<9)
-#define BMCR_DPX             (1<<8)
-#define BMCR_COLT            (1<<7)
-#define BMSR_100_T4          (1<<15)
-#define BMSR_100_FDX         (1<<14)
-#define BMSR_100_HDX         (1<<13)
-#define BMSR_10_FDX          (1<<12)
-#define BMSR_10_HDX          (1<<11)
-#define BMSR_MF_SUP          (1<<6)
-#define BMSR_AN_COMP         (1<<5)
-#define BMSR_REMOTE_FAULT    (1<<4)
-#define BMSR_AN_ABILITY      (1<<3)
-#define BMSR_LINK_STATUS     (1<<2)
-#define BMSR_JABBER_DETECT   (1<<1)
-#define BMSR_EXT_CAPA        (1<<0)
+constexpr uint32_t _Sn_MR_(uint8_t n)      { return (0x0000 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_PSR_(uint8_t n)     { return (0x0004 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_CR_(uint8_t n)      { return (0x0010 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_IR_(uint8_t n)      { return (0x0020 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_IMR_(uint8_t n)     { return (0x0024 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_IRCLR_(uint8_t n)   { return (0x0028 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_SR_(uint8_t n)      { return (0x0030 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_ESR_(uint8_t n)     { return (0x0031 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_PNR_(uint8_t n)     { return (0x0100 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_NHR_(uint8_t n)     { return _Sn_PNR_(n); }
+constexpr uint32_t _Sn_TOSR_(uint8_t n)    { return (0x0104 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_TTLR_(uint8_t n)    { return (0x0108 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_HOPR_(uint8_t n)    { return _Sn_TTLR_(n); }
+constexpr uint32_t _Sn_FRGR_(uint8_t n)    { return (0x010C << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_MSSR_(uint8_t n)    { return (0x0110 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_PORTR_(uint8_t n)   { return (0x0114 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_DHAR_(uint8_t n)    { return (0x0118 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_DIPR_(uint8_t n)    { return (0x0120 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_DIP4R_(uint8_t n)   { return _Sn_DIPR_(n); }
+constexpr uint32_t _Sn_DIP6R_(uint8_t n)   { return (0x0130 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_DPORTR_(uint8_t n)  { return (0x0140 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_MR2_(uint8_t n)     { return (0x0144 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RTR_(uint8_t n)     { return (0x0180 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RCR_(uint8_t n)     { return (0x0184 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_KPALVTR_(uint8_t n) { return (0x0188 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_TX_BSR_(uint8_t n)  { return (0x0200 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_TX_FSR_(uint8_t n)  { return (0x0204 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_TX_RD_(uint8_t n)   { return (0x0208 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_TX_WR_(uint8_t n)   { return (0x020C << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RX_BSR_(uint8_t n)  { return (0x0220 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RX_RSR_(uint8_t n)  { return (0x0224 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RX_RD_(uint8_t n)   { return (0x0228 << 8) + WIZCHIP_SREG_BLOCK(n); }
+constexpr uint32_t _Sn_RX_WR_(uint8_t n)   { return (0x022C << 8) + WIZCHIP_SREG_BLOCK(n); }
 
+constexpr uint8_t SYSR_CHPL            = 1 << 7;
+constexpr uint8_t SYSR_NETL            = 1 << 6;
+constexpr uint8_t SYSR_PHYL            = 1 << 5;
+constexpr uint8_t SYSR_IND             = 1 << 5;
+constexpr uint8_t SYSR_SPI             = 1 << 0;
+constexpr uint8_t SYCR0_RST            = 0x00;
+constexpr uint8_t SYCR1_IEN            = 1 << 7;
+constexpr uint8_t SYCR1_CLKSEL         = 1 << 0;
+constexpr uint8_t SYCR1_CLKSEL_25M     = 1;
+constexpr uint8_t SYCR1_CLKSEL_100M    = 0;
+constexpr uint8_t IR_WOL               = 1 << 7;
+constexpr uint8_t IR_UNR6              = 1 << 4;
+constexpr uint8_t IR_IPCONF            = 1 << 2;
+constexpr uint8_t IR_UNR4              = 1 << 1;
+constexpr uint8_t IR_PTERM             = 1 << 0;
+constexpr uint8_t SIR_INT(uint8_t n)   { return 1 << n; }
+constexpr uint8_t SLIR_TOUT            = 1 << 7;
+constexpr uint8_t SLIR_ARP4            = 1 << 6;
+constexpr uint8_t SLIR_PING4           = 1 << 5;
+constexpr uint8_t SLIR_ARP6            = 1 << 4;
+constexpr uint8_t SLIR_PING6           = 1 << 3;
+constexpr uint8_t SLIR_NS              = 1 << 2;
+constexpr uint8_t SLIR_RS              = 1 << 1;
+constexpr uint8_t SLIR_RA              = 1 << 0;
+constexpr uint8_t PSR_AUTO             = 0x00;
+constexpr uint8_t PSR_LLA              = 0x02;
+constexpr uint8_t PSR_GUA              = 0x03;
+constexpr uint8_t SLCR_ARP4            = 1 << 6;
+constexpr uint8_t SLCR_PING4           = 1 << 5;
+constexpr uint8_t SLCR_ARP6            = 1 << 4;
+constexpr uint8_t SLCR_PING6           = 1 << 3;
+constexpr uint8_t SLCR_NS              = 1 << 2;
+constexpr uint8_t SLCR_RS              = 1 << 1;
+constexpr uint8_t SLCR_UNA             = 1 << 0;
+constexpr uint8_t PHYSR_CAB            = 1 << 7;
+constexpr uint8_t PHYSR_CAB_OFF        = 1 << 7;
+constexpr uint8_t PHYSR_CAB_ON         = 0 << 7;
+constexpr uint8_t PHYSR_MODE           = 7 << 3;
+constexpr uint8_t PHYSR_MODE_AUTO      = 0 << 3;
+constexpr uint8_t PHYSR_MODE_100F      = 4 << 3;
+constexpr uint8_t PHYSR_MODE_100H      = 5 << 3;
+constexpr uint8_t PHYSR_MODE_10F       = 6 << 3;
+constexpr uint8_t PHYSR_MODE_10H       = 7 << 3;
+constexpr uint8_t PHYSR_DPX            = 1 << 2;
+constexpr uint8_t PHYSR_DPX_HALF       = 1 << 2;
+constexpr uint8_t PHYSR_DPX_FULL       = 0 << 2;
+constexpr uint8_t PHYSR_SPD            = 1 << 1;
+constexpr uint8_t PHYSR_SPD_10M        = 1 << 1;
+constexpr uint8_t PHYSR_SPD_100M       = 0 << 1;
+constexpr uint8_t PHYSR_LNK            = 1 << 0;
+constexpr uint8_t PHYSR_LNK_UP         = 1 << 0;
+constexpr uint8_t PHYSR_LNK_DOWN       = 0 << 0;
+constexpr uint8_t PHYACR_READ          = 0x02;
+constexpr uint8_t PHYACR_WRITE         = 0x01;
+constexpr uint8_t PHYDIVR_32           = 0x00;
+constexpr uint8_t PHYDIVR_64           = 0x01;
+constexpr uint8_t PHYDIVR_128          = 0xFF;
+constexpr uint8_t PHYCR0_AUTO          = 0x00;
+constexpr uint8_t PHYCR0_100F          = 0x04;
+constexpr uint8_t PHYCR0_100H          = 0x05;
+constexpr uint8_t PHYCR0_10F           = 0x06;
+constexpr uint8_t PHYCR0_10H           = 0x07;
+constexpr uint8_t PHYCR1_PWDN          = 1 << 5;
+constexpr uint8_t PHYCR1_TE            = 1 << 3;
+constexpr uint8_t PHYCR1_RST           = 1 << 0;
+constexpr uint8_t NETxMR_UNRB          = 1 << 3;
+constexpr uint8_t NETxMR_PARP          = 1 << 2;
+constexpr uint8_t NETxMR_RSTB          = 1 << 1;
+constexpr uint8_t NETxMR_PB            = 1 << 0;
+constexpr uint8_t NETMR_ANB            = 1 << 5;
+constexpr uint8_t NETMR_M6B            = 1 << 4;
+constexpr uint8_t NETMR_WOL            = 1 << 2;
+constexpr uint8_t NETMR_IP6B           = 1 << 1;
+constexpr uint8_t NETMR_IP4B           = 1 << 0;
+constexpr uint8_t NETMR2_DHAS          = 1 << 7;
+constexpr uint8_t NETMR2_DHAS_ARP      = 1 << 7;
+constexpr uint8_t NETMR2_DHAS_ETH      = 0 << 7;
+constexpr uint8_t NETMR2_PPPoE         = 1 << 0;
+constexpr uint8_t ICMP6BLKR_PING6      = 1 << 4;
+constexpr uint8_t ICMP6BLKR_MLD        = 1 << 3;
+constexpr uint8_t ICMP6BLKR_RA         = 1 << 2;
+constexpr uint8_t ICMP6BLKR_NA         = 1 << 1;
+constexpr uint8_t ICMP6BLKR_NS         = 1 << 0;
+constexpr uint8_t Sn_MR_MULTI          = 1 << 7;
+constexpr uint8_t Sn_MR_MF             = 1 << 7;
+constexpr uint8_t Sn_MR_BRDB           = 1 << 6;
+constexpr uint8_t Sn_MR_FPSH           = 1 << 6;
+constexpr uint8_t Sn_MR_ND             = 1 << 5;
+constexpr uint8_t Sn_MR_MC             = 1 << 5;
+constexpr uint8_t Sn_MR_SMB            = 1 << 5;
+constexpr uint8_t Sn_MR_MMB            = 1 << 5;
+constexpr uint8_t Sn_MR_MMB4           = Sn_MR_MMB;
+constexpr uint8_t Sn_MR_UNIB           = 1 << 4;
+constexpr uint8_t Sn_MR_MMB6           = 1 << 4;
+constexpr uint8_t Sn_MR_CLOSE          = 0x00;
+constexpr uint8_t Sn_MR_TCP            = 0x01;
+constexpr uint8_t Sn_MR_TCP4           = Sn_MR_TCP;
+constexpr uint8_t Sn_MR_UDP            = 0x02;
+constexpr uint8_t Sn_MR_UDP4           = Sn_MR_UDP;
+constexpr uint8_t Sn_MR_IPRAW          = 0x03;
+constexpr uint8_t Sn_MR_IPRAW4         = Sn_MR_IPRAW;
+constexpr uint8_t Sn_MR_MACRAW         = 0x07;
+constexpr uint8_t Sn_MR_TCP6           = 0x09;
+constexpr uint8_t Sn_MR_UDP6           = 0x0A;
+constexpr uint8_t Sn_MR_IPRAW6         = 0x0B;
+constexpr uint8_t Sn_MR_TCPD           = 0x0D;
+constexpr uint8_t Sn_MR_UDPD           = 0x0E;
+constexpr uint8_t Sn_CR_OPEN           = 0x01;
+constexpr uint8_t Sn_CR_LISTEN         = 0x02;
+constexpr uint8_t Sn_CR_CONNECT        = 0x04;
+constexpr uint8_t Sn_CR_CONNECT6       = 0x84;
+constexpr uint8_t Sn_CR_DISCON         = 0x08;
+constexpr uint8_t Sn_CR_CLOSE          = 0x10;
+constexpr uint8_t Sn_CR_SEND           = 0x20;
+constexpr uint8_t Sn_CR_SEND6          = 0xA0;
+constexpr uint8_t Sn_CR_SEND_KEEP      = 0x22;
+constexpr uint8_t Sn_CR_RECV           = 0x40;
+constexpr uint8_t Sn_IR_SENDOK         = 0x10;
+constexpr uint8_t Sn_IR_TIMEOUT        = 0x08;
+constexpr uint8_t Sn_IR_RECV           = 0x04;
+constexpr uint8_t Sn_IR_DISCON         = 0x02;
+constexpr uint8_t Sn_IR_CON            = 0x01;
+constexpr uint8_t SOCK_CLOSED          = 0x00;
+constexpr uint8_t SOCK_INIT            = 0x13;
+constexpr uint8_t SOCK_LISTEN          = 0x14;
+constexpr uint8_t SOCK_SYNSENT         = 0x15;
+constexpr uint8_t SOCK_SYNRECV         = 0x16;
+constexpr uint8_t SOCK_ESTABLISHED     = 0x17;
+constexpr uint8_t SOCK_FIN_WAIT        = 0x18;
+constexpr uint8_t SOCK_TIME_WAIT       = 0x1B;
+constexpr uint8_t SOCK_CLOSE_WAIT      = 0x1C;
+constexpr uint8_t SOCK_LAST_ACK        = 0x1D;
+constexpr uint8_t SOCK_UDP             = 0x22;
+constexpr uint8_t SOCK_IPRAW4          = 0x32;
+constexpr uint8_t SOCK_IPRAW           = SOCK_IPRAW4;
+constexpr uint8_t SOCK_IPRAW6          = 0x33;
+constexpr uint8_t SOCK_MACRAW          = 0x42;
+constexpr uint8_t Sn_ESR_TCPM          = 1 << 2;
+constexpr uint8_t Sn_ESR_TCPM_IPV4     = 0 << 2;
+constexpr uint8_t Sn_ESR_TCPM_IPV6     = 1 << 2;
+constexpr uint8_t Sn_ESR_TCPOP         = 1 << 1;
+constexpr uint8_t Sn_ESR_TCPOP_SVR     = 0 << 1;
+constexpr uint8_t Sn_ESR_TCPOP_CLT     = 1 << 1;
+constexpr uint8_t Sn_ESR_IP6T          = 1 << 0;
+constexpr uint8_t Sn_ESR_IP6T_LLA      = 0 << 0;
+constexpr uint8_t Sn_ESR_IP6T_GUA      = 1 << 0;
+constexpr uint8_t Sn_MR2_DHAM          = 1 << 1;
+constexpr uint8_t Sn_MR2_DHAM_AUTO     = 0 << 1;
+constexpr uint8_t Sn_MR2_DHAM_MANUAL   = 1 << 1;
+constexpr uint8_t Sn_MR2_FARP          = 1 << 0;
+constexpr uint8_t PHYRAR_BMCR          = 0x00;
+constexpr uint8_t PHYRAR_BMSR          = 0x01;
+constexpr uint16_t BMCR_RST            = 1 << 15;
+constexpr uint16_t BMCR_LB             = 1 << 14;
+constexpr uint16_t BMCR_SPD            = 1 << 13;
+constexpr uint16_t BMCR_ANE            = 1 << 12;
+constexpr uint16_t BMCR_PWDN           = 1 << 11;
+constexpr uint16_t BMCR_ISOL           = 1 << 10;
+constexpr uint16_t BMCR_REAN           = 1 << 9;
+constexpr uint16_t BMCR_DPX            = 1 << 8;
+constexpr uint16_t BMCR_COLT           = 1 << 7;
+constexpr uint16_t BMSR_100_T4         = 1 << 15;
+constexpr uint16_t BMSR_100_FDX        = 1 << 14;
+constexpr uint16_t BMSR_100_HDX        = 1 << 13;
+constexpr uint16_t BMSR_10_FDX         = 1 << 12;
+constexpr uint16_t BMSR_10_HDX         = 1 << 11;
+constexpr uint16_t BMSR_MF_SUP         = 1 << 6;
+constexpr uint16_t BMSR_AN_COMP        = 1 << 5;
+constexpr uint16_t BMSR_REMOTE_FAULT   = 1 << 4;
+constexpr uint16_t BMSR_AN_ABILITY     = 1 << 3;
+constexpr uint16_t BMSR_LINK_STATUS    = 1 << 2;
+constexpr uint16_t BMSR_JABBER_DETECT  = 1 << 1;
+constexpr uint16_t BMSR_EXT_CAPA       = 1 << 0;
 
 void wizchip_cris_enter();
 void wizchip_cris_exit();
-#define WIZCHIP_CRITICAL_ENTER()       wizchip_cris_enter()
-#define WIZCHIP_CRITICAL_EXIT()        wizchip_cris_exit()
+inline void WIZCHIP_CRITICAL_ENTER() { wizchip_cris_enter(); }
+inline void WIZCHIP_CRITICAL_EXIT()  { wizchip_cris_exit(); }
 
 uint8_t WIZCHIP_READ(uint32_t AddrSel);
 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb);
 void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, datasize_t len);
 
-#define getRTL() \
-        WIZCHIP_READ(_RTL_)
-
-#define getCIDR() \
-        ((((uint16_t)WIZCHIP_READ(_CIDR_)| (((WIZCHIP_READ(_RTL_))&0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_,1)))
-
-#define getVER() \
-        ((((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_,1)))
-
-#define getSYSR() \
-        WIZCHIP_READ(_SYSR_)
-
-#define getSYCR0() \
-        WIZCHIP_READ(_SYCR0_)
-
-#define setSYCR0(sycr0) \
-        WIZCHIP_WRITE(_SYCR0_, (sycr0))
-
-#define getSYCR1() \
-        WIZCHIP_READ(_SYCR1_)
-
-#define setSYCR1(sycr1) \
-        WIZCHIP_WRITE(_SYCR1_, (sycr1))
-
-#define getTCNTR() \
-        ((((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_,1)))
-
-#define setTCNTRCLR(tcntrclr) \
-        WIZCHIP_WRITE(_TCNTRCLR_,(tcntrclr))
-
-#define getIR() \
-        WIZCHIP_READ(_IR_)
-
-#define getSIR() \
-        WIZCHIP_READ(_SIR_)
-
-#define getSLIR() \
-        WIZCHIP_READ(_SLIR_)
-
-#define setIMR(imr) \
-        WIZCHIP_WRITE(_IMR_,(imr))
-
-#define getIMR() \
-        WIZCHIP_READ(_IMR_)
-
-#define setIRCLR(irclr) \
-        WIZCHIP_WRITE(_IRCLR_,(irclr))
-#define setIR(ir)                setIRCLR(ir)
-
-#define setSIMR(simr) \
-        WIZCHIP_WRITE(_SIMR_,(simr))
-
-#define getSIMR() \
-        WIZCHIP_READ(_SIMR_)
-
-#define setSLIMR(slimr) \
-        WIZCHIP_WRITE(_SLIMR_,(slimr))
-
-#define getSLIMR() \
-        WIZCHIP_READ(_SLIMR_)
-
-#define setSLIRCLR(slirclr) \
-        WIZCHIP_WRITE(_SLIRCLR_,(slirclr))
-#define setSLIR(slir)            setSLIRCLR(slir)
-
-#define setSLPSR(slpsr) \
-        WIZCHIP_WRITE(_SLPSR_,(slpsr))
-
-#define getSLPSR() \
-        WIZCHIP_READ(_SLPSR_)
-
-#define setSLCR(slcr) \
-        WIZCHIP_WRITE(_SLCR_,(slcr))
-
-#define getSLCR()      \
-        WIZCHIP_READ(_SLCR_)
-
-#define getPHYSR() \
-        WIZCHIP_READ(_PHYSR_)
-
-#define setPHYRAR(phyrar) \
-        WIZCHIP_WRITE(_PHYRAR_,(phyrar))
-
-#define getPHYRAR() \
-        WIZCHIP_READ(_PHYRAR_)
-
-#define setPHYDIR(phydir)  \
-        do{                                                                       \
-           WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_,1), (uint8_t)((phydir)>>8)); \
-           WIZCHIP_WRITE(_PHYDIR_, (uint8_t)(phydir));                            \
-        }while(0);
-
-#define getPHYDOR() \
-        ((((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_,1))) << 8) + WIZCHIP_READ(_PHYDOR_))
-
-#define setPHYACR(phyacr) \
-        WIZCHIP_WRITE(_PHYACR_,(phyacr))
-
-#define getPHYACR() \
-        WIZCHIP_READ(_PHYACR_)
-
-#define setPHYDIVR(phydivr) \
-        WIZCHIP_WRITE(_PHYDIVR_,(phydivr))
-
-#define getPHYDIVR() \
-        WIZCHIP_READ(_PHYDIVR_)
-
-#define setPHYCR0(phycr0) \
-        WIZCHIP_WRITE(_PHYCR0_,(phycr0))
-
-#define setPHYCR1(phycr1) \
-        WIZCHIP_WRITE(_PHYCR1_,(phycr1))
-
-#define getPHYCR1() \
-        WIZCHIP_READ(_PHYCR1_)
-
-#define setNET4MR(net4mr) \
-        WIZCHIP_WRITE(_NET4MR_,(net4mr))
-
-#define setNET6MR(net6mr) \
-        WIZCHIP_WRITE(_NET6MR_,(net6mr))
-
-#define setNETMR(netmr) \
-        WIZCHIP_WRITE(_NETMR_,(netmr))
-
-#define setNETMR2(netmr2) \
-        WIZCHIP_WRITE(_NETMR2_,(netmr2))
-
-#define getNET4MR() \
-        WIZCHIP_READ(_NET4MR_)
-
-#define getNET6MR() \
-        WIZCHIP_READ(_NET6MR_)
-
-#define getNETMR() \
-        WIZCHIP_READ(_NETMR_)
-
-#define getNETMR2() \
-        WIZCHIP_READ(_NETMR2_)
-
-#define setPTMR(ptmr) \
-        WIZCHIP_WRITE(_PTMR_, (ptmr))
-
-#define getPTMR() \
-        WIZCHIP_READ(_PTMR_)
-
-#define setPMNR(pmnr) \
-        WIZCHIP_WRITE(_PMNR_, (pmnr))
-
-#define getPMNR() \
-        WIZCHIP_READ(_PMNR_)
-
-#define setPHAR(phar) \
-        WIZCHIP_WRITE_BUF(_PHAR_,(phar),6)
-
-#define getPHAR(phar) \
-        WIZCHIP_READ_BUF(_PHAR_,(phar),6)
-
-#define setPSIDR(psidr) \
-        do{                                                                \
-            WIZCHIP_WRITE(_PSIDR_,(uint8_t)((psidr) >> 8));                \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_,1),(uint8_t)(psidr)); \
-        }while(0);
-
-#define getPSIDR() \
-        ((((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_,1)))
-
-#define setPMRUR(pmrur) \
-        do{                                                                \
-            WIZCHIP_WRITE(_PMRUR_,(uint8_t)((pmrur) >> 8));                \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_,1),(uint8_t)(pmrur)); \
-        }while(0);
-
-#define getPMRUR() \
-        ((((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_,1)))
-
-#define setSHAR(shar) \
-        WIZCHIP_WRITE_BUF(_SHAR_,(shar),6)
-
-#define getSHAR(shar) \
-        WIZCHIP_READ_BUF(_SHAR_,(shar),6)
-
-#define setGAR(gar) \
-        WIZCHIP_WRITE_BUF(_GAR_,(gar),4)
-
-#define getGAR(gar) \
-        WIZCHIP_READ_BUF(_GAR_,(gar),4)
-
-#define setGA4R(ga4r)            setGAR(ga4r)
-#define getGA4R(ga4r)            getGAR(ga4r)
-
-#define setSUBR(subr) \
-        WIZCHIP_WRITE_BUF(_SUBR_,(subr),4)
-
-#define getSUBR(subr) \
-        WIZCHIP_READ_BUF(_SUBR_,(subr),4)
-
-#define setSUB4R(sub4r)          setSUBR(sub4r)
-#define getSUB4R(sub4r)          getSUBR(sub4r)
-
-#define setSIPR(sipr) \
-        WIZCHIP_WRITE_BUF(_SIPR_,(sipr),4)
-
-#define getSIPR(sipr) \
-        WIZCHIP_READ_BUF(_SIPR_,(sipr),4)
-
-#define setLLAR(llar) \
-        WIZCHIP_WRITE_BUF(_LLAR_,(llar),16)
-
-#define getLLAR(llar) \
-        WIZCHIP_READ_BUF(_LLAR_,(llar),16)
-
-#define setGUAR(guar) \
-        WIZCHIP_WRITE_BUF(_GUAR_,(guar),16)
-
-#define getGUAR(guar) \
-        WIZCHIP_READ_BUF(_GUAR_,(guar),16)
-
-#define setSUB6R(sub6r) \
-        WIZCHIP_WRITE_BUF(_SUB6R_,(sub6r),16)
-
-#define getSUB6R(sub6r) \
-        WIZCHIP_READ_BUF(_SUB6R_,(sub6r),16)
-
-#define setGA6R(ga6r) \
-        WIZCHIP_WRITE_BUF(_GA6R_,(ga6r),16)
-
-#define getGA6R(ga6r) \
-        WIZCHIP_READ_BUF(_GA6R_,(ga6r),16)
-
-#define setSLDIPR(sldipr) \
-        WIZCHIP_WRITE_BUF(_SLDIPR_,(sldipr),4)
-#define setSLDIP4R(sldip4r)      setSLDIPR((sldip4r))
-
-#define getSLDIPR(sldipr) \
-        WIZCHIP_READ_BUF(_SLDIPR_,(sldipr),4)
-#define getSLDIP4R(sldip4r)      getSLDIPR((sldip4r))
-
-#define setSLDIP6R(sldip6r) \
-        WIZCHIP_WRITE_BUF(_SLDIP6R_, (sldip6r),16)
-
-#define getSLDIP6R(sldip6r) \
-        WIZCHIP_READ_BUF(_SLDIP6R_,(sldip6r),16)
-
-#define getSLDHAR(sldhar) \
-        WIZCHIP_READ_BUF(_SLDHAR_,(sldhar),6)
-
-#define setPINGIDR(pingidr) \
-        do{                                                                    \
-            WIZCHIP_WRITE(_PINGIDR_,(uint8_t)((pingidr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_,1),(uint8_t)(pingidr)); \
-        }while(0);
-
-#define getPINGIDR() \
-        (((int16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_,1)))
-
-#define setPINGSEQR(pingseqr) \
-        do{                                                                      \
-            WIZCHIP_WRITE(_PINGSEQR_,(uint8_t)((pingseqr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_,1),(uint8_t)(pingseqr)); \
-        }while(0);
-
-#define getPINGSEQR() \
-        (((int16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_,1)))
-
-#define getUIPR(uipr) \
-        WIZCHIP_READ_BUF(_UIPR_, (uipr), 4)
-
-#define getUIP4R(uip4r)          getUIPR(uip4r)
-
-#define getUPORTR() \
-        ((((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_,1)))
-
-#define getUPORT4R()             getUPORTR()
-
-#define getUIP6R(uip6r) \
-        WIZCHIP_READ_BUF(_UIP6R_,(uip6r),16)
-
-#define getUPORT6R(uport6r) \
-        ((((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_,1)))
-
-#define setINTPTMR(intptmr) \
-        do{                                                                     \
-            WIZCHIP_WRITE(_INTPTMR_,(uint8_t)((intptmr) >> 8));                 \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_,1),(uint8_t)(intptmr));  \
-       }while(0);
-
-#define getINTPTMR() \
-        ((((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_,1)))
-
-#define getPLR() \
-        WIZCHIP_READ(_PLR_)
-
-#define getPFR() \
-        WIZCHIP_READ(_PFR_)
-
-#define getVLTR() \
-        ( (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) +                       \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,1))) << 16) + \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,2))) << 16) + \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_,3))) << 16) )
-
-#define getPLTR() \
-        ( (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) +                       \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,1))) << 16) + \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,2))) << 16) + \
-          (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_,3))) << 16) )
-
-#define getPAR(par) \
-        WIZCHIP_READ_BUF(_PAR_, (par), 16)
-
-#define setICMP6BLKR(icmp6blkr) \
-        WIZCHIP_WRITE(_ICMP6BLKR_,(icmp6blkr))
-
-#define getICMP6BLKR() \
-        WIZCHIP_READ(_ICMP6BLKR_)
-
-#define setCHPLCKR(chplckr) \
-        WIZCHIP_WRITE(_CHPLCKR_, (chplckr))
-
-#define getCHPLCKR() \
-        ((getSYSR() & SYSR_CHPL) >> 7)
-
-#define CHIPLOCK()      setCHPLCKR(0xFF)
-#define CHIPUNLOCK()    setCHPLCKR(0xCE)
-
-#define setNETLCKR(netlckr) \
-        WIZCHIP_WRITE(_NETLCKR_, (netlckr))
-
-#define getNETLCKR() \
-        ((getSYSR() & SYSR_NETL) >> 6)
-
-#define NETLOCK()      setNETLCKR(0xC5)
-#define NETUNLOCK()    setNETLCKR(0x3A)
-
-#define setPHYLCKR(phylckr) \
-        WIZCHIP_WRITE(_PHYLCKR_,(phylckr))
-
-#define getPHYLCKR() \
-        ((getSYSR() & SYSR_PHYL) >> 5)
-
-#define PHYLOCK()      setPHYLCKR(0xFF)
-#define PHYUNLOCK()    setPHYLCKR(0x53)
-
-#define setRTR(rtr) \
-        do{                                                            \
-            WIZCHIP_WRITE(_RTR_,(uint8_t)((rtr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1),(uint8_t)(rtr)); \
-        }while(0);
-
-#define getRTR() \
-        ((((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
-
-#define setRCR(rcr) \
-        WIZCHIP_WRITE(_RCR_,(rcr))
-
-#define getRCR() \
-        WIZCHIP_READ(_RCR_)
-
-#define setSLRTR(slrtr) \
-        do{                                                                \
-            WIZCHIP_WRITE(_SLRTR_,(uint8_t)((slrtr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_,1),(uint8_t)(slrtr)); \
-        }while(0);
-
-#define getSLRTR() \
-        ((((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_,1)))
-
-#define setSLRCR(slrcr) \
-        WIZCHIP_WRITE(_SLRCR_,(slrcr))
-
-#define getSLRCR() \
-        WIZCHIP_READ(_SLRCR_)
-
-#define setSLHOPR(slhopr) \
-        WIZCHIP_WRITE(_SLHOPR_,(slhopr))
-
-#define getSLHOPR() \
-        WIZCHIP_READ(_SLHOPR_)
-/**
-    @}
-*/
-
-
-////////////////////////////////////
-// SOCKETn  register I/O function //
-////////////////////////////////////
-/**
-    @addtogroup Socket_register_access_function_W6300
-    @{
-*/
-#define setSn_MR(sn,mr) \
-        WIZCHIP_WRITE(_Sn_MR_(sn),(mr))
-#define getSn_MR(sn) \
-        WIZCHIP_READ(_Sn_MR_(sn))
-
-#define setSn_PSR(sn,psr) \
-        WIZCHIP_WRITE(_Sn_PSR_(sn),(psr))
-#define getSn_PSR(sn) \
-        WIZCHIP_READ(_Sn_PSR_(sn))
-
-#define setSn_CR(sn,cr) \
-        WIZCHIP_WRITE(_Sn_CR_(sn),(cr))
-#define getSn_CR(sn) \
-        WIZCHIP_READ(_Sn_CR_(sn))
-
-#define getSn_IR(sn) \
-        WIZCHIP_READ(_Sn_IR_(sn))
-
-#define setSn_IMR(sn,imr) \
-        WIZCHIP_WRITE(_Sn_IMR_(sn),(imr))
-#define getSn_IMR(sn) \
-        WIZCHIP_READ(_Sn_IMR_(sn))
-
-#define setSn_IRCLR(sn,irclr) \
-        WIZCHIP_WRITE(_Sn_IRCLR_(sn),(irclr))
-#define setSn_IR(sn,ir)          setSn_IRCLR(sn,(ir))
-
-#define getSn_SR(sn) \
-        WIZCHIP_READ(_Sn_SR_(sn))
-
-#define getSn_ESR(sn) \
-        WIZCHIP_READ(_Sn_ESR_(sn))
-
-#define setSn_PNR(sn,pnr) \
-        WIZCHIP_WRITE(_Sn_PNR_(sn),(pnr))
-#define setSn_NHR(sn,nhr)        setSn_PNR(_Sn_PNR_(sn),(nhr))
-
-#define getSn_PNR(sn) \
-        WIZCHIP_READ(_Sn_PNR_(sn))
-#define getSn_NHR(sn)            getSn_PNR(sn)
-
-#define setSn_TOSR(sn,tosr) \
-        WIZCHIP_WRITE(_Sn_TOSR_(sn),(tosr))
-#define getSn_TOSR(sn) \
-        WIZCHIP_READ(_Sn_TOSR_(sn))
-#define getSn_TOS(sn)   getSn_TOSR(sn)    ///< For compatible ioLibrar
-#define setSn_TOS(sn,tos)  setSn_TOSR(sn,tos)   ///< For compatible ioLibrar
-
-
-#define setSn_TTLR(sn,ttlr) \
-        WIZCHIP_WRITE(_Sn_TTLR_(sn),(ttlr))
-#define getSn_TTLR(sn) \
-        WIZCHIP_READ(_Sn_TTLR_(sn))
-#define setSn_TTL(sn,ttl)       setSn_TTLR(sn,ttl)   ///< For compatible ioLibrary
-#define getSn_TTL(sn)           getSn_TTLR(sn)   ///< For compatible ioLibrary
-
-#define setSn_HOPR(sn,hopr)      setSn_TTLR(sn),(ttlr))
-#define getSn_HOPR(sn)           getSn_TTLR(sn)
-
-#define setSn_FRGR(sn,frgr) \
-        do{                                                                      \
-            WIZCHIP_WRITE(_Sn_FRGR_(sn),(uint8_t)((frgr)>>8));                   \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1),(uint8_t)(frgr));  \
-        }while(0);
-#define getSn_FRGR(sn,frgr) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1)))
-
-#define setSn_MSSR(sn,mssr) \
-        do{                                                                      \
-            WIZCHIP_WRITE(_Sn_MSSR_(sn),(uint8_t)((mssr)>>8));                   \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1),(uint8_t)(mssr));  \
-        }while(0);
-#define getSn_MSSR(sn) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1)))
-
-#define setSn_PORTR(sn,portr) \
-        do{                                                                       \
-            WIZCHIP_WRITE(_Sn_PORTR_(sn),(uint8_t)((portr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1),(uint8_t)(portr)); \
-        }while(0);
-#define getSn_PORTR(sn) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1)))
-
-#define setSn_DHAR(sn,dhar) \
-        WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn),(dhar),6)
-#define getSn_DHAR(sn,dhar) \
-        WIZCHIP_READ_BUF(_Sn_DHAR_(sn),(dhar),6)
-
-#define setSn_DIPR(sn,dipr) \
-        WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn),(dipr),4)
-#define getSn_DIPR(sn,dipr) \
-        WIZCHIP_READ_BUF(_Sn_DIPR_(sn),(dipr),4)
-
-#define setSn_DIP4R(sn,dipr)      setSn_DIPR(sn,(dipr))
-#define getSn_DIP4R(sn,dipr)      getSn_DIPR(sn,(dipr))
-
-#define setSn_DIP6R(sn,dip6r) \
-        WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn),(dip6r),16)
-#define getSn_DIP6R(sn,dip6r) \
-        WIZCHIP_READ_BUF(_Sn_DIP6R_(sn),(dip6r),16)
-
-#define setSn_DPORTR(sn,dportr) \
-        do{                                                                         \
-            WIZCHIP_WRITE(_Sn_DPORTR_(sn),(uint8_t)((dportr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1),(uint8_t)(dportr)); \
-        }while(0);
-
-
-#define getSn_DPORTR(sn) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1)))
-
-#define getSn_DPORT(sn) getSn_DPORTR(sn)
-#define setSn_DPORT(sn,dportr)  setSn_DPORTR(sn,dportr)
-
-
-#define setSn_MR2(sn,mr2) \
-        WIZCHIP_WRITE(_Sn_MR2_(sn),(mr2))
-#define getSn_MR2(sn) \
-        WIZCHIP_READ(_Sn_MR2_(sn))
-
-#define setSn_RTR(sn,rtr) \
-        do{                                                                   \
-            WIZCHIP_WRITE(_Sn_RTR_(sn),(uint8_t)((rtr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1),(uint8_t)(rtr)); \
-        }while(0);
-#define getSn_RTR(sn) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1)))
-
-#define setSn_RCR(sn,rcr) \
-        WIZCHIP_WRITE(_Sn_RCR_(sn),(rcr))
-#define getSn_RCR(sn) \
-        WIZCHIP_READ(_Sn_RCR_(sn))
-
-#define setSn_KPALVTR(sn,kpalvtr) \
-        WIZCHIP_WRITE(_Sn_KPALVTR_(sn),(kpalvtr))
-#define getSn_KPALVTR(sn) \
-        WIZCHIP_READ(_Sn_KPALVTR_(sn))
-
-#define setSn_TX_BSR(sn, tmsr) \
-        WIZCHIP_WRITE(_Sn_TX_BSR_(sn),(tmsr))
-#define setSn_TXBUF_SIZE(sn, tmsr)      setSn_TX_BSR(sn,(tmsr))
-
-#define getSn_TX_BSR(sn) \
-        WIZCHIP_READ(_Sn_TX_BSR_(sn))
-#define getSn_TXBUF_SIZE(sn)            getSn_TX_BSR(sn)
-
-#define getSn_TxMAX(sn) \
-	  (getSn_TX_BSR(sn) << 10)
+inline uint8_t getRTL() { return WIZCHIP_READ(_RTL_); }
+inline uint16_t getCIDR() { return (((uint16_t)WIZCHIP_READ(_CIDR_) | (((WIZCHIP_READ(_RTL_)) & 0x0F) << 1)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_, 1)); }
+inline uint16_t getVER() { return (((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_, 1)); }
+inline uint8_t getSYSR() { return WIZCHIP_READ(_SYSR_); }
+inline uint8_t getSYCR0() { return WIZCHIP_READ(_SYCR0_); }
+inline void setSYCR0(uint8_t v) { WIZCHIP_WRITE(_SYCR0_, v); }
+inline uint8_t getSYCR1() { return WIZCHIP_READ(_SYCR1_); }
+inline void setSYCR1(uint8_t v) { WIZCHIP_WRITE(_SYCR1_, v); }
+inline uint16_t getTCNTR() { return (((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_, 1)); }
+inline void setTCNTRCLR(uint8_t v) { WIZCHIP_WRITE(_TCNTRCLR_, v); }
+inline uint8_t getIR() { return WIZCHIP_READ(_IR_); }
+inline uint8_t getSIR() { return WIZCHIP_READ(_SIR_); }
+inline uint8_t getSLIR() { return WIZCHIP_READ(_SLIR_); }
+inline void setIMR(uint8_t v) { WIZCHIP_WRITE(_IMR_, v); }
+inline uint8_t getIMR() { return WIZCHIP_READ(_IMR_); }
+inline void setIRCLR(uint8_t v) { WIZCHIP_WRITE(_IRCLR_, v); }
+inline void setIR(uint8_t v) { setIRCLR(v); }
+inline void setSIMR(uint8_t v) { WIZCHIP_WRITE(_SIMR_, v); }
+inline uint8_t getSIMR() { return WIZCHIP_READ(_SIMR_); }
+inline void setSLIMR(uint8_t v) { WIZCHIP_WRITE(_SLIMR_, v); }
+inline uint8_t getSLIMR() { return WIZCHIP_READ(_SLIMR_); }
+inline void setSLIRCLR(uint8_t v) { WIZCHIP_WRITE(_SLIRCLR_, v); }
+inline void setSLIR(uint8_t v) { setSLIRCLR(v); }
+inline void setSLPSR(uint8_t v) { WIZCHIP_WRITE(_SLPSR_, v); }
+inline uint8_t getSLPSR() { return WIZCHIP_READ(_SLPSR_); }
+inline void setSLCR(uint8_t v) { WIZCHIP_WRITE(_SLCR_, v); }
+inline uint8_t getSLCR() { return WIZCHIP_READ(_SLCR_); }
+inline uint8_t getPHYSR() { return WIZCHIP_READ(_PHYSR_); }
+inline void setPHYRAR(uint8_t v) { WIZCHIP_WRITE(_PHYRAR_, v); }
+inline uint8_t getPHYRAR() { return WIZCHIP_READ(_PHYRAR_); }
+inline void setPHYDIR(uint16_t v) {
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PHYDIR_, 1), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(_PHYDIR_, (uint8_t)v);
+}
+inline uint16_t getPHYDOR() { return (((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_, 1))) << 8) + WIZCHIP_READ(_PHYDOR_); }
+inline void setPHYACR(uint8_t v) { WIZCHIP_WRITE(_PHYACR_, v); }
+inline uint8_t getPHYACR() { return WIZCHIP_READ(_PHYACR_); }
+inline void setPHYDIVR(uint8_t v) { WIZCHIP_WRITE(_PHYDIVR_, v); }
+inline uint8_t getPHYDIVR() { return WIZCHIP_READ(_PHYDIVR_); }
+inline void setPHYCR0(uint8_t v) { WIZCHIP_WRITE(_PHYCR0_, v); }
+inline void setPHYCR1(uint8_t v) { WIZCHIP_WRITE(_PHYCR1_, v); }
+inline uint8_t getPHYCR1() { return WIZCHIP_READ(_PHYCR1_); }
+inline void setNET4MR(uint8_t v) { WIZCHIP_WRITE(_NET4MR_, v); }
+inline void setNET6MR(uint8_t v) { WIZCHIP_WRITE(_NET6MR_, v); }
+inline void setNETMR(uint8_t v) { WIZCHIP_WRITE(_NETMR_, v); }
+inline void setNETMR2(uint8_t v) { WIZCHIP_WRITE(_NETMR2_, v); }
+inline uint8_t getNET4MR() { return WIZCHIP_READ(_NET4MR_); }
+inline uint8_t getNET6MR() { return WIZCHIP_READ(_NET6MR_); }
+inline uint8_t getNETMR() { return WIZCHIP_READ(_NETMR_); }
+inline uint8_t getNETMR2() { return WIZCHIP_READ(_NETMR2_); }
+inline void setPTMR(uint8_t v) { WIZCHIP_WRITE(_PTMR_, v); }
+inline uint8_t getPTMR() { return WIZCHIP_READ(_PTMR_); }
+inline void setPMNR(uint8_t v) { WIZCHIP_WRITE(_PMNR_, v); }
+inline uint8_t getPMNR() { return WIZCHIP_READ(_PMNR_); }
+inline void setPHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_PHAR_, v, 6); }
+inline void getPHAR(uint8_t* v) { WIZCHIP_READ_BUF(_PHAR_, v, 6); }
+inline void setPSIDR(uint16_t v) {
+    WIZCHIP_WRITE(_PSIDR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PSIDR_, 1), (uint8_t)v);
+}
+inline uint16_t getPSIDR() { return (((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_, 1)); }
+inline void setPMRUR(uint16_t v) {
+    WIZCHIP_WRITE(_PMRUR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PMRUR_, 1), (uint8_t)v);
+}
+inline uint16_t getPMRUR() { return (((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_, 1)); }
+inline void setSHAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SHAR_, v, 6); }
+inline void getSHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SHAR_, v, 6); }
+inline void setGAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GAR_, v, 4); }
+inline void getGAR(uint8_t* v) { WIZCHIP_READ_BUF(_GAR_, v, 4); }
+inline void setGA4R(uint8_t* v) { setGAR(v); }
+inline void getGA4R(uint8_t* v) { getGAR(v); }
+inline void setSUBR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUBR_, v, 4); }
+inline void getSUBR(uint8_t* v) { WIZCHIP_READ_BUF(_SUBR_, v, 4); }
+inline void setSUB4R(uint8_t* v) { setSUBR(v); }
+inline void getSUB4R(uint8_t* v) { getSUBR(v); }
+inline void setSIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SIPR_, v, 4); }
+inline void getSIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SIPR_, v, 4); }
+inline void setLLAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_LLAR_, v, 16); }
+inline void getLLAR(uint8_t* v) { WIZCHIP_READ_BUF(_LLAR_, v, 16); }
+inline void setGUAR(uint8_t* v) { WIZCHIP_WRITE_BUF(_GUAR_, v, 16); }
+inline void getGUAR(uint8_t* v) { WIZCHIP_READ_BUF(_GUAR_, v, 16); }
+inline void setSUB6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SUB6R_, v, 16); }
+inline void getSUB6R(uint8_t* v) { WIZCHIP_READ_BUF(_SUB6R_, v, 16); }
+inline void setGA6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_GA6R_, v, 16); }
+inline void getGA6R(uint8_t* v) { WIZCHIP_READ_BUF(_GA6R_, v, 16); }
+inline void setSLDIPR(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIPR_, v, 4); }
+inline void setSLDIP4R(uint8_t* v) { setSLDIPR(v); }
+inline void getSLDIPR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIPR_, v, 4); }
+inline void getSLDIP4R(uint8_t* v) { getSLDIPR(v); }
+inline void setSLDIP6R(uint8_t* v) { WIZCHIP_WRITE_BUF(_SLDIP6R_, v, 16); }
+inline void getSLDIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_SLDIP6R_, v, 16); }
+inline void getSLDHAR(uint8_t* v) { WIZCHIP_READ_BUF(_SLDHAR_, v, 6); }
+inline void setPINGIDR(uint16_t v) {
+    WIZCHIP_WRITE(_PINGIDR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGIDR_, 1), (uint8_t)v);
+}
+inline uint16_t getPINGIDR() { return ((uint16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_, 1)); }
+inline void setPINGSEQR(uint16_t v) {
+    WIZCHIP_WRITE(_PINGSEQR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1), (uint8_t)v);
+}
+inline uint16_t getPINGSEQR() { return ((uint16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_, 1)); }
+inline void getUIPR(uint8_t* v) { WIZCHIP_READ_BUF(_UIPR_, v, 4); }
+inline void getUIP4R(uint8_t* v) { getUIPR(v); }
+inline uint16_t getUPORTR() { return (((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_, 1)); }
+inline uint16_t getUPORT4R() { return getUPORTR(); }
+inline void getUIP6R(uint8_t* v) { WIZCHIP_READ_BUF(_UIP6R_, v, 16); }
+inline uint16_t getUPORT6R() { return (((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_, 1)); }
+inline void setINTPTMR(uint16_t v) {
+    WIZCHIP_WRITE(_INTPTMR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_INTPTMR_, 1), (uint8_t)v);
+}
+inline uint16_t getINTPTMR() { return (((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_, 1)); }
+inline uint8_t getPLR() { return WIZCHIP_READ(_PLR_); }
+inline uint8_t getPFR() { return WIZCHIP_READ(_PFR_); }
+inline uint32_t getVLTR() {
+    return (((uint32_t)WIZCHIP_READ(_VLTR_)) << 24) +
+           (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 1))) << 16) +
+           (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 2))) << 8) +
+            ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VLTR_, 3)));
+}
+inline uint32_t getPLTR() {
+    return (((uint32_t)WIZCHIP_READ(_PLTR_)) << 24) +
+           (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 1))) << 16) +
+           (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 2))) << 8) +
+            ((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PLTR_, 3)));
+}
+inline void getPAR(uint8_t* v) { WIZCHIP_READ_BUF(_PAR_, v, 16); }
+inline void setICMP6BLKR(uint8_t v) { WIZCHIP_WRITE(_ICMP6BLKR_, v); }
+inline uint8_t getICMP6BLKR() { return WIZCHIP_READ(_ICMP6BLKR_); }
+inline void setCHPLCKR(uint8_t v) { WIZCHIP_WRITE(_CHPLCKR_, v); }
+inline uint8_t getCHPLCKR() { return (getSYSR() & SYSR_CHPL) >> 7; }
+inline void CHIPLOCK() { setCHPLCKR(0xFF); }
+inline void CHIPUNLOCK() { setCHPLCKR(0xCE); }
+inline void setNETLCKR(uint8_t v) { WIZCHIP_WRITE(_NETLCKR_, v); }
+inline uint8_t getNETLCKR() { return (getSYSR() & SYSR_NETL) >> 6; }
+inline void NETLOCK() { setNETLCKR(0xC5); }
+inline void NETUNLOCK() { setNETLCKR(0x3A); }
+inline void setPHYLCKR(uint8_t v) { WIZCHIP_WRITE(_PHYLCKR_, v); }
+inline uint8_t getPHYLCKR() { return (getSYSR() & SYSR_PHYL) >> 5; }
+inline void PHYLOCK() { setPHYLCKR(0xFF); }
+inline void PHYUNLOCK() { setPHYLCKR(0x53); }
+inline void setRTR(uint16_t v) {
+    WIZCHIP_WRITE(_RTR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_, 1), (uint8_t)v);
+}
+inline uint16_t getRTR() { return (((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); }
+inline void setRCR(uint8_t v) { WIZCHIP_WRITE(_RCR_, v); }
+inline uint8_t getRCR() { return WIZCHIP_READ(_RCR_); }
+inline void setSLRTR(uint16_t v) {
+    WIZCHIP_WRITE(_SLRTR_, (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_SLRTR_, 1), (uint8_t)v);
+}
+inline uint16_t getSLRTR() { return (((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_, 1)); }
+inline void setSLRCR(uint8_t v) { WIZCHIP_WRITE(_SLRCR_, v); }
+inline uint8_t getSLRCR() { return WIZCHIP_READ(_SLRCR_); }
+inline void setSLHOPR(uint8_t v) { WIZCHIP_WRITE(_SLHOPR_, v); }
+inline uint8_t getSLHOPR() { return WIZCHIP_READ(_SLHOPR_); }
+
+inline void setSn_MR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR_(sn), v); }
+inline uint8_t getSn_MR(uint8_t sn) { return WIZCHIP_READ(_Sn_MR_(sn)); }
+inline void setSn_PSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PSR_(sn), v); }
+inline uint8_t getSn_PSR(uint8_t sn) { return WIZCHIP_READ(_Sn_PSR_(sn)); }
+inline void setSn_CR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_CR_(sn), v); }
+inline uint8_t getSn_CR(uint8_t sn) { return WIZCHIP_READ(_Sn_CR_(sn)); }
+inline uint8_t getSn_IR(uint8_t sn) { return WIZCHIP_READ(_Sn_IR_(sn)); }
+inline void setSn_IMR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IMR_(sn), v); }
+inline uint8_t getSn_IMR(uint8_t sn) { return WIZCHIP_READ(_Sn_IMR_(sn)); }
+inline void setSn_IRCLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_IRCLR_(sn), v); }
+inline void setSn_IR(uint8_t sn, uint8_t v) { setSn_IRCLR(sn, v); }
+inline uint8_t getSn_SR(uint8_t sn) { return WIZCHIP_READ(_Sn_SR_(sn)); }
+inline uint8_t getSn_ESR(uint8_t sn) { return WIZCHIP_READ(_Sn_ESR_(sn)); }
+inline void setSn_PNR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_PNR_(sn), v); }
+inline void setSn_NHR(uint8_t sn, uint8_t v) { setSn_PNR(sn, v); }
+inline uint8_t getSn_PNR(uint8_t sn) { return WIZCHIP_READ(_Sn_PNR_(sn)); }
+inline uint8_t getSn_NHR(uint8_t sn) { return getSn_PNR(sn); }
+inline void setSn_TOSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TOSR_(sn), v); }
+inline uint8_t getSn_TOSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TOSR_(sn)); }
+inline uint8_t getSn_TOS(uint8_t sn) { return getSn_TOSR(sn); }
+inline void setSn_TOS(uint8_t sn, uint8_t v) { setSn_TOSR(sn, v); }
+inline void setSn_TTLR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TTLR_(sn), v); }
+inline uint8_t getSn_TTLR(uint8_t sn) { return WIZCHIP_READ(_Sn_TTLR_(sn)); }
+inline void setSn_TTL(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); }
+inline uint8_t getSn_TTL(uint8_t sn) { return getSn_TTLR(sn); }
+inline void setSn_HOPR(uint8_t sn, uint8_t v) { setSn_TTLR(sn, v); }
+inline uint8_t getSn_HOPR(uint8_t sn) { return getSn_TTLR(sn); }
+inline void setSn_FRGR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_FRGR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_FRGR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn), 1)); }
+inline void setSn_MSSR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_MSSR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_MSSR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn), 1)); }
+inline void setSn_PORTR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_PORTR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_PORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn), 1)); }
+inline void setSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn), v, 6); }
+inline void getSn_DHAR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DHAR_(sn), v, 6); }
+inline void setSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn), v, 4); }
+inline void getSn_DIPR(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIPR_(sn), v, 4); }
+inline void setSn_DIP4R(uint8_t sn, uint8_t* v) { setSn_DIPR(sn, v); }
+inline void getSn_DIP4R(uint8_t sn, uint8_t* v) { getSn_DIPR(sn, v); }
+inline void setSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn), v, 16); }
+inline void getSn_DIP6R(uint8_t sn, uint8_t* v) { WIZCHIP_READ_BUF(_Sn_DIP6R_(sn), v, 16); }
+inline void setSn_DPORTR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_DPORTR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_DPORTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn), 1)); }
+inline uint16_t getSn_DPORT(uint8_t sn) { return getSn_DPORTR(sn); }
+inline void setSn_DPORT(uint8_t sn, uint16_t v) { setSn_DPORTR(sn, v); }
+inline void setSn_MR2(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_MR2_(sn), v); }
+inline uint8_t getSn_MR2(uint8_t sn) { return WIZCHIP_READ(_Sn_MR2_(sn)); }
+inline void setSn_RTR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_RTR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_RTR(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn), 1)); }
+inline void setSn_RCR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RCR_(sn), v); }
+inline uint8_t getSn_RCR(uint8_t sn) { return WIZCHIP_READ(_Sn_RCR_(sn)); }
+inline void setSn_KPALVTR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_KPALVTR_(sn), v); }
+inline uint8_t getSn_KPALVTR(uint8_t sn) { return WIZCHIP_READ(_Sn_KPALVTR_(sn)); }
+inline void setSn_TX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_TX_BSR_(sn), v); }
+inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_TX_BSR(sn, v); }
+inline uint8_t getSn_TX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_TX_BSR_(sn)); }
+inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) { return getSn_TX_BSR(sn); }
+inline uint16_t getSn_TxMAX(uint8_t sn) { return getSn_TX_BSR(sn) << 10; }
 
 uint16_t getSn_TX_FSR(uint8_t sn);
 
-#define getSn_TX_RD(sn) \
-        ((((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn),1)))
-
-#define setSn_TX_WR(sn,txwr) \
-        do{                                                                       \
-            WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)((txwr)>>8));                  \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1), (uint8_t)(txwr)); \
-        }while(0);
-#define getSn_TX_WR(sn) \
-        (((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1)))
-
-#define setSn_RX_BSR(sn,rmsr) \
-        WIZCHIP_WRITE(_Sn_RX_BSR_(sn),(rmsr))
-#define setSn_RXBUF_SIZE(sn,rmsr)      setSn_RX_BSR(sn,(rmsr))
-
-#define getSn_RX_BSR(sn) \
-        WIZCHIP_READ(_Sn_RX_BSR_(sn))
-#define getSn_RXBUF_SIZE(sn)           getSn_RX_BSR(sn)
-
-#define getSn_RxMAX(sn) \
-        (getSn_RX_BSR(sn) <<10)
+inline uint16_t getSn_TX_RD(uint8_t sn) { return (((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn), 1)); }
+inline void setSn_TX_WR(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_TX_WR_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_TX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn), 1)); }
+inline void setSn_RX_BSR(uint8_t sn, uint8_t v) { WIZCHIP_WRITE(_Sn_RX_BSR_(sn), v); }
+inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t v) { setSn_RX_BSR(sn, v); }
+inline uint8_t getSn_RX_BSR(uint8_t sn) { return WIZCHIP_READ(_Sn_RX_BSR_(sn)); }
+inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) { return getSn_RX_BSR(sn); }
+inline uint16_t getSn_RxMAX(uint8_t sn) { return getSn_RX_BSR(sn) << 10; }
 
 uint16_t getSn_RX_RSR(uint8_t s);
 
-#define setSn_RX_RD(sn,rxrd) \
-        do{                                                                        \
-            WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)((rxrd)>>8));                   \
-            WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1), (uint8_t)(rxrd)) ; \
-        }while(0);
-
-#define getSn_RX_RD(sn) \
-        (((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1)))
-
-#define getSn_RX_WR(sn) \
-        (((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn),1)))
+inline void setSn_RX_RD(uint8_t sn, uint16_t v) {
+    WIZCHIP_WRITE(_Sn_RX_RD_(sn), (uint8_t)(v >> 8));
+    WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1), (uint8_t)v);
+}
+inline uint16_t getSn_RX_RD(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn), 1)); }
+inline uint16_t getSn_RX_WR(uint8_t sn) { return ((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn), 1)); }
 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
 void wiz_recv_ignore(uint8_t sn, uint16_t len);
 void wiz_delay_ms(uint32_t ms);
 
-#if (_PHY_IO_MODE_ == _PHY_IO_MODE_MII_)
 void wiz_mdio_write(uint8_t phyregaddr, uint16_t var);
 uint16_t wiz_mdio_read(uint8_t phyregaddr);
-#endif
 
diff --git a/w6300/wizchip_conf.h b/w6300/wizchip_conf.h
index f329459..0e410ad 100644
--- a/w6300/wizchip_conf.h
+++ b/w6300/wizchip_conf.h
@@ -1,14 +1,13 @@
 #pragma once
 #include <cstdint>
 
-#define W6300 6300
-#define _WIZCHIP_ W6300
+constexpr int _WIZCHIP_ = 6300;
 
-#define _PHY_IO_MODE_PHYCR_            0x0000
-#define _PHY_IO_MODE_MII_              0x0010
-#define _PHY_IO_MODE_                  _PHY_IO_MODE_MII_
+constexpr uint16_t _PHY_IO_MODE_PHYCR_ = 0x0000;
+constexpr uint16_t _PHY_IO_MODE_MII_   = 0x0010;
+constexpr uint16_t _PHY_IO_MODE_       = _PHY_IO_MODE_MII_;
 
-#define _WIZCHIP_QSPI_MODE_           (0x02 << 6)
+constexpr uint8_t _WIZCHIP_QSPI_MODE_ = 0x02 << 6;
 
 using iodata_t = uint8_t;
 using datasize_t = int16_t;
@@ -16,7 +15,7 @@ using datasize_t = int16_t;
 #include "w6300.h"
 
 constexpr int WIZCHIP_SOCK_NUM = 8;
-#define _WIZCHIP_SOCK_NUM_ WIZCHIP_SOCK_NUM
+constexpr int _WIZCHIP_SOCK_NUM_ = WIZCHIP_SOCK_NUM;
 
 enum ctlwizchip_type {
     CW_SYS_LOCK, CW_SYS_UNLOCK, CW_GET_SYSLOCK,