4.1 KiB
Current state
Committed tree
AF_PACKET raw sockets everywhere (sock.go), flow-director steering, read-time-stamped rate buckets, framebuffer UI, harness. The zero-copy AF_XDP conversion (both directions, hand-rolled XSK + hand-assembled XDP program, per-frame MAC-stamp buckets via rx metadata) lives uncommitted in stash@{0}; it was built for the era when the test path ran on the E810, whose datapath delivers per-packet MAC timestamps. It is an experiment, not a requirement.
stash@{1} holds the phydiag campaign: python transport clients (i40e_aq.py, rollball_i40e.py, sff.py), scanners, and a STATUS.md campaign log. Working copies extracted to ~/work/phydiag-work/ during the module work. The knowledge from that campaign is now in these docs; the code should eventually move into the repo properly.
Hardware in flight
- Intel X520-DA2 ordered — replaces the E810 in the box's single PCIe slot. Chosen because ixgbe bit-bangs module I2C from the host (no firmware policy layer), enabling in-product module-PHY diagnostics; see transports.md.
- Replacement Wiitek (Marvell CUX3610) modules ordered. Both original units were bricked by register exploration — see modules.md for the trap before ever touching one.
- In hand (all copper RJ45 10GBASE-T modules with cloned/lying fiber EEPROMs — see hardware.md; none are actually fiber):
- 2× FS SFP-10G-T-100 (Broadcom BCM84891L, fully documented diagnostics).
- 1× Fibergaga SFP-10G-T-30M (Aquantia, RollBall, the proven oracle module).
- 1× 10Gtek, EEPROM claims SFP-10G-SR — still a copper RJ45 module; filler, not part of the test set.
X520 prep — built ahead of the card, untested (no hardware yet)
In ~/work/ alongside the ice-sff/phydiag-work artifacts, ready to fold into the repo's kernel/ once validated on real hardware:
- Patched ixgbe (
~/work/ixgbe-sff/, built against the running kernel, vermagic matches): addsixgbe_i2c_raw_write/ixgbe_i2c_raw_readinixgbe_phy.c(arbitrary START…STOP transactions built from the existing bit-bang primitives, swfw-semaphore bracketed) and ansff_i2cdebugfs file withw <addr8> <bytes…>/r <addr8> <n>commands, result read back from the fd. Modeled on the proven icesff_i2c; ixgbe has no firmware to refuse, so arbitrary framing works.load-ixgberebuilds + swaps the module. - BCM client (
~/work/phydiag-work/bcm_ixgbe.py): BCM SMI framing on those two ops (read = write[001+devad,RegH,RegL], >1 ms delay, read 2 B; write = 5-byte frame) plus the full command handler (_wait_idle→ DATA → CMD|bit15 → poll PASS/ERROR → read DATA),CMD_GET_SNRdecoded to per-pair dB, and EEPROM/PHY-ID/STATUS sanity reads. The same two ops compose RollBall for the Wiiteks.
Bringup plan when the X520 arrives
- Install card, move FS modules in,
./load-ixgbe, confirmsff_i2cappears. - FS/BCM modules first:
bcm_ixgbe.pysanity reads (EEPROM, PHY ID, STATUS) to prove the SMI transport, then the command handler (CMD_GET_SNR vs the IEEE registers) on the test cable set. - Replacement Wiiteks: IEEE-standard registers only (SNR, latches) unless/until a documented recipe exists for more; the VCT templates in modules.md are candidates for single-shot targeted probes on a sacrificial unit only.
- Re-derive host tuning on ixgbe (coalescing/ring syntax differs) and re-verify the rxnfc flow-steering code against ixgbe's fdir.
Open items
- ECD register chapter: the one missing document for BCM cable length. FS has been responsive; the narrow ask is "which registers invoke ECD / report the DSP cable-length estimate, and does it run with link up?"
- Pre-FEC classification on the Aquantia (3.e820): needs a marginal channel; cabletest's noise stress will provide one once diagnostics are integrated.
- X710 PTP path-delay length measurement: viable fallback for linked-cable length (PTP-latch timestamps both ports, same oscillator, 1 ft calibration cancels PHY latency); scoped but unbuilt. Superseded for the product if BCM ECD/DSP length pans out.
- E810 leaves the box when the X520 arrives; the patched ice +
sff_i2cremains useful only if an E810 returns for read-side work.