Nothing lives outside the repo: the bench ixgbe driver source moves in tracked at kernel/ixgbe-sff/ (build artifacts gitignored, load-ixgbe repointed, module build verified from the new home — the reg_ops/ts_bench bench extras are finally versioned), the ice sff_i2c patch is vendored at docs/nics/e810/ice-sff-i2c.patch with its out-of-tree build recipe (TRACE_INCLUDE_PATH fixup, version-matched Makefile), the e810 NVM flash logistics land in the e810 README (exact package name, rollback -m B49691D578EC into the inactive bank, post-flash inventory failing until power cycle is the expected tell), and every ~/work/phydiag-work pointer becomes an inline statement; phydiag-work, ice-sff, e810nvm and the wiitekphy CLI (a duplicate of documented transport+protocol) are deleted
This commit is contained in:
flamingcow
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#include "ixgbe.h"
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82598.h"
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/**
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* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Rx Data Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *prio_type)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
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IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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/* Enable Arbiter */
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reg &= ~IXGBE_RMCS_ARBDIS;
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/* Enable Receive Recycle within the BWG */
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reg |= IXGBE_RMCS_RRM;
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/* Enable Deficit Fixed Priority arbitration*/
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reg |= IXGBE_RMCS_DFP;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RT2CR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
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}
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reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
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reg |= IXGBE_RDRXCTL_RDMTS_1_2;
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reg |= IXGBE_RDRXCTL_MPBEN;
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reg |= IXGBE_RDRXCTL_MCEN;
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IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
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/* Make sure there is enough descriptors before arbitration */
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reg &= ~IXGBE_RXCTRL_DMBYPS;
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type)
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{
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u32 reg, max_credits;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
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/* Enable arbiter */
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reg &= ~IXGBE_DPMCS_ARBDIS;
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reg |= IXGBE_DPMCS_TSOEF;
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/* Configure Max TSO packet size 34KB including payload and headers */
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reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_TDTQ2TCCR_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_TDTQ2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Tx Data Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type)
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{
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u32 reg;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
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/* Enable Data Plane Arbiter */
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reg &= ~IXGBE_PDPMCS_ARBDIS;
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/* Enable DFP and Transmit Recycle Mode */
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reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
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IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_TDPT2TCCR_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_TDPT2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
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}
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/* Enable Tx packet buffer division */
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reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
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reg |= IXGBE_DTXCTL_ENDBUBD;
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IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_pfc_82598 - Config priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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*
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* Configure Priority Flow Control for each traffic class.
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*/
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int ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
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{
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u32 fcrtl, reg;
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u8 i;
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/* Enable Transmit Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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reg &= ~IXGBE_RMCS_TFCE_802_3X;
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reg |= IXGBE_RMCS_TFCE_PRIORITY;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Enable Receive Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
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if (pfc_en)
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reg |= IXGBE_FCTRL_RPFCE;
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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if (!(pfc_en & BIT(i))) {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
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continue;
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}
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
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}
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/* Configure pause time */
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reg = hw->fc.pause_time * 0x00010001;
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for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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static int ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
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{
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u32 reg = 0;
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u8 i = 0;
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u8 j = 0;
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/* Receive Queues stats setting - 8 queues per statistics reg */
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for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
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}
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/* Transmit Queues stats setting - 4 queues per statistics reg */
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for (i = 0; i < 8; i++) {
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reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
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reg |= ((0x1010101) * i);
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IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_hw_config_82598 - Config and enable DCB
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure dcb settings and enable dcb mode.
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*/
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int ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type)
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{
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ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
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ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_pfc_82598(hw, pfc_en);
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ixgbe_dcb_config_tc_stats_82598(hw);
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return 0;
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}
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