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X520 returns as product NIC: smoothed-bucket rate plan (read-time buckets, backward excess-fill, rate as headline not verdict) dissolves the per-frame RX timestamp requirement; CX-5 retired with full record (MCIA via VSC/ICMD proven, fwctl write-block, card-global module index, ~150ms mailbox quantum unexplained, FS link deadlock); E810 below-AQ bit-bang idea recorded and retired; FS+Wiitek pair and length return as goals

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flamingcow
2026-08-16 22:02:04 -07:00
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docs/modules/fs/README.md
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@@ -16,6 +16,16 @@ PHY at I2C 8-bit **0xAC write / 0xAD read**.
- Single-byte reads see the bridge as inert (returns 0) — the DevAD-prefixed frame + delay is mandatory. This is why early probing wrongly declared 0x56 dead. Treat 0x0000 reads as retry-with-longer-delay: 0 is also the bridge's not-ready signature.
- Recorded for a future multi-byte firmware transport (mlx5 MCIA shape): read = write `[001+devad,RegH,RegL]` offset_size=1, STOP, >1 ms, read 2 B offset_size=0; write = offset_size=2, addr = devad<<8|RegH, data = `[RegL,DataH,DataL]`.
## Host interface (XFI) bring-up gating
**The module never enables its XFI TX toward the host until it receives valid host signal** — observed live on the ConnectX-5, where it produces a mutual-wait deadlock ([../../nics/connectx-5/README.md](../../nics/connectx-5/README.md)):
- While ungated it asserts RX_LOS (the SFP pin and A2h byte 110 bit 1 both) and its host-side TX is electrically dark (NIC RX eye grade 0). The copper side is independent: it trains and holds link normally the whole time, so RX_LOS here means "no host signal", not "no copper link".
- The gate is PCS-qualified, not analog: PRBS31 and electrical-idle patterns at 10.3125G into the module do not clear it — only valid 10GBASE-R does. Hosts that emit SFI idles from driver load (ixgbe) never see any of this.
- With its host side dead and copper trained, the module signals fault over the copper; the far-end module relays it to its own host as remote-fault ordered sets (the far end's tell that this end's host interface is down).
- Not a path to the gate: PMA soft reset (1.0.15, self-clearing — copper retrains, host TX stays dark), KR mode (SET 0x800F PASSes, no host TX with or without AN restart; GET 0x800E is a DATA1-answer readback, unusable), the LED controller (1.0xA83B = 0x8400, 1.0xA83C = 0x00E1; rewriting either does not move the RX_LOS pin — the pin is not LED-sourced). All of it survived un-bricked, values restored.
- A0h byte 36 = 0x1C (10GBASE-T Short Reach) is the honest class declaration; power is not the issue (A0h byte 64 = 0x00 declares no high-power-level mechanism; A2h 92–94 are filler bytes).
## MDIO command handler
Protocol and full verified catalog: [bcm84891l-mdio-commands.md](bcm84891l-mdio-commands.md). Traps: